12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later
2732fdf0eSGiuseppe CAVALLARO /*
3d15891caSSrinivas Kandagatla * dwmac-sti.c - STMicroelectronics DWMAC Specific Glue layer
4d15891caSSrinivas Kandagatla *
5d15891caSSrinivas Kandagatla * Copyright (C) 2003-2014 STMicroelectronics (R&D) Limited
6d15891caSSrinivas Kandagatla * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
753b26b9bSGiuseppe CAVALLARO * Contributors: Giuseppe Cavallaro <peppe.cavallaro@st.com>
8d15891caSSrinivas Kandagatla */
9d15891caSSrinivas Kandagatla
10d15891caSSrinivas Kandagatla #include <linux/kernel.h>
11d15891caSSrinivas Kandagatla #include <linux/slab.h>
12d15891caSSrinivas Kandagatla #include <linux/platform_device.h>
13d15891caSSrinivas Kandagatla #include <linux/stmmac.h>
14d15891caSSrinivas Kandagatla #include <linux/phy.h>
15d15891caSSrinivas Kandagatla #include <linux/mfd/syscon.h>
162a321798SJoachim Eastwood #include <linux/module.h>
17d15891caSSrinivas Kandagatla #include <linux/regmap.h>
18d15891caSSrinivas Kandagatla #include <linux/clk.h>
19d15891caSSrinivas Kandagatla #include <linux/of.h>
20d15891caSSrinivas Kandagatla #include <linux/of_net.h>
21d15891caSSrinivas Kandagatla
22f10f9fb2SAndy Shevchenko #include "stmmac_platform.h"
23f10f9fb2SAndy Shevchenko
2453b26b9bSGiuseppe CAVALLARO #define DWMAC_125MHZ 125000000
2553b26b9bSGiuseppe CAVALLARO #define DWMAC_50MHZ 50000000
2653b26b9bSGiuseppe CAVALLARO #define DWMAC_25MHZ 25000000
2753b26b9bSGiuseppe CAVALLARO #define DWMAC_2_5MHZ 2500000
2853b26b9bSGiuseppe CAVALLARO
2953b26b9bSGiuseppe CAVALLARO #define IS_PHY_IF_MODE_RGMII(iface) (iface == PHY_INTERFACE_MODE_RGMII || \
3053b26b9bSGiuseppe CAVALLARO iface == PHY_INTERFACE_MODE_RGMII_ID || \
3153b26b9bSGiuseppe CAVALLARO iface == PHY_INTERFACE_MODE_RGMII_RXID || \
3253b26b9bSGiuseppe CAVALLARO iface == PHY_INTERFACE_MODE_RGMII_TXID)
3353b26b9bSGiuseppe CAVALLARO
3453b26b9bSGiuseppe CAVALLARO #define IS_PHY_IF_MODE_GBIT(iface) (IS_PHY_IF_MODE_RGMII(iface) || \
3553b26b9bSGiuseppe CAVALLARO iface == PHY_INTERFACE_MODE_GMII)
3653b26b9bSGiuseppe CAVALLARO
3714cac662SAlain Volmat /* STiH4xx register definitions (STiH407/STiH410 families)
38732fdf0eSGiuseppe CAVALLARO *
39d15891caSSrinivas Kandagatla * Below table summarizes the clock requirement and clock sources for
40d15891caSSrinivas Kandagatla * supported phy interface modes with link speeds.
41d15891caSSrinivas Kandagatla * ________________________________________________
42d15891caSSrinivas Kandagatla *| PHY_MODE | 1000 Mbit Link | 100 Mbit Link |
43d15891caSSrinivas Kandagatla * ------------------------------------------------
44d15891caSSrinivas Kandagatla *| MII | n/a | 25Mhz |
45d15891caSSrinivas Kandagatla *| | | txclk |
46d15891caSSrinivas Kandagatla * ------------------------------------------------
47d15891caSSrinivas Kandagatla *| GMII | 125Mhz | 25Mhz |
48d15891caSSrinivas Kandagatla *| | clk-125/txclk | txclk |
49d15891caSSrinivas Kandagatla * ------------------------------------------------
50d15891caSSrinivas Kandagatla *| RGMII | 125Mhz | 25Mhz |
51d15891caSSrinivas Kandagatla *| | clk-125/txclk | clkgen |
5253b26b9bSGiuseppe CAVALLARO *| | clkgen | |
53d15891caSSrinivas Kandagatla * ------------------------------------------------
54d15891caSSrinivas Kandagatla *| RMII | n/a | 25Mhz |
55d15891caSSrinivas Kandagatla *| | |clkgen/phyclk-in |
56d15891caSSrinivas Kandagatla * ------------------------------------------------
57d15891caSSrinivas Kandagatla *
5853b26b9bSGiuseppe CAVALLARO * Register Configuration
5953b26b9bSGiuseppe CAVALLARO *-------------------------------
6053b26b9bSGiuseppe CAVALLARO * src |BIT(8)| BIT(7)| BIT(6)|
6153b26b9bSGiuseppe CAVALLARO *-------------------------------
62d15891caSSrinivas Kandagatla * txclk | 0 | n/a | 1 |
6353b26b9bSGiuseppe CAVALLARO *-------------------------------
64d15891caSSrinivas Kandagatla * ck_125| 0 | n/a | 0 |
6553b26b9bSGiuseppe CAVALLARO *-------------------------------
66d15891caSSrinivas Kandagatla * phyclk| 1 | 0 | n/a |
6753b26b9bSGiuseppe CAVALLARO *-------------------------------
68d15891caSSrinivas Kandagatla * clkgen| 1 | 1 | n/a |
6953b26b9bSGiuseppe CAVALLARO *-------------------------------
70d15891caSSrinivas Kandagatla */
71d15891caSSrinivas Kandagatla
7253b26b9bSGiuseppe CAVALLARO #define STIH4XX_RETIME_SRC_MASK GENMASK(8, 6)
7353b26b9bSGiuseppe CAVALLARO #define STIH4XX_ETH_SEL_TX_RETIME_CLK BIT(8)
7453b26b9bSGiuseppe CAVALLARO #define STIH4XX_ETH_SEL_INTERNAL_NOTEXT_PHYCLK BIT(7)
7553b26b9bSGiuseppe CAVALLARO #define STIH4XX_ETH_SEL_TXCLK_NOT_CLK125 BIT(6)
76d15891caSSrinivas Kandagatla
77d15891caSSrinivas Kandagatla #define ENMII_MASK GENMASK(5, 5)
78d15891caSSrinivas Kandagatla #define ENMII BIT(5)
7953b26b9bSGiuseppe CAVALLARO #define EN_MASK GENMASK(1, 1)
8053b26b9bSGiuseppe CAVALLARO #define EN BIT(1)
81d15891caSSrinivas Kandagatla
82732fdf0eSGiuseppe CAVALLARO /*
83d15891caSSrinivas Kandagatla * 3 bits [4:2]
84d15891caSSrinivas Kandagatla * 000-GMII/MII
85d15891caSSrinivas Kandagatla * 001-RGMII
86d15891caSSrinivas Kandagatla * 010-SGMII
87d15891caSSrinivas Kandagatla * 100-RMII
88d15891caSSrinivas Kandagatla */
89d15891caSSrinivas Kandagatla #define MII_PHY_SEL_MASK GENMASK(4, 2)
90d15891caSSrinivas Kandagatla #define ETH_PHY_SEL_RMII BIT(4)
91d15891caSSrinivas Kandagatla #define ETH_PHY_SEL_SGMII BIT(3)
92d15891caSSrinivas Kandagatla #define ETH_PHY_SEL_RGMII BIT(2)
93d15891caSSrinivas Kandagatla #define ETH_PHY_SEL_GMII 0x0
94d15891caSSrinivas Kandagatla #define ETH_PHY_SEL_MII 0x0
95d15891caSSrinivas Kandagatla
96d15891caSSrinivas Kandagatla struct sti_dwmac {
970c65b2b9SAndrew Lunn phy_interface_t interface; /* MII interface */
9853b26b9bSGiuseppe CAVALLARO bool ext_phyclk; /* Clock from external PHY */
9953b26b9bSGiuseppe CAVALLARO u32 tx_retime_src; /* TXCLK Retiming*/
10053b26b9bSGiuseppe CAVALLARO struct clk *clk; /* PHY clock */
1019b1a6d36SPeter Griffin u32 ctrl_reg; /* GMAC glue-logic control register */
10253b26b9bSGiuseppe CAVALLARO int clk_sel_reg; /* GMAC ext clk selection register */
103d15891caSSrinivas Kandagatla struct regmap *regmap;
10406a6e829SJoachim Eastwood bool gmac_en;
10553b26b9bSGiuseppe CAVALLARO u32 speed;
106*1fc04a0bSShenwei Wang void (*fix_retime_src)(void *priv, unsigned int speed, unsigned int mode);
107d15891caSSrinivas Kandagatla };
108d15891caSSrinivas Kandagatla
10907ca3749SJoachim Eastwood struct sti_dwmac_of_data {
110*1fc04a0bSShenwei Wang void (*fix_retime_src)(void *priv, unsigned int speed, unsigned int mode);
11107ca3749SJoachim Eastwood };
11207ca3749SJoachim Eastwood
113d15891caSSrinivas Kandagatla static u32 phy_intf_sels[] = {
114d15891caSSrinivas Kandagatla [PHY_INTERFACE_MODE_MII] = ETH_PHY_SEL_MII,
115d15891caSSrinivas Kandagatla [PHY_INTERFACE_MODE_GMII] = ETH_PHY_SEL_GMII,
116d15891caSSrinivas Kandagatla [PHY_INTERFACE_MODE_RGMII] = ETH_PHY_SEL_RGMII,
117d15891caSSrinivas Kandagatla [PHY_INTERFACE_MODE_RGMII_ID] = ETH_PHY_SEL_RGMII,
118d15891caSSrinivas Kandagatla [PHY_INTERFACE_MODE_SGMII] = ETH_PHY_SEL_SGMII,
119d15891caSSrinivas Kandagatla [PHY_INTERFACE_MODE_RMII] = ETH_PHY_SEL_RMII,
120d15891caSSrinivas Kandagatla };
121d15891caSSrinivas Kandagatla
122d15891caSSrinivas Kandagatla enum {
123d15891caSSrinivas Kandagatla TX_RETIME_SRC_NA = 0,
124d15891caSSrinivas Kandagatla TX_RETIME_SRC_TXCLK = 1,
125d15891caSSrinivas Kandagatla TX_RETIME_SRC_CLK_125,
126d15891caSSrinivas Kandagatla TX_RETIME_SRC_PHYCLK,
127d15891caSSrinivas Kandagatla TX_RETIME_SRC_CLKGEN,
128d15891caSSrinivas Kandagatla };
129d15891caSSrinivas Kandagatla
13053b26b9bSGiuseppe CAVALLARO static u32 stih4xx_tx_retime_val[] = {
13153b26b9bSGiuseppe CAVALLARO [TX_RETIME_SRC_TXCLK] = STIH4XX_ETH_SEL_TXCLK_NOT_CLK125,
132d15891caSSrinivas Kandagatla [TX_RETIME_SRC_CLK_125] = 0x0,
13353b26b9bSGiuseppe CAVALLARO [TX_RETIME_SRC_PHYCLK] = STIH4XX_ETH_SEL_TX_RETIME_CLK,
13453b26b9bSGiuseppe CAVALLARO [TX_RETIME_SRC_CLKGEN] = STIH4XX_ETH_SEL_TX_RETIME_CLK
13553b26b9bSGiuseppe CAVALLARO | STIH4XX_ETH_SEL_INTERNAL_NOTEXT_PHYCLK,
136d15891caSSrinivas Kandagatla };
137d15891caSSrinivas Kandagatla
stih4xx_fix_retime_src(void * priv,u32 spd,unsigned int mode)138*1fc04a0bSShenwei Wang static void stih4xx_fix_retime_src(void *priv, u32 spd, unsigned int mode)
139d15891caSSrinivas Kandagatla {
14053b26b9bSGiuseppe CAVALLARO struct sti_dwmac *dwmac = priv;
14153b26b9bSGiuseppe CAVALLARO u32 src = dwmac->tx_retime_src;
14253b26b9bSGiuseppe CAVALLARO u32 reg = dwmac->ctrl_reg;
14353b26b9bSGiuseppe CAVALLARO u32 freq = 0;
144d15891caSSrinivas Kandagatla
14553b26b9bSGiuseppe CAVALLARO if (dwmac->interface == PHY_INTERFACE_MODE_MII) {
146d15891caSSrinivas Kandagatla src = TX_RETIME_SRC_TXCLK;
147d15891caSSrinivas Kandagatla } else if (dwmac->interface == PHY_INTERFACE_MODE_RMII) {
148d15891caSSrinivas Kandagatla if (dwmac->ext_phyclk) {
149d15891caSSrinivas Kandagatla src = TX_RETIME_SRC_PHYCLK;
150d15891caSSrinivas Kandagatla } else {
151d15891caSSrinivas Kandagatla src = TX_RETIME_SRC_CLKGEN;
15253b26b9bSGiuseppe CAVALLARO freq = DWMAC_50MHZ;
153d15891caSSrinivas Kandagatla }
154d15891caSSrinivas Kandagatla } else if (IS_PHY_IF_MODE_RGMII(dwmac->interface)) {
15553b26b9bSGiuseppe CAVALLARO /* On GiGa clk source can be either ext or from clkgen */
15653b26b9bSGiuseppe CAVALLARO if (spd == SPEED_1000) {
15753b26b9bSGiuseppe CAVALLARO freq = DWMAC_125MHZ;
15853b26b9bSGiuseppe CAVALLARO } else {
15953b26b9bSGiuseppe CAVALLARO /* Switch to clkgen for these speeds */
160d15891caSSrinivas Kandagatla src = TX_RETIME_SRC_CLKGEN;
16153b26b9bSGiuseppe CAVALLARO if (spd == SPEED_100)
16253b26b9bSGiuseppe CAVALLARO freq = DWMAC_25MHZ;
16353b26b9bSGiuseppe CAVALLARO else if (spd == SPEED_10)
16453b26b9bSGiuseppe CAVALLARO freq = DWMAC_2_5MHZ;
16553b26b9bSGiuseppe CAVALLARO }
166d15891caSSrinivas Kandagatla }
167d15891caSSrinivas Kandagatla
168b211aa65SJoachim Eastwood if (src == TX_RETIME_SRC_CLKGEN && freq)
169d15891caSSrinivas Kandagatla clk_set_rate(dwmac->clk, freq);
170d15891caSSrinivas Kandagatla
17153b26b9bSGiuseppe CAVALLARO regmap_update_bits(dwmac->regmap, reg, STIH4XX_RETIME_SRC_MASK,
17253b26b9bSGiuseppe CAVALLARO stih4xx_tx_retime_val[src]);
173d15891caSSrinivas Kandagatla }
174d15891caSSrinivas Kandagatla
sti_dwmac_set_mode(struct sti_dwmac * dwmac)1750eebedc2SJoachim Eastwood static int sti_dwmac_set_mode(struct sti_dwmac *dwmac)
17653b26b9bSGiuseppe CAVALLARO {
17753b26b9bSGiuseppe CAVALLARO struct regmap *regmap = dwmac->regmap;
17853b26b9bSGiuseppe CAVALLARO int iface = dwmac->interface;
17953b26b9bSGiuseppe CAVALLARO u32 reg = dwmac->ctrl_reg;
18053b26b9bSGiuseppe CAVALLARO u32 val;
18153b26b9bSGiuseppe CAVALLARO
18206a6e829SJoachim Eastwood if (dwmac->gmac_en)
18353b26b9bSGiuseppe CAVALLARO regmap_update_bits(regmap, reg, EN_MASK, EN);
18453b26b9bSGiuseppe CAVALLARO
18553b26b9bSGiuseppe CAVALLARO regmap_update_bits(regmap, reg, MII_PHY_SEL_MASK, phy_intf_sels[iface]);
18653b26b9bSGiuseppe CAVALLARO
18753b26b9bSGiuseppe CAVALLARO val = (iface == PHY_INTERFACE_MODE_REVMII) ? 0 : ENMII;
18853b26b9bSGiuseppe CAVALLARO regmap_update_bits(regmap, reg, ENMII_MASK, val);
18953b26b9bSGiuseppe CAVALLARO
190*1fc04a0bSShenwei Wang dwmac->fix_retime_src(dwmac, dwmac->speed, 0);
19153b26b9bSGiuseppe CAVALLARO
19253b26b9bSGiuseppe CAVALLARO return 0;
193d15891caSSrinivas Kandagatla }
194d15891caSSrinivas Kandagatla
sti_dwmac_parse_data(struct sti_dwmac * dwmac,struct platform_device * pdev)195d15891caSSrinivas Kandagatla static int sti_dwmac_parse_data(struct sti_dwmac *dwmac,
196d15891caSSrinivas Kandagatla struct platform_device *pdev)
197d15891caSSrinivas Kandagatla {
198d15891caSSrinivas Kandagatla struct resource *res;
199d15891caSSrinivas Kandagatla struct device *dev = &pdev->dev;
200d15891caSSrinivas Kandagatla struct device_node *np = dev->of_node;
201d15891caSSrinivas Kandagatla struct regmap *regmap;
202d15891caSSrinivas Kandagatla int err;
203d15891caSSrinivas Kandagatla
20453b26b9bSGiuseppe CAVALLARO /* clk selection from extra syscfg register */
20553b26b9bSGiuseppe CAVALLARO dwmac->clk_sel_reg = -ENXIO;
20653b26b9bSGiuseppe CAVALLARO res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sti-clkconf");
20753b26b9bSGiuseppe CAVALLARO if (res)
20853b26b9bSGiuseppe CAVALLARO dwmac->clk_sel_reg = res->start;
209d15891caSSrinivas Kandagatla
210d15891caSSrinivas Kandagatla regmap = syscon_regmap_lookup_by_phandle(np, "st,syscon");
211d15891caSSrinivas Kandagatla if (IS_ERR(regmap))
212d15891caSSrinivas Kandagatla return PTR_ERR(regmap);
213d15891caSSrinivas Kandagatla
2149b1a6d36SPeter Griffin err = of_property_read_u32_index(np, "st,syscon", 1, &dwmac->ctrl_reg);
2159b1a6d36SPeter Griffin if (err) {
2169b1a6d36SPeter Griffin dev_err(dev, "Can't get sysconfig ctrl offset (%d)\n", err);
2179b1a6d36SPeter Griffin return err;
2189b1a6d36SPeter Griffin }
2199b1a6d36SPeter Griffin
2200c65b2b9SAndrew Lunn err = of_get_phy_mode(np, &dwmac->interface);
2210c65b2b9SAndrew Lunn if (err && err != -ENODEV) {
2220c65b2b9SAndrew Lunn dev_err(dev, "Can't get phy-mode\n");
2230c65b2b9SAndrew Lunn return err;
2240c65b2b9SAndrew Lunn }
2250c65b2b9SAndrew Lunn
226d15891caSSrinivas Kandagatla dwmac->regmap = regmap;
22706a6e829SJoachim Eastwood dwmac->gmac_en = of_property_read_bool(np, "st,gmac_en");
228d15891caSSrinivas Kandagatla dwmac->ext_phyclk = of_property_read_bool(np, "st,ext-phyclk");
22953b26b9bSGiuseppe CAVALLARO dwmac->tx_retime_src = TX_RETIME_SRC_NA;
23053b26b9bSGiuseppe CAVALLARO dwmac->speed = SPEED_100;
231d15891caSSrinivas Kandagatla
232d15891caSSrinivas Kandagatla if (IS_PHY_IF_MODE_GBIT(dwmac->interface)) {
233d15891caSSrinivas Kandagatla const char *rs;
234d15891caSSrinivas Kandagatla
23522407e13SGiuseppe CAVALLARO dwmac->tx_retime_src = TX_RETIME_SRC_CLKGEN;
23622407e13SGiuseppe CAVALLARO
237d15891caSSrinivas Kandagatla err = of_property_read_string(np, "st,tx-retime-src", &rs);
23850262c85SGeert Uytterhoeven if (err < 0) {
23953b26b9bSGiuseppe CAVALLARO dev_warn(dev, "Use internal clock source\n");
24022407e13SGiuseppe CAVALLARO } else {
24122407e13SGiuseppe CAVALLARO if (!strcasecmp(rs, "clk_125"))
24253b26b9bSGiuseppe CAVALLARO dwmac->tx_retime_src = TX_RETIME_SRC_CLK_125;
24322407e13SGiuseppe CAVALLARO else if (!strcasecmp(rs, "txclk"))
24453b26b9bSGiuseppe CAVALLARO dwmac->tx_retime_src = TX_RETIME_SRC_TXCLK;
24550262c85SGeert Uytterhoeven }
24653b26b9bSGiuseppe CAVALLARO dwmac->speed = SPEED_1000;
247d15891caSSrinivas Kandagatla }
248d15891caSSrinivas Kandagatla
249d15891caSSrinivas Kandagatla dwmac->clk = devm_clk_get(dev, "sti-ethclk");
25053b26b9bSGiuseppe CAVALLARO if (IS_ERR(dwmac->clk)) {
25153b26b9bSGiuseppe CAVALLARO dev_warn(dev, "No phy clock provided...\n");
252d15891caSSrinivas Kandagatla dwmac->clk = NULL;
253d15891caSSrinivas Kandagatla }
254d15891caSSrinivas Kandagatla
255d15891caSSrinivas Kandagatla return 0;
256d15891caSSrinivas Kandagatla }
257d15891caSSrinivas Kandagatla
sti_dwmac_probe(struct platform_device * pdev)2588387ee21SJoachim Eastwood static int sti_dwmac_probe(struct platform_device *pdev)
259d15891caSSrinivas Kandagatla {
2608387ee21SJoachim Eastwood struct plat_stmmacenet_data *plat_dat;
26107ca3749SJoachim Eastwood const struct sti_dwmac_of_data *data;
2628387ee21SJoachim Eastwood struct stmmac_resources stmmac_res;
263d15891caSSrinivas Kandagatla struct sti_dwmac *dwmac;
264d15891caSSrinivas Kandagatla int ret;
265d15891caSSrinivas Kandagatla
266149adeddSJoachim Eastwood data = of_device_get_match_data(&pdev->dev);
267149adeddSJoachim Eastwood if (!data) {
268149adeddSJoachim Eastwood dev_err(&pdev->dev, "No OF match data provided\n");
269149adeddSJoachim Eastwood return -EINVAL;
270149adeddSJoachim Eastwood }
271149adeddSJoachim Eastwood
2728387ee21SJoachim Eastwood ret = stmmac_get_platform_resources(pdev, &stmmac_res);
2738387ee21SJoachim Eastwood if (ret)
2748387ee21SJoachim Eastwood return ret;
2758387ee21SJoachim Eastwood
27683216e39SMichael Walle plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac);
2778387ee21SJoachim Eastwood if (IS_ERR(plat_dat))
2788387ee21SJoachim Eastwood return PTR_ERR(plat_dat);
2798387ee21SJoachim Eastwood
280d15891caSSrinivas Kandagatla dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL);
281d2ed0a77SJohan Hovold if (!dwmac) {
282d2ed0a77SJohan Hovold ret = -ENOMEM;
283d2ed0a77SJohan Hovold goto err_remove_config_dt;
284d2ed0a77SJohan Hovold }
285d15891caSSrinivas Kandagatla
286d15891caSSrinivas Kandagatla ret = sti_dwmac_parse_data(dwmac, pdev);
287d15891caSSrinivas Kandagatla if (ret) {
288d15891caSSrinivas Kandagatla dev_err(&pdev->dev, "Unable to parse OF data\n");
289d2ed0a77SJohan Hovold goto err_remove_config_dt;
290d15891caSSrinivas Kandagatla }
291d15891caSSrinivas Kandagatla
29216b1adbbSJoachim Eastwood dwmac->fix_retime_src = data->fix_retime_src;
2938387ee21SJoachim Eastwood
29416b1adbbSJoachim Eastwood plat_dat->bsp_priv = dwmac;
29516b1adbbSJoachim Eastwood plat_dat->fix_mac_speed = data->fix_retime_src;
29616b1adbbSJoachim Eastwood
297b89cbfb0SJoachim Eastwood ret = clk_prepare_enable(dwmac->clk);
2988387ee21SJoachim Eastwood if (ret)
299d2ed0a77SJohan Hovold goto err_remove_config_dt;
3008387ee21SJoachim Eastwood
3010eebedc2SJoachim Eastwood ret = sti_dwmac_set_mode(dwmac);
302b89cbfb0SJoachim Eastwood if (ret)
303b89cbfb0SJoachim Eastwood goto disable_clk;
304b89cbfb0SJoachim Eastwood
305b89cbfb0SJoachim Eastwood ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
306b89cbfb0SJoachim Eastwood if (ret)
307b89cbfb0SJoachim Eastwood goto disable_clk;
308b89cbfb0SJoachim Eastwood
309b89cbfb0SJoachim Eastwood return 0;
310b89cbfb0SJoachim Eastwood
311b89cbfb0SJoachim Eastwood disable_clk:
312b89cbfb0SJoachim Eastwood clk_disable_unprepare(dwmac->clk);
313d2ed0a77SJohan Hovold err_remove_config_dt:
314d2ed0a77SJohan Hovold stmmac_remove_config_dt(pdev, plat_dat);
3150a9e2271SJohan Hovold
316b89cbfb0SJoachim Eastwood return ret;
317d15891caSSrinivas Kandagatla }
318d15891caSSrinivas Kandagatla
sti_dwmac_remove(struct platform_device * pdev)319b394982aSUwe Kleine-König static void sti_dwmac_remove(struct platform_device *pdev)
3202517cfd4SJoachim Eastwood {
3212517cfd4SJoachim Eastwood struct sti_dwmac *dwmac = get_stmmac_bsp_priv(&pdev->dev);
322ff0011cfSUwe Kleine-König
323ff0011cfSUwe Kleine-König stmmac_dvr_remove(&pdev->dev);
3242517cfd4SJoachim Eastwood
3252517cfd4SJoachim Eastwood clk_disable_unprepare(dwmac->clk);
3262517cfd4SJoachim Eastwood }
3272517cfd4SJoachim Eastwood
3282517cfd4SJoachim Eastwood #ifdef CONFIG_PM_SLEEP
sti_dwmac_suspend(struct device * dev)3292517cfd4SJoachim Eastwood static int sti_dwmac_suspend(struct device *dev)
3302517cfd4SJoachim Eastwood {
3312517cfd4SJoachim Eastwood struct sti_dwmac *dwmac = get_stmmac_bsp_priv(dev);
3322517cfd4SJoachim Eastwood int ret = stmmac_suspend(dev);
3332517cfd4SJoachim Eastwood
3342517cfd4SJoachim Eastwood clk_disable_unprepare(dwmac->clk);
3352517cfd4SJoachim Eastwood
3362517cfd4SJoachim Eastwood return ret;
3372517cfd4SJoachim Eastwood }
3382517cfd4SJoachim Eastwood
sti_dwmac_resume(struct device * dev)3392517cfd4SJoachim Eastwood static int sti_dwmac_resume(struct device *dev)
3402517cfd4SJoachim Eastwood {
3412517cfd4SJoachim Eastwood struct sti_dwmac *dwmac = get_stmmac_bsp_priv(dev);
3422517cfd4SJoachim Eastwood
343b89cbfb0SJoachim Eastwood clk_prepare_enable(dwmac->clk);
3440eebedc2SJoachim Eastwood sti_dwmac_set_mode(dwmac);
3452517cfd4SJoachim Eastwood
3462517cfd4SJoachim Eastwood return stmmac_resume(dev);
3472517cfd4SJoachim Eastwood }
3482517cfd4SJoachim Eastwood #endif /* CONFIG_PM_SLEEP */
3492517cfd4SJoachim Eastwood
3502517cfd4SJoachim Eastwood static SIMPLE_DEV_PM_OPS(sti_dwmac_pm_ops, sti_dwmac_suspend,
3512517cfd4SJoachim Eastwood sti_dwmac_resume);
3522517cfd4SJoachim Eastwood
35307ca3749SJoachim Eastwood static const struct sti_dwmac_of_data stih4xx_dwmac_data = {
35416b1adbbSJoachim Eastwood .fix_retime_src = stih4xx_fix_retime_src,
35553b26b9bSGiuseppe CAVALLARO };
35653b26b9bSGiuseppe CAVALLARO
3572a321798SJoachim Eastwood static const struct of_device_id sti_dwmac_match[] = {
3582a321798SJoachim Eastwood { .compatible = "st,stih407-dwmac", .data = &stih4xx_dwmac_data},
3592a321798SJoachim Eastwood { }
3602a321798SJoachim Eastwood };
3612a321798SJoachim Eastwood MODULE_DEVICE_TABLE(of, sti_dwmac_match);
3622a321798SJoachim Eastwood
3632a321798SJoachim Eastwood static struct platform_driver sti_dwmac_driver = {
3648387ee21SJoachim Eastwood .probe = sti_dwmac_probe,
365b394982aSUwe Kleine-König .remove_new = sti_dwmac_remove,
3662a321798SJoachim Eastwood .driver = {
3672a321798SJoachim Eastwood .name = "sti-dwmac",
3682517cfd4SJoachim Eastwood .pm = &sti_dwmac_pm_ops,
3692a321798SJoachim Eastwood .of_match_table = sti_dwmac_match,
3702a321798SJoachim Eastwood },
3712a321798SJoachim Eastwood };
3722a321798SJoachim Eastwood module_platform_driver(sti_dwmac_driver);
3732a321798SJoachim Eastwood
3742a321798SJoachim Eastwood MODULE_AUTHOR("Srinivas Kandagatla <srinivas.kandagatla@st.com>");
3752a321798SJoachim Eastwood MODULE_DESCRIPTION("STMicroelectronics DWMAC Specific Glue layer");
3762a321798SJoachim Eastwood MODULE_LICENSE("GPL");
377