1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * dwmac-sti.c - STMicroelectronics DWMAC Specific Glue layer
4  *
5  * Copyright (C) 2003-2014 STMicroelectronics (R&D) Limited
6  * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
7  * Contributors: Giuseppe Cavallaro <peppe.cavallaro@st.com>
8  */
9 
10 #include <linux/kernel.h>
11 #include <linux/slab.h>
12 #include <linux/platform_device.h>
13 #include <linux/stmmac.h>
14 #include <linux/phy.h>
15 #include <linux/mfd/syscon.h>
16 #include <linux/module.h>
17 #include <linux/regmap.h>
18 #include <linux/clk.h>
19 #include <linux/of.h>
20 #include <linux/of_net.h>
21 
22 #include "stmmac_platform.h"
23 
24 #define DWMAC_125MHZ	125000000
25 #define DWMAC_50MHZ	50000000
26 #define DWMAC_25MHZ	25000000
27 #define DWMAC_2_5MHZ	2500000
28 
29 #define IS_PHY_IF_MODE_RGMII(iface)	(iface == PHY_INTERFACE_MODE_RGMII || \
30 			iface == PHY_INTERFACE_MODE_RGMII_ID || \
31 			iface == PHY_INTERFACE_MODE_RGMII_RXID || \
32 			iface == PHY_INTERFACE_MODE_RGMII_TXID)
33 
34 #define IS_PHY_IF_MODE_GBIT(iface)	(IS_PHY_IF_MODE_RGMII(iface) || \
35 					 iface == PHY_INTERFACE_MODE_GMII)
36 
37 /* STiH4xx register definitions (STiH407/STiH410 families)
38  *
39  * Below table summarizes the clock requirement and clock sources for
40  * supported phy interface modes with link speeds.
41  * ________________________________________________
42  *|  PHY_MODE	| 1000 Mbit Link | 100 Mbit Link   |
43  * ------------------------------------------------
44  *|	MII	|	n/a	 |	25Mhz	   |
45  *|		|		 |	txclk	   |
46  * ------------------------------------------------
47  *|	GMII	|     125Mhz	 |	25Mhz	   |
48  *|		|  clk-125/txclk |	txclk	   |
49  * ------------------------------------------------
50  *|	RGMII	|     125Mhz	 |	25Mhz	   |
51  *|		|  clk-125/txclk |	clkgen     |
52  *|		|    clkgen	 |		   |
53  * ------------------------------------------------
54  *|	RMII	|	n/a	 |	25Mhz	   |
55  *|		|		 |clkgen/phyclk-in |
56  * ------------------------------------------------
57  *
58  *	  Register Configuration
59  *-------------------------------
60  * src	 |BIT(8)| BIT(7)| BIT(6)|
61  *-------------------------------
62  * txclk |   0	|  n/a	|   1	|
63  *-------------------------------
64  * ck_125|   0	|  n/a	|   0	|
65  *-------------------------------
66  * phyclk|   1	|   0	|  n/a	|
67  *-------------------------------
68  * clkgen|   1	|   1	|  n/a	|
69  *-------------------------------
70  */
71 
72 #define STIH4XX_RETIME_SRC_MASK			GENMASK(8, 6)
73 #define STIH4XX_ETH_SEL_TX_RETIME_CLK		BIT(8)
74 #define STIH4XX_ETH_SEL_INTERNAL_NOTEXT_PHYCLK	BIT(7)
75 #define STIH4XX_ETH_SEL_TXCLK_NOT_CLK125	BIT(6)
76 
77 #define ENMII_MASK	GENMASK(5, 5)
78 #define ENMII		BIT(5)
79 #define EN_MASK		GENMASK(1, 1)
80 #define EN		BIT(1)
81 
82 /*
83  * 3 bits [4:2]
84  *	000-GMII/MII
85  *	001-RGMII
86  *	010-SGMII
87  *	100-RMII
88  */
89 #define MII_PHY_SEL_MASK	GENMASK(4, 2)
90 #define ETH_PHY_SEL_RMII	BIT(4)
91 #define ETH_PHY_SEL_SGMII	BIT(3)
92 #define ETH_PHY_SEL_RGMII	BIT(2)
93 #define ETH_PHY_SEL_GMII	0x0
94 #define ETH_PHY_SEL_MII		0x0
95 
96 struct sti_dwmac {
97 	phy_interface_t interface;	/* MII interface */
98 	bool ext_phyclk;	/* Clock from external PHY */
99 	u32 tx_retime_src;	/* TXCLK Retiming*/
100 	struct clk *clk;	/* PHY clock */
101 	u32 ctrl_reg;		/* GMAC glue-logic control register */
102 	int clk_sel_reg;	/* GMAC ext clk selection register */
103 	struct regmap *regmap;
104 	bool gmac_en;
105 	u32 speed;
106 	void (*fix_retime_src)(void *priv, unsigned int speed, unsigned int mode);
107 };
108 
109 struct sti_dwmac_of_data {
110 	void (*fix_retime_src)(void *priv, unsigned int speed, unsigned int mode);
111 };
112 
113 static u32 phy_intf_sels[] = {
114 	[PHY_INTERFACE_MODE_MII] = ETH_PHY_SEL_MII,
115 	[PHY_INTERFACE_MODE_GMII] = ETH_PHY_SEL_GMII,
116 	[PHY_INTERFACE_MODE_RGMII] = ETH_PHY_SEL_RGMII,
117 	[PHY_INTERFACE_MODE_RGMII_ID] = ETH_PHY_SEL_RGMII,
118 	[PHY_INTERFACE_MODE_SGMII] = ETH_PHY_SEL_SGMII,
119 	[PHY_INTERFACE_MODE_RMII] = ETH_PHY_SEL_RMII,
120 };
121 
122 enum {
123 	TX_RETIME_SRC_NA = 0,
124 	TX_RETIME_SRC_TXCLK = 1,
125 	TX_RETIME_SRC_CLK_125,
126 	TX_RETIME_SRC_PHYCLK,
127 	TX_RETIME_SRC_CLKGEN,
128 };
129 
130 static u32 stih4xx_tx_retime_val[] = {
131 	[TX_RETIME_SRC_TXCLK] = STIH4XX_ETH_SEL_TXCLK_NOT_CLK125,
132 	[TX_RETIME_SRC_CLK_125] = 0x0,
133 	[TX_RETIME_SRC_PHYCLK] = STIH4XX_ETH_SEL_TX_RETIME_CLK,
134 	[TX_RETIME_SRC_CLKGEN] = STIH4XX_ETH_SEL_TX_RETIME_CLK
135 				 | STIH4XX_ETH_SEL_INTERNAL_NOTEXT_PHYCLK,
136 };
137 
stih4xx_fix_retime_src(void * priv,u32 spd,unsigned int mode)138 static void stih4xx_fix_retime_src(void *priv, u32 spd, unsigned int mode)
139 {
140 	struct sti_dwmac *dwmac = priv;
141 	u32 src = dwmac->tx_retime_src;
142 	u32 reg = dwmac->ctrl_reg;
143 	u32 freq = 0;
144 
145 	if (dwmac->interface == PHY_INTERFACE_MODE_MII) {
146 		src = TX_RETIME_SRC_TXCLK;
147 	} else if (dwmac->interface == PHY_INTERFACE_MODE_RMII) {
148 		if (dwmac->ext_phyclk) {
149 			src = TX_RETIME_SRC_PHYCLK;
150 		} else {
151 			src = TX_RETIME_SRC_CLKGEN;
152 			freq = DWMAC_50MHZ;
153 		}
154 	} else if (IS_PHY_IF_MODE_RGMII(dwmac->interface)) {
155 		/* On GiGa clk source can be either ext or from clkgen */
156 		if (spd == SPEED_1000) {
157 			freq = DWMAC_125MHZ;
158 		} else {
159 			/* Switch to clkgen for these speeds */
160 			src = TX_RETIME_SRC_CLKGEN;
161 			if (spd == SPEED_100)
162 				freq = DWMAC_25MHZ;
163 			else if (spd == SPEED_10)
164 				freq = DWMAC_2_5MHZ;
165 		}
166 	}
167 
168 	if (src == TX_RETIME_SRC_CLKGEN && freq)
169 		clk_set_rate(dwmac->clk, freq);
170 
171 	regmap_update_bits(dwmac->regmap, reg, STIH4XX_RETIME_SRC_MASK,
172 			   stih4xx_tx_retime_val[src]);
173 }
174 
sti_dwmac_set_mode(struct sti_dwmac * dwmac)175 static int sti_dwmac_set_mode(struct sti_dwmac *dwmac)
176 {
177 	struct regmap *regmap = dwmac->regmap;
178 	int iface = dwmac->interface;
179 	u32 reg = dwmac->ctrl_reg;
180 	u32 val;
181 
182 	if (dwmac->gmac_en)
183 		regmap_update_bits(regmap, reg, EN_MASK, EN);
184 
185 	regmap_update_bits(regmap, reg, MII_PHY_SEL_MASK, phy_intf_sels[iface]);
186 
187 	val = (iface == PHY_INTERFACE_MODE_REVMII) ? 0 : ENMII;
188 	regmap_update_bits(regmap, reg, ENMII_MASK, val);
189 
190 	dwmac->fix_retime_src(dwmac, dwmac->speed, 0);
191 
192 	return 0;
193 }
194 
sti_dwmac_parse_data(struct sti_dwmac * dwmac,struct platform_device * pdev)195 static int sti_dwmac_parse_data(struct sti_dwmac *dwmac,
196 				struct platform_device *pdev)
197 {
198 	struct resource *res;
199 	struct device *dev = &pdev->dev;
200 	struct device_node *np = dev->of_node;
201 	struct regmap *regmap;
202 	int err;
203 
204 	/* clk selection from extra syscfg register */
205 	dwmac->clk_sel_reg = -ENXIO;
206 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sti-clkconf");
207 	if (res)
208 		dwmac->clk_sel_reg = res->start;
209 
210 	regmap = syscon_regmap_lookup_by_phandle(np, "st,syscon");
211 	if (IS_ERR(regmap))
212 		return PTR_ERR(regmap);
213 
214 	err = of_property_read_u32_index(np, "st,syscon", 1, &dwmac->ctrl_reg);
215 	if (err) {
216 		dev_err(dev, "Can't get sysconfig ctrl offset (%d)\n", err);
217 		return err;
218 	}
219 
220 	err = of_get_phy_mode(np, &dwmac->interface);
221 	if (err && err != -ENODEV) {
222 		dev_err(dev, "Can't get phy-mode\n");
223 		return err;
224 	}
225 
226 	dwmac->regmap = regmap;
227 	dwmac->gmac_en = of_property_read_bool(np, "st,gmac_en");
228 	dwmac->ext_phyclk = of_property_read_bool(np, "st,ext-phyclk");
229 	dwmac->tx_retime_src = TX_RETIME_SRC_NA;
230 	dwmac->speed = SPEED_100;
231 
232 	if (IS_PHY_IF_MODE_GBIT(dwmac->interface)) {
233 		const char *rs;
234 
235 		dwmac->tx_retime_src = TX_RETIME_SRC_CLKGEN;
236 
237 		err = of_property_read_string(np, "st,tx-retime-src", &rs);
238 		if (err < 0) {
239 			dev_warn(dev, "Use internal clock source\n");
240 		} else {
241 			if (!strcasecmp(rs, "clk_125"))
242 				dwmac->tx_retime_src = TX_RETIME_SRC_CLK_125;
243 			else if (!strcasecmp(rs, "txclk"))
244 				dwmac->tx_retime_src = TX_RETIME_SRC_TXCLK;
245 		}
246 		dwmac->speed = SPEED_1000;
247 	}
248 
249 	dwmac->clk = devm_clk_get(dev, "sti-ethclk");
250 	if (IS_ERR(dwmac->clk)) {
251 		dev_warn(dev, "No phy clock provided...\n");
252 		dwmac->clk = NULL;
253 	}
254 
255 	return 0;
256 }
257 
sti_dwmac_probe(struct platform_device * pdev)258 static int sti_dwmac_probe(struct platform_device *pdev)
259 {
260 	struct plat_stmmacenet_data *plat_dat;
261 	const struct sti_dwmac_of_data *data;
262 	struct stmmac_resources stmmac_res;
263 	struct sti_dwmac *dwmac;
264 	int ret;
265 
266 	data = of_device_get_match_data(&pdev->dev);
267 	if (!data) {
268 		dev_err(&pdev->dev, "No OF match data provided\n");
269 		return -EINVAL;
270 	}
271 
272 	ret = stmmac_get_platform_resources(pdev, &stmmac_res);
273 	if (ret)
274 		return ret;
275 
276 	plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac);
277 	if (IS_ERR(plat_dat))
278 		return PTR_ERR(plat_dat);
279 
280 	dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL);
281 	if (!dwmac) {
282 		ret = -ENOMEM;
283 		goto err_remove_config_dt;
284 	}
285 
286 	ret = sti_dwmac_parse_data(dwmac, pdev);
287 	if (ret) {
288 		dev_err(&pdev->dev, "Unable to parse OF data\n");
289 		goto err_remove_config_dt;
290 	}
291 
292 	dwmac->fix_retime_src = data->fix_retime_src;
293 
294 	plat_dat->bsp_priv = dwmac;
295 	plat_dat->fix_mac_speed = data->fix_retime_src;
296 
297 	ret = clk_prepare_enable(dwmac->clk);
298 	if (ret)
299 		goto err_remove_config_dt;
300 
301 	ret = sti_dwmac_set_mode(dwmac);
302 	if (ret)
303 		goto disable_clk;
304 
305 	ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
306 	if (ret)
307 		goto disable_clk;
308 
309 	return 0;
310 
311 disable_clk:
312 	clk_disable_unprepare(dwmac->clk);
313 err_remove_config_dt:
314 	stmmac_remove_config_dt(pdev, plat_dat);
315 
316 	return ret;
317 }
318 
sti_dwmac_remove(struct platform_device * pdev)319 static void sti_dwmac_remove(struct platform_device *pdev)
320 {
321 	struct sti_dwmac *dwmac = get_stmmac_bsp_priv(&pdev->dev);
322 
323 	stmmac_dvr_remove(&pdev->dev);
324 
325 	clk_disable_unprepare(dwmac->clk);
326 }
327 
328 #ifdef CONFIG_PM_SLEEP
sti_dwmac_suspend(struct device * dev)329 static int sti_dwmac_suspend(struct device *dev)
330 {
331 	struct sti_dwmac *dwmac = get_stmmac_bsp_priv(dev);
332 	int ret = stmmac_suspend(dev);
333 
334 	clk_disable_unprepare(dwmac->clk);
335 
336 	return ret;
337 }
338 
sti_dwmac_resume(struct device * dev)339 static int sti_dwmac_resume(struct device *dev)
340 {
341 	struct sti_dwmac *dwmac = get_stmmac_bsp_priv(dev);
342 
343 	clk_prepare_enable(dwmac->clk);
344 	sti_dwmac_set_mode(dwmac);
345 
346 	return stmmac_resume(dev);
347 }
348 #endif /* CONFIG_PM_SLEEP */
349 
350 static SIMPLE_DEV_PM_OPS(sti_dwmac_pm_ops, sti_dwmac_suspend,
351 					   sti_dwmac_resume);
352 
353 static const struct sti_dwmac_of_data stih4xx_dwmac_data = {
354 	.fix_retime_src = stih4xx_fix_retime_src,
355 };
356 
357 static const struct of_device_id sti_dwmac_match[] = {
358 	{ .compatible = "st,stih407-dwmac", .data = &stih4xx_dwmac_data},
359 	{ }
360 };
361 MODULE_DEVICE_TABLE(of, sti_dwmac_match);
362 
363 static struct platform_driver sti_dwmac_driver = {
364 	.probe  = sti_dwmac_probe,
365 	.remove_new = sti_dwmac_remove,
366 	.driver = {
367 		.name           = "sti-dwmac",
368 		.pm		= &sti_dwmac_pm_ops,
369 		.of_match_table = sti_dwmac_match,
370 	},
371 };
372 module_platform_driver(sti_dwmac_driver);
373 
374 MODULE_AUTHOR("Srinivas Kandagatla <srinivas.kandagatla@st.com>");
375 MODULE_DESCRIPTION("STMicroelectronics DWMAC Specific Glue layer");
376 MODULE_LICENSE("GPL");
377