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/openbmc/linux/Documentation/devicetree/bindings/display/rockchip/
H A Drockchip-vop.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip-vop.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip SoC display controller (VOP)
10 VOP (Video Output Processor) is the display controller for the Rockchip
15 - Sandy Huang <hjc@rock-chips.com>
16 - Heiko Stuebner <heiko@sntech.de>
21 - rockchip,px30-vop-big
22 - rockchip,px30-vop-lit
[all …]
H A Drockchip,lvds.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip low-voltage differential signal (LVDS) transmitter
10 - Sandy Huang <hjc@rock-chips.com>
11 - Heiko Stuebner <heiko@sntech.de>
16 - rockchip,px30-lvds
17 - rockchip,rk3288-lvds
25 clock-names:
28 avdd1v0-supply:
[all …]
H A Drockchip,dw-hdmi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Yao <markyao0591@gmail.com>
17 - $ref: ../bridge/synopsys,dw-hdmi.yaml#
22 - rockchip,rk3228-dw-hdmi
23 - rockchip,rk3288-dw-hdmi
24 - rockchip,rk3328-dw-hdmi
25 - rockchip,rk3399-dw-hdmi
[all …]
/openbmc/u-boot/drivers/video/rockchip/
H A Drk3288_vop.c1 // SPDX-License-Identifier: GPL-2.0+
26 struct rk3288_vop *regs = priv->regs; in rk3288_set_pin_polarity()
28 /* The RK3328 VOP (v3.1) has its polarity configuration in ctrl0 */ in rk3288_set_pin_polarity()
29 clrsetbits_le32(&regs->dsp_ctrl0, in rk3288_set_pin_polarity()
39 /* lcdc(vop) iodomain select 1.8V */ in rk3288_set_io_vsel()
40 rk_setreg(&grf->io_vsel, 1 << 0); in rk3288_set_io_vsel()
59 if (!(gd->flags & GD_FLG_RELOC)) in rk3288_vop_probe()
62 /* Set the LCDC(vop) iodomain to 1.8V */ in rk3288_vop_probe()
65 /* Probe regulators required for the RK3288 VOP */ in rk3288_vop_probe()
75 struct rk3288_vop *regs = priv->regs; in rk_vop_remove()
[all …]
H A Drk3288_hdmi.c1 // SPDX-License-Identifier: GPL-2.0+
27 int vop_id = uc_plat->source_id; in rk3288_hdmi_enable()
28 struct rk3288_grf *grf = priv->grf; in rk3288_hdmi_enable()
31 rk_setreg(&grf->soc_con6, 1 << 15); in rk3288_hdmi_enable()
33 /* hdmi data from vop id */ in rk3288_hdmi_enable()
34 rk_clrsetreg(&grf->soc_con6, 1 << 4, (vop_id == 1) ? (1 << 4) : 0); in rk3288_hdmi_enable()
42 struct dw_hdmi *hdmi = &priv->hdmi; in rk3288_hdmi_ofdata_to_platdata()
44 hdmi->i2c_clk_high = 0x7a; in rk3288_hdmi_ofdata_to_platdata()
45 hdmi->i2c_clk_low = 0x8d; in rk3288_hdmi_ofdata_to_platdata()
48 * TODO(sjg@chromium.org): The above values don't work - these in rk3288_hdmi_ofdata_to_platdata()
[all …]
H A DKconfig6 # display by configure the device tree, and the vop driver will do the rest.
8 # Author: Eric Gao <eric.gao@rock-chips.com>
15 Rockchip SoCs provide video output capabilities for High-Definition
16 Multimedia Interface (HDMI), Low-voltage Differential Signalling
19 This driver supports the on-chip video output device, and targets the
20 Rockchip RK3288 and RK3399.
29 framebuffer during device-model binding/probing.
38 framebuffer during device-model binding/probing.
52 This enables Low-voltage Differential Signaling(LVDS) display
60 This enables High-Definition Multimedia Interface display support.
[all …]
/openbmc/linux/drivers/gpu/drm/rockchip/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
25 bool "Rockchip VOP driver"
28 This selects support for the VOP driver. You should enable it
45 on RK3288 or RK3399 based SoC, you should select this option.
63 enable HDMI on RK3288 or RK3399 based SoC, you should select
72 enable MIPI DSI on RK3288 or RK3399 based SoC, you should
88 Rockchip rk3288 SoC has LVDS TX Controller can be used, and it
H A Danalogix_dp-rockchip.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Author: Andy Yan <andy.yan@rock-chips.com>
7 * Yakir Yang <ykk@rock-chips.com>
8 * Jeff Chen <jeff.chen@rock-chips.com>
45 * struct rockchip_dp_chip_data - splite the grf setting of kind of chips
47 * @lcdsel_big: reg value of selecting vop big for eDP
48 * @lcdsel_lit: reg value of selecting vop little for eDP
89 reset_control_assert(dp->rst); in rockchip_dp_pre_init()
91 reset_control_deassert(dp->rst); in rockchip_dp_pre_init()
101 ret = clk_prepare_enable(dp->pclk); in rockchip_dp_poweron_start()
[all …]
H A Drockchip_vop_reg.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author:Mark Yao <mark.yao@rock-chips.com>
461 * hs_start interrupt fires at frame-start, so serves
569 * hs_start interrupt fires at frame-start, so serves
701 * Note: rk3288 has a dedicated 'cursor' window, however, that window requires
965 * rk3399 vop big windows register layout is same as rk3288, but we
1126 { .compatible = "rockchip,rk3036-vop",
1128 { .compatible = "rockchip,rk3126-vop",
1130 { .compatible = "rockchip,px30-vop-big",
1132 { .compatible = "rockchip,px30-vop-lit",
[all …]
H A Drockchip_lvds.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Mark Yao <mark.yao@rock-chips.com>
6 * Sandy Huang <hjc@rock-chips.com>
40 * struct rockchip_lvds_soc_data - rockchip lvds Soc private data
81 writel_relaxed(val, lvds->regs + offset); in rk3288_writel()
82 if (lvds->output == DISPLAY_OUTPUT_LVDS) in rk3288_writel()
84 writel_relaxed(val, lvds->regs + offset + RK3288_LVDS_CH1_OFFSET); in rk3288_writel()
89 if (strncmp(s, "jeida-18", 8) == 0) in rockchip_lvds_name_to_format()
91 else if (strncmp(s, "jeida-24", 8) == 0) in rockchip_lvds_name_to_format()
93 else if (strncmp(s, "vesa-24", 7) == 0) in rockchip_lvds_name_to_format()
[all …]
H A Ddw_hdmi-rockchip.c1 // SPDX-License-Identifier: GPL-2.0-or-later
61 * struct rockchip_hdmi_chip_data - splite the grf setting of kind of chips
63 * @lcdsel_big: reg value of selecting vop big for HDMI
64 * @lcdsel_lit: reg value of selecting vop little for HDMI
212 struct device_node *np = hdmi->dev->of_node; in rockchip_hdmi_parse_dt()
214 hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); in rockchip_hdmi_parse_dt()
215 if (IS_ERR(hdmi->regmap)) { in rockchip_hdmi_parse_dt()
216 DRM_DEV_ERROR(hdmi->dev, "Unable to get rockchip,grf\n"); in rockchip_hdmi_parse_dt()
217 return PTR_ERR(hdmi->regmap); in rockchip_hdmi_parse_dt()
220 hdmi->ref_clk = devm_clk_get_optional(hdmi->dev, "ref"); in rockchip_hdmi_parse_dt()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pwm/
H A Dpwm-rockchip.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pwm/pwm-rockchip.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
15 - const: rockchip,rk2928-pwm
16 - const: rockchip,rk3288-pwm
17 - const: rockchip,rk3328-pwm
18 - const: rockchip,vop-pwm
19 - items:
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Drk3288.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3288-cru.h>
8 #include <dt-bindings/power-domain/rk3288.h>
9 #include <dt-bindings/thermal/thermal.h>
10 #include <dt-bindings/video/rk3288.h>
14 compatible = "rockchip,rk3288";
[all …]
H A Drk3399.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd.
6 #include <dt-bindings/clock/rk3399-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3399-power.h>
12 #include <dt-bindings/thermal/thermal.h>
18 interrupt-parent = <&gic>;
[all …]
/openbmc/linux/arch/arm/boot/dts/rockchip/
H A Drk3288.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3288-cru.h>
8 #include <dt-bindings/power/rk3288-power.h>
9 #include <dt-bindings/thermal/thermal.h>
10 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #address-cells = <2>;
[all …]
H A Drv1126.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rockchip,rv1126-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rockchip,rv1126-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
15 #address-cells = <1>;
16 #size-cells = <1>;
[all …]
H A Drk3036.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3036-cru.h>
8 #include <dt-bindings/soc/rockchip,boot-mode.h>
9 #include <dt-bindings/power/rk3036-power.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
[all …]
H A Drk322x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3228-cru.h>
8 #include <dt-bindings/thermal/thermal.h>
9 #include <dt-bindings/power/rk3228-power.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
[all …]
H A Drk3188.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3188-cru.h>
10 #include <dt-bindings/power/rk3188-power.h>
17 #address-cells = <1>;
18 #size-cells = <0>;
19 enable-method = "rockchip,rk3066-smp";
23 compatible = "arm,cortex-a9";
24 next-level-cache = <&L2>;
[all …]
/openbmc/u-boot/arch/arm/mach-rockchip/
H A Drk3288-board.c1 // SPDX-License-Identifier: GPL-2.0+
20 #include <dt-bindings/clock/rk3288-cru.h>
33 /* set vop qos to higher priority */ in rk3288_qos_init()
37 if (!fdt_node_check_compatible(gd->fdt_blob, 0, in rk3288_qos_init()
38 "rockchip,rk3288-tinker")) in rk3288_qos_init()
56 switch (cru->cru_glb_rst_st) { in rk3288_detect_reset_reason()
82 rk_clrreg(&cru->cru_glb_rst_st, GLB_RST_ST_MASK); in rk3288_detect_reset_reason()
174 return -1; in board_init()
179 if (!fdt_node_check_compatible(gd->fdt_blob, 0, "google,veyron")) { in board_init()
192 /* Enable D-cache. I-cache is already enabled in start.S */ in enable_caches()
[all …]
/openbmc/u-boot/doc/
H A DREADME.rockchip1 # SPDX-License-Identifier: GPL-2.0+
6 U-Boot on Rockchip
9 A wide range of Rockchip SoCs are supported in mainline U-Boot
17 - Firefly RK3288 board or something else with a supported RockChip SoC
18 - Power connection to 5V using the supplied micro-USB power cable
19 - Separate USB serial cable attached to your computer and the Firefly
20 (connect to the micro-USB connector below the logo)
21 - rkflashtool [3]
22 - openssl (sudo apt-get install openssl)
23 - Serial UART connection [4]
[all …]
/openbmc/linux/Documentation/devicetree/bindings/power/
H A Drockchip-io-domain.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/power/rockchip-io-domain.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
17 A specific example using rk3288
42 to report their voltage. The IO Voltage Domain for any non-specified
48 - rockchip,px30-io-voltage-domain
49 - rockchip,px30-pmu-io-voltage-domain
50 - rockchip,rk3188-io-voltage-domain
[all …]
/openbmc/linux/arch/arm64/boot/dts/rockchip/
H A Drk3368.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3368-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3368-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
[all …]
/openbmc/linux/drivers/pwm/
H A Dpwm-rockchip.c1 // SPDX-License-Identifier: GPL-2.0-only
65 u32 enable_conf = pc->data->enable_conf; in rockchip_pwm_get_state()
71 ret = clk_enable(pc->pclk); in rockchip_pwm_get_state()
75 ret = clk_enable(pc->clk); in rockchip_pwm_get_state()
79 clk_rate = clk_get_rate(pc->clk); in rockchip_pwm_get_state()
81 tmp = readl_relaxed(pc->base + pc->data->regs.period); in rockchip_pwm_get_state()
82 tmp *= pc->data->prescaler * NSEC_PER_SEC; in rockchip_pwm_get_state()
83 state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate); in rockchip_pwm_get_state()
85 tmp = readl_relaxed(pc->base + pc->data->regs.duty); in rockchip_pwm_get_state()
86 tmp *= pc->data->prescaler * NSEC_PER_SEC; in rockchip_pwm_get_state()
[all …]
/openbmc/u-boot/drivers/clk/rockchip/
H A Dclk_rk3288.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <clk-uclass.h>
11 #include <dt-structs.h>
20 #include <dt-bindings/clock/rk3288-cru.h>
21 #include <dm/device-internal.h>
23 #include <dm/uclass-internal.h>
148 struct rk3288_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll()
150 uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000; in rkclk_set_pll()
151 uint output_hz = vco_hz / div->no; in rkclk_set_pll()
154 (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz); in rkclk_set_pll()
[all …]

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