Lines Matching +full:rk3288 +full:- +full:vop
1 // SPDX-License-Identifier: GPL-2.0+
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3288-cru.h>
8 #include <dt-bindings/power-domain/rk3288.h>
9 #include <dt-bindings/thermal/thermal.h>
10 #include <dt-bindings/video/rk3288.h>
14 compatible = "rockchip,rk3288";
16 interrupt-parent = <&gic>;
52 #address-cells = <1>;
53 #size-cells = <0>;
54 enable-method = "rockchip,rk3066-smp";
59 compatible = "arm,cortex-a12";
61 operating-points = <
77 #cooling-cells = <2>; /* min followed by max */
78 clock-latency = <40000>;
84 compatible = "arm,cortex-a12";
90 compatible = "arm,cortex-a12";
96 compatible = "arm,cortex-a12";
103 compatible = "arm,amba-bus";
104 #address-cells = <1>;
105 #size-cells = <1>;
108 dmac_peri: dma-controller@ff250000 {
110 broken-no-flushp;
114 #dma-cells = <1>;
116 clock-names = "apb_pclk";
119 dmac_bus_ns: dma-controller@ff600000 {
121 broken-no-flushp;
125 #dma-cells = <1>;
127 clock-names = "apb_pclk";
131 dmac_bus_s: dma-controller@ffb20000 {
133 broken-no-flushp;
137 #dma-cells = <1>;
139 clock-names = "apb_pclk";
144 compatible = "fixed-clock";
145 clock-frequency = <24000000>;
146 clock-output-names = "xin24m";
147 #clock-cells = <0>;
151 arm,use-physical-timer;
152 compatible = "arm,armv7-timer";
157 clock-frequency = <24000000>;
158 always-on;
161 display-subsystem {
162 compatible = "rockchip,display-subsystem";
167 compatible = "rockchip,rk3288-dw-mshc";
168 max-frequency = <150000000>;
171 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
172 fifo-depth = <0x100>;
179 compatible = "rockchip,rk3288-dw-mshc";
180 max-frequency = <150000000>;
183 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
184 fifo-depth = <0x100>;
191 compatible = "rockchip,rk3288-dw-mshc";
192 max-frequency = <150000000>;
195 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
196 fifo-depth = <0x100>;
203 compatible = "rockchip,rk3288-dw-mshc";
204 max-frequency = <150000000>;
207 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
208 fifo-depth = <0x100>;
218 #io-channel-cells = <1>;
220 clock-names = "saradc", "apb_pclk";
225 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
227 clock-names = "spiclk", "apb_pclk";
229 dma-names = "tx", "rx";
231 pinctrl-names = "default";
232 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
234 #address-cells = <1>;
235 #size-cells = <0>;
240 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
242 clock-names = "spiclk", "apb_pclk";
244 dma-names = "tx", "rx";
246 pinctrl-names = "default";
247 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
249 #address-cells = <1>;
250 #size-cells = <0>;
255 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
257 clock-names = "spiclk", "apb_pclk";
259 dma-names = "tx", "rx";
261 pinctrl-names = "default";
262 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
264 #address-cells = <1>;
265 #size-cells = <0>;
270 compatible = "rockchip,rk3288-i2c";
273 #address-cells = <1>;
274 #size-cells = <0>;
275 clock-names = "i2c";
277 pinctrl-names = "default";
278 pinctrl-0 = <&i2c1_xfer>;
283 compatible = "rockchip,rk3288-i2c";
286 #address-cells = <1>;
287 #size-cells = <0>;
288 clock-names = "i2c";
290 pinctrl-names = "default";
291 pinctrl-0 = <&i2c3_xfer>;
296 compatible = "rockchip,rk3288-i2c";
299 #address-cells = <1>;
300 #size-cells = <0>;
301 clock-names = "i2c";
303 pinctrl-names = "default";
304 pinctrl-0 = <&i2c4_xfer>;
309 compatible = "rockchip,rk3288-i2c";
312 #address-cells = <1>;
313 #size-cells = <0>;
314 clock-names = "i2c";
316 pinctrl-names = "default";
317 pinctrl-0 = <&i2c5_xfer>;
321 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
324 reg-shift = <2>;
325 reg-io-width = <4>;
326 clock-frequency = <24000000>;
328 clock-names = "baudclk", "apb_pclk";
329 pinctrl-names = "default";
330 pinctrl-0 = <&uart0_xfer>;
335 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
338 reg-shift = <2>;
339 reg-io-width = <4>;
340 clock-frequency = <24000000>;
342 clock-names = "baudclk", "apb_pclk";
343 pinctrl-names = "default";
344 pinctrl-0 = <&uart1_xfer>;
349 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
352 reg-shift = <2>;
353 reg-io-width = <4>;
354 clock-frequency = <24000000>;
356 clock-names = "baudclk", "apb_pclk";
357 pinctrl-names = "default";
358 pinctrl-0 = <&uart2_xfer>;
362 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
365 reg-shift = <2>;
366 reg-io-width = <4>;
367 clock-frequency = <24000000>;
369 clock-names = "baudclk", "apb_pclk";
370 pinctrl-names = "default";
371 pinctrl-0 = <&uart3_xfer>;
376 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
379 reg-shift = <2>;
380 reg-io-width = <4>;
381 clock-frequency = <24000000>;
383 clock-names = "baudclk", "apb_pclk";
384 pinctrl-names = "default";
385 pinctrl-0 = <&uart4_xfer>;
388 thermal: thermal-zones {
389 #include "rk3288-thermal.dtsi"
393 compatible = "rockchip,rk3288-tsadc";
397 clock-names = "tsadc", "apb_pclk";
399 reset-names = "tsadc-apb";
400 pinctrl-names = "otp_out";
401 pinctrl-0 = <&otp_out>;
402 #thermal-sensor-cells = <1>;
403 hw-shut-temp = <125000>;
408 compatible = "rockchip,rk3288-gmac";
411 interrupt-names = "macirq";
417 clock-names = "stmmaceth",
424 compatible = "generic-ehci";
428 clock-names = "usbhost";
430 phy-names = "usb";
437 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
442 clock-names = "otg";
444 phy-names = "usb2-phy";
449 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
454 clock-names = "otg";
457 phy-names = "usb2-phy";
462 compatible = "generic-ehci";
466 clock-names = "usbhost";
471 u-boot,dm-pre-reloc;
472 compatible = "rockchip,rk3288-dmc", "syscon";
486 clock-names = "pclk_ddrupctl0", "pclk_publ0",
492 compatible = "rockchip,rk3288-i2c";
495 #address-cells = <1>;
496 #size-cells = <0>;
497 clock-names = "i2c";
499 pinctrl-names = "default";
500 pinctrl-0 = <&i2c0_xfer>;
505 compatible = "rockchip,rk3288-i2c";
508 #address-cells = <1>;
509 #size-cells = <0>;
510 clock-names = "i2c";
512 pinctrl-names = "default";
513 pinctrl-0 = <&i2c2_xfer>;
518 compatible = "rockchip,rk3288-pwm";
520 #pwm-cells = <3>;
521 pinctrl-names = "default";
522 pinctrl-0 = <&pwm0_pin>;
524 clock-names = "pwm";
530 compatible = "rockchip,rk3288-pwm";
532 #pwm-cells = <3>;
533 pinctrl-names = "default";
534 pinctrl-0 = <&pwm1_pin>;
536 clock-names = "pwm";
542 compatible = "rockchip,rk3288-pwm";
544 #pwm-cells = <3>;
545 pinctrl-names = "default";
546 pinctrl-0 = <&pwm2_pin>;
548 clock-names = "pwm";
554 compatible = "rockchip,rk3288-pwm";
556 #pwm-cells = <2>;
557 pinctrl-names = "default";
558 pinctrl-0 = <&pwm3_pin>;
560 clock-names = "pwm";
566 compatible = "mmio-sram";
568 #address-cells = <1>;
569 #size-cells = <1>;
571 smp-sram@0 {
572 compatible = "rockchip,rk3066-smp-sram";
575 ddr_sram: ddr-sram@1000 {
576 compatible = "rockchip,rk3288-ddr-sram";
582 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
586 pmu: power-management@ff730000 {
587 u-boot,dm-pre-reloc;
588 compatible = "rockchip,rk3288-pmu", "syscon";
593 u-boot,dm-pre-reloc;
594 compatible = "rockchip,rk3288-sgrf", "syscon";
598 cru: clock-controller@ff760000 {
599 compatible = "rockchip,rk3288-cru";
602 u-boot,dm-pre-reloc;
603 #clock-cells = <1>;
604 #reset-cells = <1>;
605 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
610 assigned-clock-rates = <594000000>, <400000000>,
618 u-boot,dm-pre-reloc;
619 compatible = "rockchip,rk3288-grf", "syscon";
624 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
632 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
634 #sound-dai-cells = <0>;
635 clock-names = "hclk", "mclk";
638 dma-names = "tx";
640 pinctrl-names = "default";
641 pinctrl-0 = <&spdif_tx>;
647 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
650 #address-cells = <1>;
651 #size-cells = <0>;
652 #sound-dai-cells = <1>;
654 dma-names = "tx", "rx";
655 clock-names = "i2s_hclk", "i2s_clk";
657 pinctrl-names = "default";
658 pinctrl-0 = <&i2s0_bus>;
662 vopb: vop@ff930000 {
663 u-boot,dm-pre-reloc;
664 compatible = "rockchip,rk3288-vop";
668 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
670 reset-names = "axi", "ahb", "dclk";
672 power-domains = <&power RK3288_PD_VIO>;
675 #address-cells = <1>;
676 #size-cells = <0>;
679 remote-endpoint = <&edp_in_vopb>;
683 remote-endpoint = <&hdmi_in_vopb>;
687 remote-endpoint = <&lvds_in_vopb>;
691 remote-endpoint = <&mipi_in_vopb>;
701 interrupt-names = "vopb_mmu";
702 power-domains = <&power RK3288_PD_VIO>;
703 #iommu-cells = <0>;
707 vopl: vop@ff940000 {
708 compatible = "rockchip,rk3288-vop";
712 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
714 reset-names = "axi", "ahb", "dclk";
716 power-domains = <&power RK3288_PD_VIO>;
718 u-boot,dm-pre-reloc;
720 #address-cells = <1>;
721 #size-cells = <0>;
724 remote-endpoint = <&edp_in_vopl>;
728 remote-endpoint = <&hdmi_in_vopl>;
732 remote-endpoint = <&lvds_in_vopl>;
736 remote-endpoint = <&mipi_in_vopl>;
746 interrupt-names = "vopl_mmu";
747 power-domains = <&power RK3288_PD_VIO>;
748 #iommu-cells = <0>;
753 compatible = "rockchip,rk3288-edp";
758 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
760 reset-names = "edp";
761 power-domains = <&power RK3288_PD_VIO>;
765 #address-cells = <1>;
766 #size-cells = <0>;
769 remote-endpoint = <&vopb_out_edp>;
773 remote-endpoint = <&vopl_out_edp>;
780 compatible = "rockchip,rk3288-dw-hdmi";
782 reg-io-width = <4>;
783 ddc-i2c-bus = <&i2c5>;
787 clock-names = "iahb", "isfr";
791 #address-cells = <1>;
792 #size-cells = <0>;
795 remote-endpoint = <&vopb_out_hdmi>;
799 remote-endpoint = <&vopl_out_hdmi>;
806 compatible = "rockchip,rk3288-lvds";
809 clock-names = "pclk_lvds";
810 pinctrl-names = "default";
811 pinctrl-0 = <&lcdc0_ctl>;
815 #address-cells = <1>;
816 #size-cells = <0>;
819 #address-cells = <1>;
820 #size-cells = <0>;
823 remote-endpoint = <&vopb_out_lvds>;
827 remote-endpoint = <&vopl_out_lvds>;
837 clock-names = "pclk_mipi";
838 /*pinctrl-names = "default";
839 pinctrl-0 = <&lcdc0_ctl>;*/
841 #address-cells = <1>;
842 #size-cells = <0>;
847 #address-cells = <1>;
848 #size-cells = <0>;
851 remote-endpoint = <&vopb_out_mipi>;
855 remote-endpoint = <&vopl_out_mipi>;
862 compatible = "rockchip,rk3288-hdmi-audio";
863 i2s-controller = <&i2s>;
867 vpu: video-codec@ff9a0000 {
868 compatible = "rockchip,rk3288-vpu";
872 interrupt-names = "vepu", "vdpu";
874 clock-names = "aclk_vcodec", "hclk_vcodec";
875 power-domains = <&power RK3288_PD_VIDEO>;
883 interrupt-names = "vpu_mmu";
884 power-domains = <&power RK3288_PD_VIDEO>;
885 #iommu-cells = <0>;
892 "arm,mali-midgard";
897 interrupt-names = "JOB", "MMU", "GPU";
899 clock-names = "aclk_gpu";
900 operating-points = <
906 /* 500000 1200000 - See crosbug.com/p/33857 */
909 power-domains = <&power RK3288_PD_GPU>;
914 u-boot,dm-pre-reloc;
915 compatible = "rockchip,rk3288-noc", "syscon";
920 compatible = "rockchip,rk3288-efuse";
925 gic: interrupt-controller@ffc01000 {
926 compatible = "arm,gic-400";
927 interrupt-controller;
928 #interrupt-cells = <3>;
929 #address-cells = <0>;
939 compatible = "rockchip,rk3288-cpuidle";
943 compatible = "rockchip,rk3288-usb-phy";
945 #address-cells = <1>;
946 #size-cells = <0>;
949 usbphy0: usb-phy0 {
950 #phy-cells = <0>;
953 clock-names = "phyclk";
956 usbphy1: usb-phy1 {
957 #phy-cells = <0>;
960 clock-names = "phyclk";
963 usbphy2: usb-phy2 {
964 #phy-cells = <0>;
967 clock-names = "phyclk";
972 compatible = "rockchip,rk3288-pinctrl";
975 #address-cells = <1>;
976 #size-cells = <1>;
980 compatible = "rockchip,gpio-bank";
985 gpio-controller;
986 #gpio-cells = <2>;
988 interrupt-controller;
989 #interrupt-cells = <2>;
993 compatible = "rockchip,gpio-bank";
998 gpio-controller;
999 #gpio-cells = <2>;
1001 interrupt-controller;
1002 #interrupt-cells = <2>;
1006 compatible = "rockchip,gpio-bank";
1011 gpio-controller;
1012 #gpio-cells = <2>;
1014 interrupt-controller;
1015 #interrupt-cells = <2>;
1019 compatible = "rockchip,gpio-bank";
1024 gpio-controller;
1025 #gpio-cells = <2>;
1027 interrupt-controller;
1028 #interrupt-cells = <2>;
1032 compatible = "rockchip,gpio-bank";
1037 gpio-controller;
1038 #gpio-cells = <2>;
1040 interrupt-controller;
1041 #interrupt-cells = <2>;
1045 compatible = "rockchip,gpio-bank";
1050 gpio-controller;
1051 #gpio-cells = <2>;
1053 interrupt-controller;
1054 #interrupt-cells = <2>;
1058 compatible = "rockchip,gpio-bank";
1063 gpio-controller;
1064 #gpio-cells = <2>;
1066 interrupt-controller;
1067 #interrupt-cells = <2>;
1071 compatible = "rockchip,gpio-bank";
1076 gpio-controller;
1077 #gpio-cells = <2>;
1079 interrupt-controller;
1080 #interrupt-cells = <2>;
1084 compatible = "rockchip,gpio-bank";
1089 gpio-controller;
1090 #gpio-cells = <2>;
1092 interrupt-controller;
1093 #interrupt-cells = <2>;
1096 pcfg_pull_up: pcfg-pull-up {
1097 bias-pull-up;
1100 pcfg_pull_down: pcfg-pull-down {
1101 bias-pull-down;
1104 pcfg_pull_none: pcfg-pull-none {
1105 bias-disable;
1108 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1109 bias-disable;
1110 drive-strength = <12>;
1114 global_pwroff: global-pwroff {
1118 ddrio_pwroff: ddrio-pwroff {
1122 ddr0_retention: ddr0-retention {
1126 ddr1_retention: ddr1-retention {
1132 i2c0_xfer: i2c0-xfer {
1139 i2c1_xfer: i2c1-xfer {
1146 i2c2_xfer: i2c2-xfer {
1153 i2c3_xfer: i2c3-xfer {
1160 i2c4_xfer: i2c4-xfer {
1167 i2c5_xfer: i2c5-xfer {
1174 i2s0_bus: i2s0-bus {
1185 lcdc0_ctl: lcdc0-ctl {
1194 sdmmc_clk: sdmmc-clk {
1198 sdmmc_cmd: sdmmc-cmd {
1202 sdmmc_cd: sdmcc-cd {
1206 sdmmc_bus1: sdmmc-bus1 {
1210 sdmmc_bus4: sdmmc-bus4 {
1219 sdio0_bus1: sdio0-bus1 {
1223 sdio0_bus4: sdio0-bus4 {
1230 sdio0_cmd: sdio0-cmd {
1234 sdio0_clk: sdio0-clk {
1238 sdio0_cd: sdio0-cd {
1242 sdio0_wp: sdio0-wp {
1246 sdio0_pwr: sdio0-pwr {
1250 sdio0_bkpwr: sdio0-bkpwr {
1254 sdio0_int: sdio0-int {
1260 sdio1_bus1: sdio1-bus1 {
1264 sdio1_bus4: sdio1-bus4 {
1271 sdio1_cd: sdio1-cd {
1275 sdio1_wp: sdio1-wp {
1279 sdio1_bkpwr: sdio1-bkpwr {
1283 sdio1_int: sdio1-int {
1287 sdio1_cmd: sdio1-cmd {
1291 sdio1_clk: sdio1-clk {
1295 sdio1_pwr: sdio1-pwr {
1301 emmc_clk: emmc-clk {
1305 emmc_cmd: emmc-cmd {
1309 emmc_pwr: emmc-pwr {
1313 emmc_bus1: emmc-bus1 {
1317 emmc_bus4: emmc-bus4 {
1324 emmc_bus8: emmc-bus8 {
1337 spi0_clk: spi0-clk {
1340 spi0_cs0: spi0-cs0 {
1343 spi0_tx: spi0-tx {
1346 spi0_rx: spi0-rx {
1349 spi0_cs1: spi0-cs1 {
1354 spi1_clk: spi1-clk {
1357 spi1_cs0: spi1-cs0 {
1360 spi1_rx: spi1-rx {
1363 spi1_tx: spi1-tx {
1369 spi2_cs1: spi2-cs1 {
1372 spi2_clk: spi2-clk {
1375 spi2_cs0: spi2-cs0 {
1378 spi2_rx: spi2-rx {
1381 spi2_tx: spi2-tx {
1387 uart0_xfer: uart0-xfer {
1392 uart0_cts: uart0-cts {
1396 uart0_rts: uart0-rts {
1402 uart1_xfer: uart1-xfer {
1407 uart1_cts: uart1-cts {
1411 uart1_rts: uart1-rts {
1417 uart2_xfer: uart2-xfer {
1425 uart3_xfer: uart3-xfer {
1430 uart3_cts: uart3-cts {
1434 uart3_rts: uart3-rts {
1440 uart4_xfer: uart4-xfer {
1445 uart4_cts: uart4-cts {
1449 uart4_rts: uart4-rts {
1455 otp_out: otp-out {
1461 pwm0_pin: pwm0-pin {
1467 pwm1_pin: pwm1-pin {
1473 pwm2_pin: pwm2-pin {
1479 pwm3_pin: pwm3-pin {
1485 rgmii_pins: rgmii-pins {
1503 rmii_pins: rmii-pins {
1518 spdif_tx: spdif-tx {
1524 power: power-controller {
1525 compatible = "rockchip,rk3288-power-controller";
1526 #power-domain-cells = <1>;
1528 #address-cells = <1>;
1529 #size-cells = <0>;