Lines Matching +full:rk3288 +full:- +full:vop
1 // SPDX-License-Identifier: GPL-2.0-or-later
61 * struct rockchip_hdmi_chip_data - splite the grf setting of kind of chips
63 * @lcdsel_big: reg value of selecting vop big for HDMI
64 * @lcdsel_lit: reg value of selecting vop little for HDMI
212 struct device_node *np = hdmi->dev->of_node; in rockchip_hdmi_parse_dt()
214 hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); in rockchip_hdmi_parse_dt()
215 if (IS_ERR(hdmi->regmap)) { in rockchip_hdmi_parse_dt()
216 DRM_DEV_ERROR(hdmi->dev, "Unable to get rockchip,grf\n"); in rockchip_hdmi_parse_dt()
217 return PTR_ERR(hdmi->regmap); in rockchip_hdmi_parse_dt()
220 hdmi->ref_clk = devm_clk_get_optional(hdmi->dev, "ref"); in rockchip_hdmi_parse_dt()
221 if (!hdmi->ref_clk) in rockchip_hdmi_parse_dt()
222 hdmi->ref_clk = devm_clk_get_optional(hdmi->dev, "vpll"); in rockchip_hdmi_parse_dt()
224 if (PTR_ERR(hdmi->ref_clk) == -EPROBE_DEFER) { in rockchip_hdmi_parse_dt()
225 return -EPROBE_DEFER; in rockchip_hdmi_parse_dt()
226 } else if (IS_ERR(hdmi->ref_clk)) { in rockchip_hdmi_parse_dt()
227 DRM_DEV_ERROR(hdmi->dev, "failed to get reference clock\n"); in rockchip_hdmi_parse_dt()
228 return PTR_ERR(hdmi->ref_clk); in rockchip_hdmi_parse_dt()
231 hdmi->grf_clk = devm_clk_get(hdmi->dev, "grf"); in rockchip_hdmi_parse_dt()
232 if (PTR_ERR(hdmi->grf_clk) == -ENOENT) { in rockchip_hdmi_parse_dt()
233 hdmi->grf_clk = NULL; in rockchip_hdmi_parse_dt()
234 } else if (PTR_ERR(hdmi->grf_clk) == -EPROBE_DEFER) { in rockchip_hdmi_parse_dt()
235 return -EPROBE_DEFER; in rockchip_hdmi_parse_dt()
236 } else if (IS_ERR(hdmi->grf_clk)) { in rockchip_hdmi_parse_dt()
237 DRM_DEV_ERROR(hdmi->dev, "failed to get grf clock\n"); in rockchip_hdmi_parse_dt()
238 return PTR_ERR(hdmi->grf_clk); in rockchip_hdmi_parse_dt()
241 hdmi->avdd_0v9 = devm_regulator_get(hdmi->dev, "avdd-0v9"); in rockchip_hdmi_parse_dt()
242 if (IS_ERR(hdmi->avdd_0v9)) in rockchip_hdmi_parse_dt()
243 return PTR_ERR(hdmi->avdd_0v9); in rockchip_hdmi_parse_dt()
245 hdmi->avdd_1v8 = devm_regulator_get(hdmi->dev, "avdd-1v8"); in rockchip_hdmi_parse_dt()
246 if (IS_ERR(hdmi->avdd_1v8)) in rockchip_hdmi_parse_dt()
247 return PTR_ERR(hdmi->avdd_1v8); in rockchip_hdmi_parse_dt()
259 int pclk = mode->clock * 1000; in dw_hdmi_rockchip_mode_valid()
260 bool exact_match = hdmi->plat_data->phy_force_vendor; in dw_hdmi_rockchip_mode_valid()
263 if (hdmi->ref_clk) { in dw_hdmi_rockchip_mode_valid()
264 int rpclk = clk_round_rate(hdmi->ref_clk, pclk); in dw_hdmi_rockchip_mode_valid()
266 if (abs(rpclk - pclk) > pclk / 1000) in dw_hdmi_rockchip_mode_valid()
306 clk_set_rate(hdmi->ref_clk, adj_mode->clock * 1000); in dw_hdmi_rockchip_encoder_mode_set()
315 if (hdmi->chip_data->lcdsel_grf_reg < 0) in dw_hdmi_rockchip_encoder_enable()
318 ret = drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, encoder); in dw_hdmi_rockchip_encoder_enable()
320 val = hdmi->chip_data->lcdsel_lit; in dw_hdmi_rockchip_encoder_enable()
322 val = hdmi->chip_data->lcdsel_big; in dw_hdmi_rockchip_encoder_enable()
324 ret = clk_prepare_enable(hdmi->grf_clk); in dw_hdmi_rockchip_encoder_enable()
326 DRM_DEV_ERROR(hdmi->dev, "failed to enable grfclk %d\n", ret); in dw_hdmi_rockchip_encoder_enable()
330 ret = regmap_write(hdmi->regmap, hdmi->chip_data->lcdsel_grf_reg, val); in dw_hdmi_rockchip_encoder_enable()
332 DRM_DEV_ERROR(hdmi->dev, "Could not write to GRF: %d\n", ret); in dw_hdmi_rockchip_encoder_enable()
334 clk_disable_unprepare(hdmi->grf_clk); in dw_hdmi_rockchip_encoder_enable()
335 DRM_DEV_DEBUG(hdmi->dev, "vop %s output to hdmi\n", in dw_hdmi_rockchip_encoder_enable()
346 s->output_mode = ROCKCHIP_OUT_MODE_AAAA; in dw_hdmi_rockchip_encoder_atomic_check()
347 s->output_type = DRM_MODE_CONNECTOR_HDMIA; in dw_hdmi_rockchip_encoder_atomic_check()
366 return phy_power_on(hdmi->phy); in dw_hdmi_rockchip_genphy_init()
373 phy_power_off(hdmi->phy); in dw_hdmi_rockchip_genphy_disable()
382 regmap_write(hdmi->regmap, in dw_hdmi_rk3228_setup_hpd()
389 regmap_write(hdmi->regmap, in dw_hdmi_rk3228_setup_hpd()
404 regmap_write(hdmi->regmap, in dw_hdmi_rk3328_read_hpd()
409 regmap_write(hdmi->regmap, in dw_hdmi_rk3328_read_hpd()
422 /* Enable and map pins to 3V grf-controlled io-voltage */ in dw_hdmi_rk3328_setup_hpd()
423 regmap_write(hdmi->regmap, in dw_hdmi_rk3328_setup_hpd()
428 regmap_write(hdmi->regmap, in dw_hdmi_rk3328_setup_hpd()
433 regmap_write(hdmi->regmap, in dw_hdmi_rk3328_setup_hpd()
451 .lcdsel_grf_reg = -1,
488 .lcdsel_grf_reg = -1,
519 .lcdsel_grf_reg = -1,
532 { .compatible = "rockchip,rk3228-dw-hdmi",
535 { .compatible = "rockchip,rk3288-dw-hdmi",
538 { .compatible = "rockchip,rk3328-dw-hdmi",
541 { .compatible = "rockchip,rk3399-dw-hdmi",
544 { .compatible = "rockchip,rk3568-dw-hdmi",
562 if (!pdev->dev.of_node) in dw_hdmi_rockchip_bind()
563 return -ENODEV; in dw_hdmi_rockchip_bind()
565 hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL); in dw_hdmi_rockchip_bind()
567 return -ENOMEM; in dw_hdmi_rockchip_bind()
569 match = of_match_node(dw_hdmi_rockchip_dt_ids, pdev->dev.of_node); in dw_hdmi_rockchip_bind()
570 plat_data = devm_kmemdup(&pdev->dev, match->data, in dw_hdmi_rockchip_bind()
573 return -ENOMEM; in dw_hdmi_rockchip_bind()
575 hdmi->dev = &pdev->dev; in dw_hdmi_rockchip_bind()
576 hdmi->plat_data = plat_data; in dw_hdmi_rockchip_bind()
577 hdmi->chip_data = plat_data->phy_data; in dw_hdmi_rockchip_bind()
578 plat_data->phy_data = hdmi; in dw_hdmi_rockchip_bind()
579 plat_data->priv_data = hdmi; in dw_hdmi_rockchip_bind()
580 encoder = &hdmi->encoder.encoder; in dw_hdmi_rockchip_bind()
582 encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node); in dw_hdmi_rockchip_bind()
583 rockchip_drm_encoder_set_crtc_endpoint_id(&hdmi->encoder, in dw_hdmi_rockchip_bind()
584 dev->of_node, 0, 0); in dw_hdmi_rockchip_bind()
592 if (encoder->possible_crtcs == 0) in dw_hdmi_rockchip_bind()
593 return -EPROBE_DEFER; in dw_hdmi_rockchip_bind()
597 if (ret != -EPROBE_DEFER) in dw_hdmi_rockchip_bind()
598 DRM_DEV_ERROR(hdmi->dev, "Unable to parse OF data\n"); in dw_hdmi_rockchip_bind()
602 hdmi->phy = devm_phy_optional_get(dev, "hdmi"); in dw_hdmi_rockchip_bind()
603 if (IS_ERR(hdmi->phy)) { in dw_hdmi_rockchip_bind()
604 ret = PTR_ERR(hdmi->phy); in dw_hdmi_rockchip_bind()
605 if (ret != -EPROBE_DEFER) in dw_hdmi_rockchip_bind()
606 DRM_DEV_ERROR(hdmi->dev, "failed to get phy\n"); in dw_hdmi_rockchip_bind()
610 ret = regulator_enable(hdmi->avdd_0v9); in dw_hdmi_rockchip_bind()
612 DRM_DEV_ERROR(hdmi->dev, "failed to enable avdd0v9: %d\n", ret); in dw_hdmi_rockchip_bind()
616 ret = regulator_enable(hdmi->avdd_1v8); in dw_hdmi_rockchip_bind()
618 DRM_DEV_ERROR(hdmi->dev, "failed to enable avdd1v8: %d\n", ret); in dw_hdmi_rockchip_bind()
622 ret = clk_prepare_enable(hdmi->ref_clk); in dw_hdmi_rockchip_bind()
624 DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI reference clock: %d\n", in dw_hdmi_rockchip_bind()
629 if (hdmi->chip_data == &rk3568_chip_data) { in dw_hdmi_rockchip_bind()
630 regmap_write(hdmi->regmap, RK3568_GRF_VO_CON1, in dw_hdmi_rockchip_bind()
642 hdmi->hdmi = dw_hdmi_bind(pdev, encoder, plat_data); in dw_hdmi_rockchip_bind()
648 if (IS_ERR(hdmi->hdmi)) { in dw_hdmi_rockchip_bind()
649 ret = PTR_ERR(hdmi->hdmi); in dw_hdmi_rockchip_bind()
657 clk_disable_unprepare(hdmi->ref_clk); in dw_hdmi_rockchip_bind()
659 regulator_disable(hdmi->avdd_1v8); in dw_hdmi_rockchip_bind()
661 regulator_disable(hdmi->avdd_0v9); in dw_hdmi_rockchip_bind()
671 dw_hdmi_unbind(hdmi->hdmi); in dw_hdmi_rockchip_unbind()
672 drm_encoder_cleanup(&hdmi->encoder.encoder); in dw_hdmi_rockchip_unbind()
673 clk_disable_unprepare(hdmi->ref_clk); in dw_hdmi_rockchip_unbind()
675 regulator_disable(hdmi->avdd_1v8); in dw_hdmi_rockchip_unbind()
676 regulator_disable(hdmi->avdd_0v9); in dw_hdmi_rockchip_unbind()
686 return component_add(&pdev->dev, &dw_hdmi_rockchip_ops); in dw_hdmi_rockchip_probe()
691 component_del(&pdev->dev, &dw_hdmi_rockchip_ops); in dw_hdmi_rockchip_remove()
698 dw_hdmi_resume(hdmi->hdmi); in dw_hdmi_rockchip_resume()
711 .name = "dwhdmi-rockchip",