1d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
2101353c8SBeniamino Galvani /*
3101353c8SBeniamino Galvani * PWM driver for Rockchip SoCs
4101353c8SBeniamino Galvani *
5101353c8SBeniamino Galvani * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
6f6306299SCaesar Wang * Copyright (C) 2014 ROCKCHIP, Inc.
7101353c8SBeniamino Galvani */
8101353c8SBeniamino Galvani
9101353c8SBeniamino Galvani #include <linux/clk.h>
10101353c8SBeniamino Galvani #include <linux/io.h>
11101353c8SBeniamino Galvani #include <linux/module.h>
12101353c8SBeniamino Galvani #include <linux/of.h>
13f6306299SCaesar Wang #include <linux/of_device.h>
14101353c8SBeniamino Galvani #include <linux/platform_device.h>
15101353c8SBeniamino Galvani #include <linux/pwm.h>
16101353c8SBeniamino Galvani #include <linux/time.h>
17101353c8SBeniamino Galvani
18101353c8SBeniamino Galvani #define PWM_CTRL_TIMER_EN (1 << 0)
19101353c8SBeniamino Galvani #define PWM_CTRL_OUTPUT_EN (1 << 3)
20101353c8SBeniamino Galvani
21f6306299SCaesar Wang #define PWM_ENABLE (1 << 0)
22f6306299SCaesar Wang #define PWM_CONTINUOUS (1 << 1)
23f6306299SCaesar Wang #define PWM_DUTY_POSITIVE (1 << 3)
247264354cSDoug Anderson #define PWM_DUTY_NEGATIVE (0 << 3)
25f6306299SCaesar Wang #define PWM_INACTIVE_NEGATIVE (0 << 4)
267264354cSDoug Anderson #define PWM_INACTIVE_POSITIVE (1 << 4)
27bc834d7bSDavid Wu #define PWM_POLARITY_MASK (PWM_DUTY_POSITIVE | PWM_INACTIVE_POSITIVE)
28f6306299SCaesar Wang #define PWM_OUTPUT_LEFT (0 << 5)
293f9a3631SDavid Wu #define PWM_LOCK_EN (1 << 6)
30f6306299SCaesar Wang #define PWM_LP_DISABLE (0 << 8)
31101353c8SBeniamino Galvani
32101353c8SBeniamino Galvani struct rockchip_pwm_chip {
33101353c8SBeniamino Galvani struct pwm_chip chip;
34101353c8SBeniamino Galvani struct clk *clk;
3527922ff5SDavid Wu struct clk *pclk;
36f6306299SCaesar Wang const struct rockchip_pwm_data *data;
37101353c8SBeniamino Galvani void __iomem *base;
38101353c8SBeniamino Galvani };
39101353c8SBeniamino Galvani
40f6306299SCaesar Wang struct rockchip_pwm_regs {
41f6306299SCaesar Wang unsigned long duty;
42f6306299SCaesar Wang unsigned long period;
43f6306299SCaesar Wang unsigned long cntr;
44f6306299SCaesar Wang unsigned long ctrl;
45f6306299SCaesar Wang };
46f6306299SCaesar Wang
47f6306299SCaesar Wang struct rockchip_pwm_data {
48f6306299SCaesar Wang struct rockchip_pwm_regs regs;
49f6306299SCaesar Wang unsigned int prescaler;
502bf1c98aSBoris Brezillon bool supports_polarity;
513f9a3631SDavid Wu bool supports_lock;
52831b2790SDavid Wu u32 enable_conf;
53f6306299SCaesar Wang };
54f6306299SCaesar Wang
to_rockchip_pwm_chip(struct pwm_chip * chip)55*454a8f59SUwe Kleine-König static inline struct rockchip_pwm_chip *to_rockchip_pwm_chip(struct pwm_chip *chip)
56101353c8SBeniamino Galvani {
57*454a8f59SUwe Kleine-König return container_of(chip, struct rockchip_pwm_chip, chip);
58101353c8SBeniamino Galvani }
59101353c8SBeniamino Galvani
rockchip_pwm_get_state(struct pwm_chip * chip,struct pwm_device * pwm,struct pwm_state * state)606c452cffSUwe Kleine-König static int rockchip_pwm_get_state(struct pwm_chip *chip,
611ebb74cfSBoris Brezillon struct pwm_device *pwm,
621ebb74cfSBoris Brezillon struct pwm_state *state)
631ebb74cfSBoris Brezillon {
641ebb74cfSBoris Brezillon struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
65831b2790SDavid Wu u32 enable_conf = pc->data->enable_conf;
661ebb74cfSBoris Brezillon unsigned long clk_rate;
671ebb74cfSBoris Brezillon u64 tmp;
68831b2790SDavid Wu u32 val;
691ebb74cfSBoris Brezillon int ret;
701ebb74cfSBoris Brezillon
7127922ff5SDavid Wu ret = clk_enable(pc->pclk);
721ebb74cfSBoris Brezillon if (ret)
73790a8baeSUwe Kleine-König return ret;
741ebb74cfSBoris Brezillon
7511be938aSSimon South ret = clk_enable(pc->clk);
7611be938aSSimon South if (ret)
77790a8baeSUwe Kleine-König return ret;
7811be938aSSimon South
791ebb74cfSBoris Brezillon clk_rate = clk_get_rate(pc->clk);
801ebb74cfSBoris Brezillon
811ebb74cfSBoris Brezillon tmp = readl_relaxed(pc->base + pc->data->regs.period);
821ebb74cfSBoris Brezillon tmp *= pc->data->prescaler * NSEC_PER_SEC;
831ebb74cfSBoris Brezillon state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
841ebb74cfSBoris Brezillon
851ebb74cfSBoris Brezillon tmp = readl_relaxed(pc->base + pc->data->regs.duty);
861ebb74cfSBoris Brezillon tmp *= pc->data->prescaler * NSEC_PER_SEC;
871ebb74cfSBoris Brezillon state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
881ebb74cfSBoris Brezillon
89831b2790SDavid Wu val = readl_relaxed(pc->base + pc->data->regs.ctrl);
90cad0f296SRasmus Villemoes state->enabled = (val & enable_conf) == enable_conf;
91831b2790SDavid Wu
92ba73deb1SUwe Kleine-König if (pc->data->supports_polarity && !(val & PWM_DUTY_POSITIVE))
93831b2790SDavid Wu state->polarity = PWM_POLARITY_INVERSED;
94ba73deb1SUwe Kleine-König else
95ba73deb1SUwe Kleine-König state->polarity = PWM_POLARITY_NORMAL;
961ebb74cfSBoris Brezillon
9711be938aSSimon South clk_disable(pc->clk);
9827922ff5SDavid Wu clk_disable(pc->pclk);
996c452cffSUwe Kleine-König
1006c452cffSUwe Kleine-König return 0;
1011ebb74cfSBoris Brezillon }
1021ebb74cfSBoris Brezillon
rockchip_pwm_config(struct pwm_chip * chip,struct pwm_device * pwm,const struct pwm_state * state)103f90df9cdSDavid Wu static void rockchip_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
10471523d18SUwe Kleine-König const struct pwm_state *state)
105101353c8SBeniamino Galvani {
106101353c8SBeniamino Galvani struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
107101353c8SBeniamino Galvani unsigned long period, duty;
108101353c8SBeniamino Galvani u64 clk_rate, div;
109bc834d7bSDavid Wu u32 ctrl;
110101353c8SBeniamino Galvani
111101353c8SBeniamino Galvani clk_rate = clk_get_rate(pc->clk);
112101353c8SBeniamino Galvani
113101353c8SBeniamino Galvani /*
114101353c8SBeniamino Galvani * Since period and duty cycle registers have a width of 32
115101353c8SBeniamino Galvani * bits, every possible input period can be obtained using the
116101353c8SBeniamino Galvani * default prescaler value for all practical clock rate values.
117101353c8SBeniamino Galvani */
118bc834d7bSDavid Wu div = clk_rate * state->period;
11912f9ce4aSBoris Brezillon period = DIV_ROUND_CLOSEST_ULL(div,
12012f9ce4aSBoris Brezillon pc->data->prescaler * NSEC_PER_SEC);
121101353c8SBeniamino Galvani
122bc834d7bSDavid Wu div = clk_rate * state->duty_cycle;
12312f9ce4aSBoris Brezillon duty = DIV_ROUND_CLOSEST_ULL(div, pc->data->prescaler * NSEC_PER_SEC);
124101353c8SBeniamino Galvani
1253f9a3631SDavid Wu /*
1263f9a3631SDavid Wu * Lock the period and duty of previous configuration, then
1273f9a3631SDavid Wu * change the duty and period, that would not be effective.
1283f9a3631SDavid Wu */
1293f9a3631SDavid Wu ctrl = readl_relaxed(pc->base + pc->data->regs.ctrl);
1303f9a3631SDavid Wu if (pc->data->supports_lock) {
1313f9a3631SDavid Wu ctrl |= PWM_LOCK_EN;
1323f9a3631SDavid Wu writel_relaxed(ctrl, pc->base + pc->data->regs.ctrl);
1333f9a3631SDavid Wu }
1343f9a3631SDavid Wu
135f6306299SCaesar Wang writel(period, pc->base + pc->data->regs.period);
136f6306299SCaesar Wang writel(duty, pc->base + pc->data->regs.duty);
137bc834d7bSDavid Wu
138bc834d7bSDavid Wu if (pc->data->supports_polarity) {
139bc834d7bSDavid Wu ctrl &= ~PWM_POLARITY_MASK;
140bc834d7bSDavid Wu if (state->polarity == PWM_POLARITY_INVERSED)
141bc834d7bSDavid Wu ctrl |= PWM_DUTY_NEGATIVE | PWM_INACTIVE_POSITIVE;
142bc834d7bSDavid Wu else
143bc834d7bSDavid Wu ctrl |= PWM_DUTY_POSITIVE | PWM_INACTIVE_NEGATIVE;
144bc834d7bSDavid Wu }
1453f9a3631SDavid Wu
1463f9a3631SDavid Wu /*
1473f9a3631SDavid Wu * Unlock and set polarity at the same time,
1483f9a3631SDavid Wu * the configuration of duty, period and polarity
1493f9a3631SDavid Wu * would be effective together at next period.
1503f9a3631SDavid Wu */
1513f9a3631SDavid Wu if (pc->data->supports_lock)
1523f9a3631SDavid Wu ctrl &= ~PWM_LOCK_EN;
1533f9a3631SDavid Wu
154bc834d7bSDavid Wu writel(ctrl, pc->base + pc->data->regs.ctrl);
155101353c8SBeniamino Galvani }
156101353c8SBeniamino Galvani
rockchip_pwm_enable(struct pwm_chip * chip,struct pwm_device * pwm,bool enable)157a900152bSDavid Wu static int rockchip_pwm_enable(struct pwm_chip *chip,
158a900152bSDavid Wu struct pwm_device *pwm,
159831b2790SDavid Wu bool enable)
160a900152bSDavid Wu {
161a900152bSDavid Wu struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
162831b2790SDavid Wu u32 enable_conf = pc->data->enable_conf;
163a900152bSDavid Wu int ret;
164ed054693SDavid Wu u32 val;
165a900152bSDavid Wu
166a900152bSDavid Wu if (enable) {
167a900152bSDavid Wu ret = clk_enable(pc->clk);
168a900152bSDavid Wu if (ret)
169a900152bSDavid Wu return ret;
170a900152bSDavid Wu }
171a900152bSDavid Wu
172ed054693SDavid Wu val = readl_relaxed(pc->base + pc->data->regs.ctrl);
173ed054693SDavid Wu
174ed054693SDavid Wu if (enable)
175ed054693SDavid Wu val |= enable_conf;
176ed054693SDavid Wu else
177ed054693SDavid Wu val &= ~enable_conf;
178ed054693SDavid Wu
179ed054693SDavid Wu writel_relaxed(val, pc->base + pc->data->regs.ctrl);
180a900152bSDavid Wu
181a900152bSDavid Wu if (!enable)
182a900152bSDavid Wu clk_disable(pc->clk);
183a900152bSDavid Wu
184a900152bSDavid Wu return 0;
185a900152bSDavid Wu }
186a900152bSDavid Wu
rockchip_pwm_apply(struct pwm_chip * chip,struct pwm_device * pwm,const struct pwm_state * state)187ed054693SDavid Wu static int rockchip_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
18871523d18SUwe Kleine-König const struct pwm_state *state)
189ed054693SDavid Wu {
190ed054693SDavid Wu struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
191831b2790SDavid Wu struct pwm_state curstate;
192831b2790SDavid Wu bool enabled;
193831b2790SDavid Wu int ret = 0;
194ed054693SDavid Wu
195ed054693SDavid Wu ret = clk_enable(pc->pclk);
196ed054693SDavid Wu if (ret)
197ed054693SDavid Wu return ret;
198ed054693SDavid Wu
19911be938aSSimon South ret = clk_enable(pc->clk);
20011be938aSSimon South if (ret)
20111be938aSSimon South return ret;
20211be938aSSimon South
203831b2790SDavid Wu pwm_get_state(pwm, &curstate);
204831b2790SDavid Wu enabled = curstate.enabled;
205831b2790SDavid Wu
2063f9a3631SDavid Wu if (state->polarity != curstate.polarity && enabled &&
2073f9a3631SDavid Wu !pc->data->supports_lock) {
208831b2790SDavid Wu ret = rockchip_pwm_enable(chip, pwm, false);
209a900152bSDavid Wu if (ret)
210a900152bSDavid Wu goto out;
211831b2790SDavid Wu enabled = false;
212831b2790SDavid Wu }
213831b2790SDavid Wu
214831b2790SDavid Wu rockchip_pwm_config(chip, pwm, state);
215831b2790SDavid Wu if (state->enabled != enabled) {
216831b2790SDavid Wu ret = rockchip_pwm_enable(chip, pwm, state->enabled);
217831b2790SDavid Wu if (ret)
218831b2790SDavid Wu goto out;
219831b2790SDavid Wu }
2202bf1c98aSBoris Brezillon
2212bf1c98aSBoris Brezillon out:
22211be938aSSimon South clk_disable(pc->clk);
22327922ff5SDavid Wu clk_disable(pc->pclk);
2242bf1c98aSBoris Brezillon
2252bf1c98aSBoris Brezillon return ret;
226101353c8SBeniamino Galvani }
227101353c8SBeniamino Galvani
228831b2790SDavid Wu static const struct pwm_ops rockchip_pwm_ops = {
2291ebb74cfSBoris Brezillon .get_state = rockchip_pwm_get_state,
2302bf1c98aSBoris Brezillon .apply = rockchip_pwm_apply,
2317264354cSDoug Anderson .owner = THIS_MODULE,
2327264354cSDoug Anderson };
2337264354cSDoug Anderson
234f6306299SCaesar Wang static const struct rockchip_pwm_data pwm_data_v1 = {
235f6306299SCaesar Wang .regs = {
236f6306299SCaesar Wang .duty = 0x04,
237f6306299SCaesar Wang .period = 0x08,
238f6306299SCaesar Wang .cntr = 0x00,
239f6306299SCaesar Wang .ctrl = 0x0c,
240f6306299SCaesar Wang },
241f6306299SCaesar Wang .prescaler = 2,
242831b2790SDavid Wu .supports_polarity = false,
2433f9a3631SDavid Wu .supports_lock = false,
244831b2790SDavid Wu .enable_conf = PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN,
245f6306299SCaesar Wang };
246f6306299SCaesar Wang
247f6306299SCaesar Wang static const struct rockchip_pwm_data pwm_data_v2 = {
248f6306299SCaesar Wang .regs = {
249f6306299SCaesar Wang .duty = 0x08,
250f6306299SCaesar Wang .period = 0x04,
251f6306299SCaesar Wang .cntr = 0x00,
252f6306299SCaesar Wang .ctrl = 0x0c,
253f6306299SCaesar Wang },
254f6306299SCaesar Wang .prescaler = 1,
2552bf1c98aSBoris Brezillon .supports_polarity = true,
2563f9a3631SDavid Wu .supports_lock = false,
257831b2790SDavid Wu .enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE |
258831b2790SDavid Wu PWM_CONTINUOUS,
259f6306299SCaesar Wang };
260f6306299SCaesar Wang
261f6306299SCaesar Wang static const struct rockchip_pwm_data pwm_data_vop = {
262f6306299SCaesar Wang .regs = {
263f6306299SCaesar Wang .duty = 0x08,
264f6306299SCaesar Wang .period = 0x04,
265f6306299SCaesar Wang .cntr = 0x0c,
266f6306299SCaesar Wang .ctrl = 0x00,
267f6306299SCaesar Wang },
268f6306299SCaesar Wang .prescaler = 1,
2692bf1c98aSBoris Brezillon .supports_polarity = true,
2703f9a3631SDavid Wu .supports_lock = false,
2713f9a3631SDavid Wu .enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE |
2723f9a3631SDavid Wu PWM_CONTINUOUS,
2733f9a3631SDavid Wu };
2743f9a3631SDavid Wu
2753f9a3631SDavid Wu static const struct rockchip_pwm_data pwm_data_v3 = {
2763f9a3631SDavid Wu .regs = {
2773f9a3631SDavid Wu .duty = 0x08,
2783f9a3631SDavid Wu .period = 0x04,
2793f9a3631SDavid Wu .cntr = 0x00,
2803f9a3631SDavid Wu .ctrl = 0x0c,
2813f9a3631SDavid Wu },
2823f9a3631SDavid Wu .prescaler = 1,
2833f9a3631SDavid Wu .supports_polarity = true,
2843f9a3631SDavid Wu .supports_lock = true,
285831b2790SDavid Wu .enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE |
286831b2790SDavid Wu PWM_CONTINUOUS,
287f6306299SCaesar Wang };
288f6306299SCaesar Wang
289f6306299SCaesar Wang static const struct of_device_id rockchip_pwm_dt_ids[] = {
290f6306299SCaesar Wang { .compatible = "rockchip,rk2928-pwm", .data = &pwm_data_v1},
291f6306299SCaesar Wang { .compatible = "rockchip,rk3288-pwm", .data = &pwm_data_v2},
292f6306299SCaesar Wang { .compatible = "rockchip,vop-pwm", .data = &pwm_data_vop},
2933f9a3631SDavid Wu { .compatible = "rockchip,rk3328-pwm", .data = &pwm_data_v3},
294f6306299SCaesar Wang { /* sentinel */ }
295f6306299SCaesar Wang };
296f6306299SCaesar Wang MODULE_DEVICE_TABLE(of, rockchip_pwm_dt_ids);
297f6306299SCaesar Wang
rockchip_pwm_probe(struct platform_device * pdev)298101353c8SBeniamino Galvani static int rockchip_pwm_probe(struct platform_device *pdev)
299101353c8SBeniamino Galvani {
300f6306299SCaesar Wang const struct of_device_id *id;
301101353c8SBeniamino Galvani struct rockchip_pwm_chip *pc;
302457f74abSSimon South u32 enable_conf, ctrl;
303d21ba5d6SSimon South bool enabled;
30427922ff5SDavid Wu int ret, count;
305101353c8SBeniamino Galvani
306f6306299SCaesar Wang id = of_match_device(rockchip_pwm_dt_ids, &pdev->dev);
307f6306299SCaesar Wang if (!id)
308f6306299SCaesar Wang return -EINVAL;
309f6306299SCaesar Wang
310101353c8SBeniamino Galvani pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
311101353c8SBeniamino Galvani if (!pc)
312101353c8SBeniamino Galvani return -ENOMEM;
313101353c8SBeniamino Galvani
3145119ee9eSYangtao Li pc->base = devm_platform_ioremap_resource(pdev, 0);
315101353c8SBeniamino Galvani if (IS_ERR(pc->base))
316101353c8SBeniamino Galvani return PTR_ERR(pc->base);
317101353c8SBeniamino Galvani
31827922ff5SDavid Wu pc->clk = devm_clk_get(&pdev->dev, "pwm");
31927922ff5SDavid Wu if (IS_ERR(pc->clk)) {
320101353c8SBeniamino Galvani pc->clk = devm_clk_get(&pdev->dev, NULL);
321836719f8SKrzysztof Kozlowski if (IS_ERR(pc->clk))
322836719f8SKrzysztof Kozlowski return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk),
323c9f809d0SSimon South "Can't get PWM clk\n");
32427922ff5SDavid Wu }
32527922ff5SDavid Wu
32627922ff5SDavid Wu count = of_count_phandle_with_args(pdev->dev.of_node,
32727922ff5SDavid Wu "clocks", "#clock-cells");
32827922ff5SDavid Wu if (count == 2)
32927922ff5SDavid Wu pc->pclk = devm_clk_get(&pdev->dev, "pclk");
33027922ff5SDavid Wu else
33127922ff5SDavid Wu pc->pclk = pc->clk;
33227922ff5SDavid Wu
3334b8857c3Szhaoxiao if (IS_ERR(pc->pclk))
3344b8857c3Szhaoxiao return dev_err_probe(&pdev->dev, PTR_ERR(pc->pclk), "Can't get APB clk\n");
335101353c8SBeniamino Galvani
33648cf973cSBoris Brezillon ret = clk_prepare_enable(pc->clk);
3374b8857c3Szhaoxiao if (ret)
3384b8857c3Szhaoxiao return dev_err_probe(&pdev->dev, ret, "Can't prepare enable PWM clk\n");
33927922ff5SDavid Wu
340d9b657a5SSimon South ret = clk_prepare_enable(pc->pclk);
34127922ff5SDavid Wu if (ret) {
3424b8857c3Szhaoxiao dev_err_probe(&pdev->dev, ret, "Can't prepare enable APB clk\n");
34327922ff5SDavid Wu goto err_clk;
34427922ff5SDavid Wu }
345101353c8SBeniamino Galvani
346101353c8SBeniamino Galvani platform_set_drvdata(pdev, pc);
347101353c8SBeniamino Galvani
348f6306299SCaesar Wang pc->data = id->data;
349101353c8SBeniamino Galvani pc->chip.dev = &pdev->dev;
350831b2790SDavid Wu pc->chip.ops = &rockchip_pwm_ops;
351101353c8SBeniamino Galvani pc->chip.npwm = 1;
352101353c8SBeniamino Galvani
353d21ba5d6SSimon South enable_conf = pc->data->enable_conf;
354d21ba5d6SSimon South ctrl = readl_relaxed(pc->base + pc->data->regs.ctrl);
355d21ba5d6SSimon South enabled = (ctrl & enable_conf) == enable_conf;
356d21ba5d6SSimon South
357101353c8SBeniamino Galvani ret = pwmchip_add(&pc->chip);
358101353c8SBeniamino Galvani if (ret < 0) {
3594b8857c3Szhaoxiao dev_err_probe(&pdev->dev, ret, "pwmchip_add() failed\n");
36027922ff5SDavid Wu goto err_pclk;
361101353c8SBeniamino Galvani }
362101353c8SBeniamino Galvani
36348cf973cSBoris Brezillon /* Keep the PWM clk enabled if the PWM appears to be up and running. */
364d21ba5d6SSimon South if (!enabled)
36548cf973cSBoris Brezillon clk_disable(pc->clk);
36648cf973cSBoris Brezillon
367d9b657a5SSimon South clk_disable(pc->pclk);
368d9b657a5SSimon South
36927922ff5SDavid Wu return 0;
37027922ff5SDavid Wu
37127922ff5SDavid Wu err_pclk:
372d9b657a5SSimon South clk_disable_unprepare(pc->pclk);
37327922ff5SDavid Wu err_clk:
37427922ff5SDavid Wu clk_disable_unprepare(pc->clk);
37527922ff5SDavid Wu
376101353c8SBeniamino Galvani return ret;
377101353c8SBeniamino Galvani }
378101353c8SBeniamino Galvani
rockchip_pwm_remove(struct platform_device * pdev)37918a95d36SUwe Kleine-König static void rockchip_pwm_remove(struct platform_device *pdev)
380101353c8SBeniamino Galvani {
381101353c8SBeniamino Galvani struct rockchip_pwm_chip *pc = platform_get_drvdata(pdev);
382101353c8SBeniamino Galvani
38384ea61f6SUwe Kleine-König pwmchip_remove(&pc->chip);
38484ea61f6SUwe Kleine-König
38527922ff5SDavid Wu clk_unprepare(pc->pclk);
386101353c8SBeniamino Galvani clk_unprepare(pc->clk);
387101353c8SBeniamino Galvani }
388101353c8SBeniamino Galvani
389101353c8SBeniamino Galvani static struct platform_driver rockchip_pwm_driver = {
390101353c8SBeniamino Galvani .driver = {
391101353c8SBeniamino Galvani .name = "rockchip-pwm",
392101353c8SBeniamino Galvani .of_match_table = rockchip_pwm_dt_ids,
393101353c8SBeniamino Galvani },
394101353c8SBeniamino Galvani .probe = rockchip_pwm_probe,
39518a95d36SUwe Kleine-König .remove_new = rockchip_pwm_remove,
396101353c8SBeniamino Galvani };
397101353c8SBeniamino Galvani module_platform_driver(rockchip_pwm_driver);
398101353c8SBeniamino Galvani
399101353c8SBeniamino Galvani MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>");
400101353c8SBeniamino Galvani MODULE_DESCRIPTION("Rockchip SoC PWM driver");
401101353c8SBeniamino Galvani MODULE_LICENSE("GPL v2");
402