dts/rockchip/rk3036.dtsi

1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3036-cru.h>
8 #include <dt-bindings/soc/rockchip,boot-mode.h>
9 #include <dt-bindings/power/rk3036-power.h>
12 	#address-cells = <1>;
13 	#size-cells = <1>;
17 	interrupt-parent = <&gic>;
33 		#address-cells = <1>;
34 		#size-cells = <0>;
35 		enable-method = "rockchip,rk3036-smp";
39 			compatible = "arm,cortex-a7";
42 			operating-points = <
46 			clock-latency = <40000>;
52 			compatible = "arm,cortex-a7";
58 	arm-pmu {
59 		compatible = "arm,cortex-a7-pmu";
62 		interrupt-affinity = <&cpu0>, <&cpu1>;
65 	display-subsystem {
66 		compatible = "rockchip,display-subsystem";
71 		compatible = "arm,armv7-timer";
72 		arm,cpu-registers-not-fw-configured;
77 		clock-frequency = <24000000>;
81 		compatible = "fixed-clock";
82 		clock-frequency = <24000000>;
83 		clock-output-names = "xin24m";
84 		#clock-cells = <0>;
88 		compatible = "mmio-sram";
90 		#address-cells = <1>;
91 		#size-cells = <1>;
94 		smp-sram@0 {
95 			compatible = "rockchip,rk3066-smp-sram";
101 		compatible = "rockchip,rk3036-mali", "arm,mali-400";
107 		interrupt-names = "gp",
111 		assigned-clocks = <&cru SCLK_GPU>;
112 		assigned-clock-rates = <100000000>;
114 		clock-names = "bus", "core";
115 		power-domains = <&power RK3036_PD_GPU>;
120 	vpu: video-codec@10108000 {
121 		compatible = "rockchip,rk3036-vpu";
124 		interrupt-names = "vdpu";
126 		clock-names = "aclk", "hclk";
128 		power-domains = <&power RK3036_PD_VPU>;
136 		clock-names = "aclk", "iface";
137 		power-domains = <&power RK3036_PD_VPU>;
138 		#iommu-cells = <0>;
141 	vop: vop@10118000 {  label
142 		compatible = "rockchip,rk3036-vop";
146 		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
148 		reset-names = "axi", "ahb", "dclk";
150 		power-domains = <&power RK3036_PD_VIO>;
154 			#address-cells = <1>;
155 			#size-cells = <0>;
158 				remote-endpoint = <&hdmi_in_vop>;
168 		clock-names = "aclk", "iface";
169 		power-domains = <&power RK3036_PD_VIO>;
170 		#iommu-cells = <0>;
175 		compatible = "rockchip,rk3036-qos", "syscon";
180 		compatible = "rockchip,rk3036-qos", "syscon";
185 		compatible = "rockchip,rk3036-qos", "syscon";
189 	gic: interrupt-controller@10139000 {
190 		compatible = "arm,gic-400";
191 		interrupt-controller;
192 		#interrupt-cells = <3>;
193 		#address-cells = <0>;
203 		compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
208 		clock-names = "otg";
210 		g-np-tx-fifo-size = <16>;
211 		g-rx-fifo-size = <275>;
212 		g-tx-fifo-size = <256 128 128 64 64 32>;
217 		compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
222 		clock-names = "otg";
228 		compatible = "rockchip,rk3036-emac";
233 		clock-names = "hclk", "macref", "macclk";
239 		assigned-clocks = <&cru SCLK_MACPLL>;
240 		assigned-clock-parents = <&cru PLL_DPLL>;
241 		max-speed = <100>;
242 		phy-mode = "rmii";
247 		compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
249 		clock-frequency = <37500000>;
250 		max-frequency = <37500000>;
252 		clock-names = "biu", "ciu";
253 		fifo-depth = <0x100>;
256 		reset-names = "reset";
261 		compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
263 		max-frequency = <37500000>;
266 		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
267 		fifo-depth = <0x100>;
270 		reset-names = "reset";
275 		compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
278 		bus-width = <8>;
279 		cap-mmc-highspeed;
280 		clock-frequency = <37500000>;
281 		max-frequency = <37500000>;
284 		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
285 		rockchip,default-sample-phase = <158>;
286 		disable-wp;
288 		dma-names = "rx-tx";
289 		fifo-depth = <0x100>;
290 		mmc-ddr-1_8v;
291 		non-removable;
292 		pinctrl-names = "default";
293 		pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
295 		reset-names = "reset";
300 		compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s";
303 		clock-names = "i2s_clk", "i2s_hclk";
306 		dma-names = "tx", "rx";
307 		pinctrl-names = "default";
308 		pinctrl-0 = <&i2s_bus>;
309 		#sound-dai-cells = <0>;
313 	nfc: nand-controller@10500000 {
314 		compatible = "rockchip,rk3036-nfc",
315 			     "rockchip,rk2928-nfc";
319 		clock-names = "ahb", "nfc";
320 		assigned-clocks = <&cru SCLK_NANDC>;
321 		assigned-clock-rates = <150000000>;
322 		pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0
324 		pinctrl-names = "default";
328 	cru: clock-controller@20000000 {
329 		compatible = "rockchip,rk3036-cru";
332 		clock-names = "xin24m";
334 		#clock-cells = <1>;
335 		#reset-cells = <1>;
336 		assigned-clocks = <&cru PLL_GPLL>;
337 		assigned-clock-rates = <594000000>;
341 		compatible = "rockchip,rk3036-grf", "syscon", "simple-mfd";
344 		power: power-controller {
345 			compatible = "rockchip,rk3036-power-controller";
346 			#power-domain-cells = <1>;
347 			#address-cells = <1>;
348 			#size-cells = <0>;
350 			power-domain@RK3036_PD_VIO {
356 				#power-domain-cells = <0>;
359 			power-domain@RK3036_PD_VPU {
364 				#power-domain-cells = <0>;
367 			power-domain@RK3036_PD_GPU {
371 				#power-domain-cells = <0>;
375 		reboot-mode {
376 			compatible = "syscon-reboot-mode";
378 			mode-normal = <BOOT_NORMAL>;
379 			mode-recovery = <BOOT_RECOVERY>;
380 			mode-bootloader = <BOOT_FASTBOOT>;
381 			mode-loader = <BOOT_BL_DOWNLOAD>;
385 	acodec: audio-codec@20030000 {
386 		compatible = "rockchip,rk3036-codec";
388 		clock-names = "acodec_pclk";
391 		#sound-dai-cells = <0>;
396 		compatible = "rockchip,rk3036-inno-hdmi";
400 		clock-names = "pclk";
401 		pinctrl-names = "default";
402 		pinctrl-0 = <&hdmi_ctl>;
406 			#address-cells = <1>;
407 			#size-cells = <0>;
413 					remote-endpoint = <&vop_out_hdmi>;
424 		compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer";
428 		clock-names = "pclk", "timer";
432 		compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
434 		#pwm-cells = <3>;
436 		pinctrl-names = "default";
437 		pinctrl-0 = <&pwm0_pin>;
442 		compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
444 		#pwm-cells = <3>;
446 		pinctrl-names = "default";
447 		pinctrl-0 = <&pwm1_pin>;
452 		compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
454 		#pwm-cells = <3>;
456 		pinctrl-names = "default";
457 		pinctrl-0 = <&pwm2_pin>;
462 		compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
464 		#pwm-cells = <2>;
466 		pinctrl-names = "default";
467 		pinctrl-0 = <&pwm3_pin>;
472 		compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
475 		#address-cells = <1>;
476 		#size-cells = <0>;
477 		clock-names = "i2c";
479 		pinctrl-names = "default";
480 		pinctrl-0 = <&i2c1_xfer>;
485 		compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
488 		#address-cells = <1>;
489 		#size-cells = <0>;
490 		clock-names = "i2c";
492 		pinctrl-names = "default";
493 		pinctrl-0 = <&i2c2_xfer>;
498 		compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
501 		reg-shift = <2>;
502 		reg-io-width = <4>;
503 		clock-frequency = <24000000>;
505 		clock-names = "baudclk", "apb_pclk";
506 		pinctrl-names = "default";
507 		pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
512 		compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
515 		reg-shift = <2>;
516 		reg-io-width = <4>;
517 		clock-frequency = <24000000>;
519 		clock-names = "baudclk", "apb_pclk";
520 		pinctrl-names = "default";
521 		pinctrl-0 = <&uart1_xfer>;
526 		compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
529 		reg-shift = <2>;
530 		reg-io-width = <4>;
531 		clock-frequency = <24000000>;
533 		clock-names = "baudclk", "apb_pclk";
534 		pinctrl-names = "default";
535 		pinctrl-0 = <&uart2_xfer>;
540 		compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
543 		#address-cells = <1>;
544 		#size-cells = <0>;
545 		clock-names = "i2c";
547 		pinctrl-names = "default";
548 		pinctrl-0 = <&i2c0_xfer>;
553 		compatible = "rockchip,rk3036-spi";
557 		clock-names = "spiclk", "apb_pclk";
559 		dma-names = "tx", "rx";
560 		pinctrl-names = "default";
561 		pinctrl-0 = <&spi_txd &spi_rxd &spi_clk &spi_cs0>;
562 		#address-cells = <1>;
563 		#size-cells = <0>;
567 	pdma: dma-controller@20078000 {
572 		#dma-cells = <1>;
573 		arm,pl330-broken-no-flushp;
574 		arm,pl330-periph-burst;
576 		clock-names = "apb_pclk";
580 		compatible = "rockchip,rk3036-pinctrl";
582 		#address-cells = <1>;
583 		#size-cells = <1>;
587 			compatible = "rockchip,gpio-bank";
592 			gpio-controller;
593 			#gpio-cells = <2>;
595 			interrupt-controller;
596 			#interrupt-cells = <2>;
600 			compatible = "rockchip,gpio-bank";
605 			gpio-controller;
606 			#gpio-cells = <2>;
608 			interrupt-controller;
609 			#interrupt-cells = <2>;
613 			compatible = "rockchip,gpio-bank";
618 			gpio-controller;
619 			#gpio-cells = <2>;
621 			interrupt-controller;
622 			#interrupt-cells = <2>;
625 		pcfg_pull_default: pcfg-pull-default {
626 			bias-pull-pin-default;
629 		pcfg_pull_none: pcfg-pull-none {
630 			bias-disable;
634 			pwm0_pin: pwm0-pin {
640 			pwm1_pin: pwm1-pin {
646 			pwm2_pin: pwm2-pin {
652 			pwm3_pin: pwm3-pin {
658 			sdmmc_clk: sdmmc-clk {
662 			sdmmc_cmd: sdmmc-cmd {
666 			sdmmc_cd: sdmmc-cd {
670 			sdmmc_bus1: sdmmc-bus1 {
674 			sdmmc_bus4: sdmmc-bus4 {
683 			sdio_bus1: sdio-bus1 {
687 			sdio_bus4: sdio-bus4 {
694 			sdio_cmd: sdio-cmd {
698 			sdio_clk: sdio-clk {
708 			emmc_clk: emmc-clk {
712 			emmc_cmd: emmc-cmd {
716 			emmc_bus8: emmc-bus8 {
729 			flash_ale: flash-ale {
733 			flash_bus8: flash-bus8 {
744 			flash_cle: flash-cle {
748 			flash_csn0: flash-csn0 {
752 			flash_rdn: flash-rdn {
756 			flash_rdy: flash-rdy {
760 			flash_wrn: flash-wrn {
766 			emac_xfer: emac-xfer {
777 			emac_mdio: emac-mdio {
784 			i2c0_xfer: i2c0-xfer {
791 			i2c1_xfer: i2c1-xfer {
798 			i2c2_xfer: i2c2-xfer {
805 			i2s_bus: i2s-bus {
816 			hdmi_ctl: hdmi-ctl {
825 			uart0_xfer: uart0-xfer {
830 			uart0_cts: uart0-cts {
834 			uart0_rts: uart0-rts {
840 			uart1_xfer: uart1-xfer {
848 			uart2_xfer: uart2-xfer {
855 		spi-pins {
856 			spi_txd:spi-txd {
860 			spi_rxd:spi-rxd {
864 			spi_clk:spi-clk {
868 			spi_cs0:spi-cs0 {
873 			spi_cs1:spi-cs1 {