xref: /openbmc/linux/drivers/pwm/pwm-rockchip.c (revision 454a8f59)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * PWM driver for Rockchip SoCs
4  *
5  * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
6  * Copyright (C) 2014 ROCKCHIP, Inc.
7  */
8 
9 #include <linux/clk.h>
10 #include <linux/io.h>
11 #include <linux/module.h>
12 #include <linux/of.h>
13 #include <linux/of_device.h>
14 #include <linux/platform_device.h>
15 #include <linux/pwm.h>
16 #include <linux/time.h>
17 
18 #define PWM_CTRL_TIMER_EN	(1 << 0)
19 #define PWM_CTRL_OUTPUT_EN	(1 << 3)
20 
21 #define PWM_ENABLE		(1 << 0)
22 #define PWM_CONTINUOUS		(1 << 1)
23 #define PWM_DUTY_POSITIVE	(1 << 3)
24 #define PWM_DUTY_NEGATIVE	(0 << 3)
25 #define PWM_INACTIVE_NEGATIVE	(0 << 4)
26 #define PWM_INACTIVE_POSITIVE	(1 << 4)
27 #define PWM_POLARITY_MASK	(PWM_DUTY_POSITIVE | PWM_INACTIVE_POSITIVE)
28 #define PWM_OUTPUT_LEFT		(0 << 5)
29 #define PWM_LOCK_EN		(1 << 6)
30 #define PWM_LP_DISABLE		(0 << 8)
31 
32 struct rockchip_pwm_chip {
33 	struct pwm_chip chip;
34 	struct clk *clk;
35 	struct clk *pclk;
36 	const struct rockchip_pwm_data *data;
37 	void __iomem *base;
38 };
39 
40 struct rockchip_pwm_regs {
41 	unsigned long duty;
42 	unsigned long period;
43 	unsigned long cntr;
44 	unsigned long ctrl;
45 };
46 
47 struct rockchip_pwm_data {
48 	struct rockchip_pwm_regs regs;
49 	unsigned int prescaler;
50 	bool supports_polarity;
51 	bool supports_lock;
52 	u32 enable_conf;
53 };
54 
to_rockchip_pwm_chip(struct pwm_chip * chip)55 static inline struct rockchip_pwm_chip *to_rockchip_pwm_chip(struct pwm_chip *chip)
56 {
57 	return container_of(chip, struct rockchip_pwm_chip, chip);
58 }
59 
rockchip_pwm_get_state(struct pwm_chip * chip,struct pwm_device * pwm,struct pwm_state * state)60 static int rockchip_pwm_get_state(struct pwm_chip *chip,
61 				  struct pwm_device *pwm,
62 				  struct pwm_state *state)
63 {
64 	struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
65 	u32 enable_conf = pc->data->enable_conf;
66 	unsigned long clk_rate;
67 	u64 tmp;
68 	u32 val;
69 	int ret;
70 
71 	ret = clk_enable(pc->pclk);
72 	if (ret)
73 		return ret;
74 
75 	ret = clk_enable(pc->clk);
76 	if (ret)
77 		return ret;
78 
79 	clk_rate = clk_get_rate(pc->clk);
80 
81 	tmp = readl_relaxed(pc->base + pc->data->regs.period);
82 	tmp *= pc->data->prescaler * NSEC_PER_SEC;
83 	state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
84 
85 	tmp = readl_relaxed(pc->base + pc->data->regs.duty);
86 	tmp *= pc->data->prescaler * NSEC_PER_SEC;
87 	state->duty_cycle =  DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
88 
89 	val = readl_relaxed(pc->base + pc->data->regs.ctrl);
90 	state->enabled = (val & enable_conf) == enable_conf;
91 
92 	if (pc->data->supports_polarity && !(val & PWM_DUTY_POSITIVE))
93 		state->polarity = PWM_POLARITY_INVERSED;
94 	else
95 		state->polarity = PWM_POLARITY_NORMAL;
96 
97 	clk_disable(pc->clk);
98 	clk_disable(pc->pclk);
99 
100 	return 0;
101 }
102 
rockchip_pwm_config(struct pwm_chip * chip,struct pwm_device * pwm,const struct pwm_state * state)103 static void rockchip_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
104 			       const struct pwm_state *state)
105 {
106 	struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
107 	unsigned long period, duty;
108 	u64 clk_rate, div;
109 	u32 ctrl;
110 
111 	clk_rate = clk_get_rate(pc->clk);
112 
113 	/*
114 	 * Since period and duty cycle registers have a width of 32
115 	 * bits, every possible input period can be obtained using the
116 	 * default prescaler value for all practical clock rate values.
117 	 */
118 	div = clk_rate * state->period;
119 	period = DIV_ROUND_CLOSEST_ULL(div,
120 				       pc->data->prescaler * NSEC_PER_SEC);
121 
122 	div = clk_rate * state->duty_cycle;
123 	duty = DIV_ROUND_CLOSEST_ULL(div, pc->data->prescaler * NSEC_PER_SEC);
124 
125 	/*
126 	 * Lock the period and duty of previous configuration, then
127 	 * change the duty and period, that would not be effective.
128 	 */
129 	ctrl = readl_relaxed(pc->base + pc->data->regs.ctrl);
130 	if (pc->data->supports_lock) {
131 		ctrl |= PWM_LOCK_EN;
132 		writel_relaxed(ctrl, pc->base + pc->data->regs.ctrl);
133 	}
134 
135 	writel(period, pc->base + pc->data->regs.period);
136 	writel(duty, pc->base + pc->data->regs.duty);
137 
138 	if (pc->data->supports_polarity) {
139 		ctrl &= ~PWM_POLARITY_MASK;
140 		if (state->polarity == PWM_POLARITY_INVERSED)
141 			ctrl |= PWM_DUTY_NEGATIVE | PWM_INACTIVE_POSITIVE;
142 		else
143 			ctrl |= PWM_DUTY_POSITIVE | PWM_INACTIVE_NEGATIVE;
144 	}
145 
146 	/*
147 	 * Unlock and set polarity at the same time,
148 	 * the configuration of duty, period and polarity
149 	 * would be effective together at next period.
150 	 */
151 	if (pc->data->supports_lock)
152 		ctrl &= ~PWM_LOCK_EN;
153 
154 	writel(ctrl, pc->base + pc->data->regs.ctrl);
155 }
156 
rockchip_pwm_enable(struct pwm_chip * chip,struct pwm_device * pwm,bool enable)157 static int rockchip_pwm_enable(struct pwm_chip *chip,
158 			       struct pwm_device *pwm,
159 			       bool enable)
160 {
161 	struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
162 	u32 enable_conf = pc->data->enable_conf;
163 	int ret;
164 	u32 val;
165 
166 	if (enable) {
167 		ret = clk_enable(pc->clk);
168 		if (ret)
169 			return ret;
170 	}
171 
172 	val = readl_relaxed(pc->base + pc->data->regs.ctrl);
173 
174 	if (enable)
175 		val |= enable_conf;
176 	else
177 		val &= ~enable_conf;
178 
179 	writel_relaxed(val, pc->base + pc->data->regs.ctrl);
180 
181 	if (!enable)
182 		clk_disable(pc->clk);
183 
184 	return 0;
185 }
186 
rockchip_pwm_apply(struct pwm_chip * chip,struct pwm_device * pwm,const struct pwm_state * state)187 static int rockchip_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
188 			      const struct pwm_state *state)
189 {
190 	struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
191 	struct pwm_state curstate;
192 	bool enabled;
193 	int ret = 0;
194 
195 	ret = clk_enable(pc->pclk);
196 	if (ret)
197 		return ret;
198 
199 	ret = clk_enable(pc->clk);
200 	if (ret)
201 		return ret;
202 
203 	pwm_get_state(pwm, &curstate);
204 	enabled = curstate.enabled;
205 
206 	if (state->polarity != curstate.polarity && enabled &&
207 	    !pc->data->supports_lock) {
208 		ret = rockchip_pwm_enable(chip, pwm, false);
209 		if (ret)
210 			goto out;
211 		enabled = false;
212 	}
213 
214 	rockchip_pwm_config(chip, pwm, state);
215 	if (state->enabled != enabled) {
216 		ret = rockchip_pwm_enable(chip, pwm, state->enabled);
217 		if (ret)
218 			goto out;
219 	}
220 
221 out:
222 	clk_disable(pc->clk);
223 	clk_disable(pc->pclk);
224 
225 	return ret;
226 }
227 
228 static const struct pwm_ops rockchip_pwm_ops = {
229 	.get_state = rockchip_pwm_get_state,
230 	.apply = rockchip_pwm_apply,
231 	.owner = THIS_MODULE,
232 };
233 
234 static const struct rockchip_pwm_data pwm_data_v1 = {
235 	.regs = {
236 		.duty = 0x04,
237 		.period = 0x08,
238 		.cntr = 0x00,
239 		.ctrl = 0x0c,
240 	},
241 	.prescaler = 2,
242 	.supports_polarity = false,
243 	.supports_lock = false,
244 	.enable_conf = PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN,
245 };
246 
247 static const struct rockchip_pwm_data pwm_data_v2 = {
248 	.regs = {
249 		.duty = 0x08,
250 		.period = 0x04,
251 		.cntr = 0x00,
252 		.ctrl = 0x0c,
253 	},
254 	.prescaler = 1,
255 	.supports_polarity = true,
256 	.supports_lock = false,
257 	.enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE |
258 		       PWM_CONTINUOUS,
259 };
260 
261 static const struct rockchip_pwm_data pwm_data_vop = {
262 	.regs = {
263 		.duty = 0x08,
264 		.period = 0x04,
265 		.cntr = 0x0c,
266 		.ctrl = 0x00,
267 	},
268 	.prescaler = 1,
269 	.supports_polarity = true,
270 	.supports_lock = false,
271 	.enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE |
272 		       PWM_CONTINUOUS,
273 };
274 
275 static const struct rockchip_pwm_data pwm_data_v3 = {
276 	.regs = {
277 		.duty = 0x08,
278 		.period = 0x04,
279 		.cntr = 0x00,
280 		.ctrl = 0x0c,
281 	},
282 	.prescaler = 1,
283 	.supports_polarity = true,
284 	.supports_lock = true,
285 	.enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE |
286 		       PWM_CONTINUOUS,
287 };
288 
289 static const struct of_device_id rockchip_pwm_dt_ids[] = {
290 	{ .compatible = "rockchip,rk2928-pwm", .data = &pwm_data_v1},
291 	{ .compatible = "rockchip,rk3288-pwm", .data = &pwm_data_v2},
292 	{ .compatible = "rockchip,vop-pwm", .data = &pwm_data_vop},
293 	{ .compatible = "rockchip,rk3328-pwm", .data = &pwm_data_v3},
294 	{ /* sentinel */ }
295 };
296 MODULE_DEVICE_TABLE(of, rockchip_pwm_dt_ids);
297 
rockchip_pwm_probe(struct platform_device * pdev)298 static int rockchip_pwm_probe(struct platform_device *pdev)
299 {
300 	const struct of_device_id *id;
301 	struct rockchip_pwm_chip *pc;
302 	u32 enable_conf, ctrl;
303 	bool enabled;
304 	int ret, count;
305 
306 	id = of_match_device(rockchip_pwm_dt_ids, &pdev->dev);
307 	if (!id)
308 		return -EINVAL;
309 
310 	pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
311 	if (!pc)
312 		return -ENOMEM;
313 
314 	pc->base = devm_platform_ioremap_resource(pdev, 0);
315 	if (IS_ERR(pc->base))
316 		return PTR_ERR(pc->base);
317 
318 	pc->clk = devm_clk_get(&pdev->dev, "pwm");
319 	if (IS_ERR(pc->clk)) {
320 		pc->clk = devm_clk_get(&pdev->dev, NULL);
321 		if (IS_ERR(pc->clk))
322 			return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk),
323 					     "Can't get PWM clk\n");
324 	}
325 
326 	count = of_count_phandle_with_args(pdev->dev.of_node,
327 					   "clocks", "#clock-cells");
328 	if (count == 2)
329 		pc->pclk = devm_clk_get(&pdev->dev, "pclk");
330 	else
331 		pc->pclk = pc->clk;
332 
333 	if (IS_ERR(pc->pclk))
334 		return dev_err_probe(&pdev->dev, PTR_ERR(pc->pclk), "Can't get APB clk\n");
335 
336 	ret = clk_prepare_enable(pc->clk);
337 	if (ret)
338 		return dev_err_probe(&pdev->dev, ret, "Can't prepare enable PWM clk\n");
339 
340 	ret = clk_prepare_enable(pc->pclk);
341 	if (ret) {
342 		dev_err_probe(&pdev->dev, ret, "Can't prepare enable APB clk\n");
343 		goto err_clk;
344 	}
345 
346 	platform_set_drvdata(pdev, pc);
347 
348 	pc->data = id->data;
349 	pc->chip.dev = &pdev->dev;
350 	pc->chip.ops = &rockchip_pwm_ops;
351 	pc->chip.npwm = 1;
352 
353 	enable_conf = pc->data->enable_conf;
354 	ctrl = readl_relaxed(pc->base + pc->data->regs.ctrl);
355 	enabled = (ctrl & enable_conf) == enable_conf;
356 
357 	ret = pwmchip_add(&pc->chip);
358 	if (ret < 0) {
359 		dev_err_probe(&pdev->dev, ret, "pwmchip_add() failed\n");
360 		goto err_pclk;
361 	}
362 
363 	/* Keep the PWM clk enabled if the PWM appears to be up and running. */
364 	if (!enabled)
365 		clk_disable(pc->clk);
366 
367 	clk_disable(pc->pclk);
368 
369 	return 0;
370 
371 err_pclk:
372 	clk_disable_unprepare(pc->pclk);
373 err_clk:
374 	clk_disable_unprepare(pc->clk);
375 
376 	return ret;
377 }
378 
rockchip_pwm_remove(struct platform_device * pdev)379 static void rockchip_pwm_remove(struct platform_device *pdev)
380 {
381 	struct rockchip_pwm_chip *pc = platform_get_drvdata(pdev);
382 
383 	pwmchip_remove(&pc->chip);
384 
385 	clk_unprepare(pc->pclk);
386 	clk_unprepare(pc->clk);
387 }
388 
389 static struct platform_driver rockchip_pwm_driver = {
390 	.driver = {
391 		.name = "rockchip-pwm",
392 		.of_match_table = rockchip_pwm_dt_ids,
393 	},
394 	.probe = rockchip_pwm_probe,
395 	.remove_new = rockchip_pwm_remove,
396 };
397 module_platform_driver(rockchip_pwm_driver);
398 
399 MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>");
400 MODULE_DESCRIPTION("Rockchip SoC PWM driver");
401 MODULE_LICENSE("GPL v2");
402