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/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Dqcom,spi-qcom-qspi.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/qcom,spi-qcom-qspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Quad Serial Peripheral Interface (QSPI)
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
12 description: The QSPI controller allows SPI protocol communication in single,
17 - $ref: /schemas/spi/spi-controller.yaml#
22 - enum:
23 - qcom,sc7180-qspi
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dzynqmp-zc1254-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2015 - 2018, Xilinx, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
18 compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp";
23 spi0 = &qspi;
28 stdout-path = "serial0:115200n8";
41 &qspi {
44 compatible = "m25p80", "spi-flash"; /* 32MB */
45 #address-cells = <1>;
[all …]
H A Dzynqmp-zc1275-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2017 - 2018, Xilinx, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
18 compatible = "xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275", "xlnx,zynqmp";
23 spi0 = &qspi;
28 stdout-path = "serial0:115200n8";
41 &qspi {
44 compatible = "m25p80", "spi-flash"; /* 32MB */
45 #address-cells = <1>;
[all …]
H A Dzynq-topic-miami.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2014-2016 Topic Embedded Products
7 /dts-v1/;
8 #include "zynq-7000.dtsi"
12 compatible = "topic,miami", "xlnx,zynq-7000";
16 spi0 = &qspi;
29 stdout-path = "serial0:115200n8";
33 &qspi {
34 u-boot,dm-pre-reloc;
36 is-dual = <0>;
[all …]
H A Dzynqmp-zc1275-revB.dts1 // SPDX-License-Identifier: GPL-2.0
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
18 compatible = "xlnx,zynqmp-zc1275-revB", "xlnx,zynqmp-zc1275", "xlnx,zynqmp";
23 spi0 = &qspi;
29 stdout-path = "serial0:115200n8";
42 &qspi {
45 compatible = "m25p80", "spi-flash"; /* 32MB */
46 #address-cells = <1>;
47 #size-cells = <1>;
[all …]
H A Dkeystone-k2g-ice.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
7 /dts-v1/;
9 #include "keystone-k2g.dtsi"
12 compatible = "ti,k2g-ice", "ti,k2g", "ti,keystone";
16 stdout-path = &uart0;
37 &qspi {
41 compatible = "s25fl256s1", "spi-flash";
43 spi-tx-bus-width = <1>;
44 spi-rx-bus-width = <4>;
[all …]
H A Dzynq-cse-qspi.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Xilinx CSE QSPI board DTS
5 * Copyright (C) 2015 - 2017 Xilinx, Inc.
7 /dts-v1/;
10 #address-cells = <1>;
11 #size-cells = <1>;
12 model = "Zynq CSE QSPI Board";
13 compatible = "xlnx,zynq-cse-qspi", "xlnx,zynq-7000";
16 spi0 = &qspi;
26 stdout-path = "serial0:115200n8";
[all …]
H A Dzynqmp-zc1232-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2017 - 2018, Xilinx, Inc.
10 /dts-v1/;
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/phy/phy.h>
18 compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", "xlnx,zynqmp";
23 spi0 = &qspi;
28 stdout-path = "serial0:115200n8";
41 &qspi {
44 compatible = "m25p80", "spi-flash"; /* 32MB FIXME */
[all …]
H A Dzynq-cc108.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2007-2018 Xilinx, Inc.
6 * (C) Copyright 2007-2013 Michal Simek
7 * (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd
11 /dts-v1/;
12 /include/ "zynq-7000.dtsi"
16 compatible = "xlnx,zynq-cc108", "xlnx,zynq-7000";
21 spi0 = &qspi;
26 stdout-path = "serial0:115200n8";
35 compatible = "usb-nop-xceiv";
[all …]
H A Dzynqmp-mini-qspi.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2015 - 2018, Xilinx, Inc.
11 /dts-v1/;
14 model = "ZynqMP MINI QSPI";
16 #address-cells = <2>;
17 #size-cells = <1>;
21 spi0 = &qspi;
25 stdout-path = "serial0:115200n8";
36 u-boot,dm-pre-reloc;
40 compatible = "simple-bus";
[all …]
H A Dkeystone-k2g-evm.dts10 /dts-v1/;
12 #include "keystone-k2g.dtsi"
15 compatible = "ti,k2g-evm","ti,keystone";
19 stdout-path = &uart0;
30 ethphy0: ethernet-phy@0 {
32 phy-mode = "rgmii-id";
42 compatible = "nop-phy";
55 compatible = "nop-phy";
65 phy-handle = <&ethphy0>;
76 #address-cells = <1>;
[all …]
H A Dzynqmp-zc1751-xm018-dc4.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm018-dc4
5 * (C) Copyright 2015 - 2018, Xilinx, Inc.
10 /dts-v1/;
13 #include "zynqmp-clk-ccf.dtsi"
16 model = "ZynqMP zc1751-xm018-dc4";
17 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
32 spi0 = &qspi;
37 stdout-path = "serial0:115200n8";
128 phy-mode = "rgmii-id";
[all …]
H A Dfsl-ls2081a-rdb.dts1 // SPDX-License-Identifier: GPL-2.0+ OR X11
3 * NXP LS2081A RDB board device tree source for QSPI-boot
10 /dts-v1/;
12 #include "fsl-ls2080a.dtsi"
16 compatible = "fsl,ls2081a-rdb", "fsl,ls2080a";
19 spi0 = &qspi;
25 bus-num = <0>;
29 #address-cells = <1>;
30 #size-cells = <1>;
31 compatible = "spi-flash";
[all …]
H A Dfsl-ls2088a-rdb-qspi.dts1 // SPDX-License-Identifier: GPL-2.0+ OR X11
3 * NXP ls2080a RDB board device tree source for QSPI-boot
10 /dts-v1/;
12 #include "fsl-ls2080a.dtsi"
16 compatible = "fsl,ls2080a-rdb", "fsl,ls2080a";
19 spi0 = &qspi;
25 bus-num = <0>;
29 #address-cells = <1>;
30 #size-cells = <1>;
31 compatible = "spi-flash";
[all …]
H A Dzynqmp-zc1751-xm015-dc1.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm015-dc1
5 * (C) Copyright 2015 - 2018, Xilinx, Inc.
10 /dts-v1/;
13 #include "zynqmp-clk-ccf.dtsi"
16 model = "ZynqMP zc1751-xm015-dc1 RevA";
17 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
27 spi0 = &qspi;
33 stdout-path = "serial0:115200n8";
76 phy-handle = <&phy0>;
[all …]
H A Dmt7629-rfb.dts5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 /dts-v1/;
13 compatible = "mediatek,mt7629-rfb", "mediatek,mt7629";
16 spi0 = &qspi;
20 stdout-path = &uart0;
21 tick-timer = &timer0;
27 mediatek,gmac-id = <1>;
28 phy-mode = "gmii";
29 phy-handle = <&phy0>;
31 phy0: ethernet-phy@0 {
[all …]
H A Dstv0991.dts1 /dts-v1/;
6 #address-cells = <1>;
7 #size-cells = <1>;
10 stdout-path = &uart0;
25 spi0 = "/spi@80203000"; /* QSPI */
28 qspi: spi@80203000 { label
29 compatible = "cdns,qspi-nor";
30 #address-cells = <1>;
31 #size-cells = <0>;
35 cdns,fifo-depth = <256>;
[all …]
H A Dzynq-picozed.dts1 // SPDX-License-Identifier: GPL-2.0+
7 /dts-v1/;
8 #include "zynq-7000.dtsi"
12 compatible = "xlnx,zynq-picozed", "xlnx,zynq-7000";
16 spi0 = &qspi;
27 u-boot,dm-pre-reloc;
31 &qspi {
32 u-boot,dm-pre-reloc;
37 u-boot,dm-pre-reloc;
H A Dfsl-ls1012a-frwy.dts1 // SPDX-License-Identifier: GPL-2.0+ OR X11
9 /dts-v1/;
10 #include "fsl-ls1012a.dtsi"
13 model = "FRWY-LS1012A Board";
16 spi0 = &qspi;
20 stdout-path = &duart0;
24 &qspi {
25 bus-num = <0>;
29 #address-cells = <1>;
30 #size-cells = <1>;
[all …]
H A Dfsl-ls1012a-2g5rdb.dts1 // SPDX-License-Identifier: GPL-2.0+
8 /dts-v1/;
9 #include "fsl-ls1012a.dtsi"
15 spi0 = &qspi;
19 stdout-path = &duart0;
23 &qspi {
24 bus-num = <0>;
28 #address-cells = <1>;
29 #size-cells = <1>;
30 compatible = "spi-flash";
[all …]
H A Dfsl-ls1088a-rdb.dts1 // SPDX-License-Identifier: GPL-2.0+ OR X11
8 /dts-v1/;
10 #include "fsl-ls1088a.dtsi"
14 compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
16 spi0 = &qspi;
20 &qspi {
21 bus-num = <0>;
25 #address-cells = <1>;
26 #size-cells = <1>;
27 compatible = "spi-flash";
[all …]
H A Dfsl-ls1046a-rdb.dts1 // SPDX-License-Identifier: GPL-2.0+ OR X11
3 * Device Tree Include file for Freescale Layerscape-1046A family SoC.
10 /dts-v1/;
11 /include/ "fsl-ls1046a.dtsi"
17 spi0 = &qspi;
22 &qspi {
23 bus-num = <0>;
27 #address-cells = <1>;
28 #size-cells = <1>;
29 compatible = "spi-flash";
[all …]
/openbmc/linux/arch/arm/boot/dts/intel/socfpga/
H A Dsocfpga_arria10_socdk_qspi.dts1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
9 &qspi {
13 #address-cells = <1>;
14 #size-cells = <1>;
15 compatible = "micron,mt25qu02g", "jedec,spi-nor";
17 spi-max-frequency = <100000000>;
19 m25p,fast-read;
20 cdns,page-size = <256>;
21 cdns,block-size = <16>;
[all …]
/openbmc/qemu/docs/system/arm/
H A Dxlnx-zynq.rst1 Xilinx Zynq board (``xilinx-zynq-a9``)
4 integrate a feature-rich dual or single-core Arm Cortex-A9 MPCore based
8 https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM/Zynq-7000-SoC-Technical-Reference-Manual
10 QEMU xilinx-zynq-a9 board supports following devices:
11 - A9 MPCORE
12 - cortex-a9
13 - GIC v1
14 - Generic timer
15 - wdt
16 - OCM 256KB
[all …]
/openbmc/linux/arch/arm64/boot/dts/xilinx/
H A Dzynqmp-zcu1275-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2017 - 2021, Xilinx, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
18 compatible = "xlnx,zynqmp-zcu1275-revA", "xlnx,zynqmp-zcu1275", "xlnx,zynqmp";
23 spi0 = &qspi;
28 stdout-path = "serial0:115200n8";
45 &qspi {
48 compatible = "m25p80", "jedec,spi-nor";
50 spi-tx-bus-width = <4>;
[all …]

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