arm/dts/zynqmp-zc1232-revA.dts

1 // SPDX-License-Identifier: GPL-2.0+
5  * (C) Copyright 2017 - 2018, Xilinx, Inc.
10 /dts-v1/;
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/phy/phy.h>
18 	compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", "xlnx,zynqmp";
23 		spi0 = &qspi;
28 		stdout-path = "serial0:115200n8";
41 &qspi {
44 		compatible = "m25p80", "spi-flash"; /* 32MB FIXME */
45 		#address-cells = <1>;
46 		#size-cells = <1>;
48 		spi-tx-bus-width = <1>;
49 		spi-rx-bus-width = <4>;
50 		spi-max-frequency = <108000000>; /* Based on DC1 spec */
51 		partition@qspi-fsbl-uboot { /* for testing purpose */
52 			label = "qspi-fsbl-uboot";
55 		partition@qspi-linux { /* for testing purpose */
56 			label = "qspi-linux";
59 		partition@qspi-device-tree { /* for testing purpose */
60 			label = "qspi-device-tree";
63 		partition@qspi-rootfs { /* for testing purpose */
64 			label = "qspi-rootfs";
73 	ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
74 	ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
75 	ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
76 	ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
77 	ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
78 	ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
79 	ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
80 	ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
81 	phy-names = "sata-phy";