1*14ed50a4SSiva Durga Prasad Paladugu// SPDX-License-Identifier: GPL-2.0+ 2*14ed50a4SSiva Durga Prasad Paladugu/* 3*14ed50a4SSiva Durga Prasad Paladugu * dts file for Xilinx ZynqMP Mini Configuration 4*14ed50a4SSiva Durga Prasad Paladugu * 5*14ed50a4SSiva Durga Prasad Paladugu * (C) Copyright 2015 - 2018, Xilinx, Inc. 6*14ed50a4SSiva Durga Prasad Paladugu * 7*14ed50a4SSiva Durga Prasad Paladugu * Siva Durga Prasad <siva.durga.paladugu@xilinx.com> 8*14ed50a4SSiva Durga Prasad Paladugu * Michal Simek <michal.simek@xilinx.com> 9*14ed50a4SSiva Durga Prasad Paladugu */ 10*14ed50a4SSiva Durga Prasad Paladugu 11*14ed50a4SSiva Durga Prasad Paladugu/dts-v1/; 12*14ed50a4SSiva Durga Prasad Paladugu 13*14ed50a4SSiva Durga Prasad Paladugu/ { 14*14ed50a4SSiva Durga Prasad Paladugu model = "ZynqMP MINI QSPI"; 15*14ed50a4SSiva Durga Prasad Paladugu compatible = "xlnx,zynqmp"; 16*14ed50a4SSiva Durga Prasad Paladugu #address-cells = <2>; 17*14ed50a4SSiva Durga Prasad Paladugu #size-cells = <1>; 18*14ed50a4SSiva Durga Prasad Paladugu 19*14ed50a4SSiva Durga Prasad Paladugu aliases { 20*14ed50a4SSiva Durga Prasad Paladugu serial0 = &dcc; 21*14ed50a4SSiva Durga Prasad Paladugu spi0 = &qspi; 22*14ed50a4SSiva Durga Prasad Paladugu }; 23*14ed50a4SSiva Durga Prasad Paladugu 24*14ed50a4SSiva Durga Prasad Paladugu chosen { 25*14ed50a4SSiva Durga Prasad Paladugu stdout-path = "serial0:115200n8"; 26*14ed50a4SSiva Durga Prasad Paladugu }; 27*14ed50a4SSiva Durga Prasad Paladugu 28*14ed50a4SSiva Durga Prasad Paladugu memory@fffc0000 { 29*14ed50a4SSiva Durga Prasad Paladugu device_type = "memory"; 30*14ed50a4SSiva Durga Prasad Paladugu reg = <0x0 0xfffc0000 0x40000>; 31*14ed50a4SSiva Durga Prasad Paladugu }; 32*14ed50a4SSiva Durga Prasad Paladugu 33*14ed50a4SSiva Durga Prasad Paladugu dcc: dcc { 34*14ed50a4SSiva Durga Prasad Paladugu compatible = "arm,dcc"; 35*14ed50a4SSiva Durga Prasad Paladugu status = "disabled"; 36*14ed50a4SSiva Durga Prasad Paladugu u-boot,dm-pre-reloc; 37*14ed50a4SSiva Durga Prasad Paladugu }; 38*14ed50a4SSiva Durga Prasad Paladugu 39*14ed50a4SSiva Durga Prasad Paladugu amba: amba { 40*14ed50a4SSiva Durga Prasad Paladugu compatible = "simple-bus"; 41*14ed50a4SSiva Durga Prasad Paladugu #address-cells = <2>; 42*14ed50a4SSiva Durga Prasad Paladugu #size-cells = <1>; 43*14ed50a4SSiva Durga Prasad Paladugu ranges; 44*14ed50a4SSiva Durga Prasad Paladugu 45*14ed50a4SSiva Durga Prasad Paladugu qspi: spi@ff0f0000 { 46*14ed50a4SSiva Durga Prasad Paladugu compatible = "xlnx,zynqmp-qspi-1.0"; 47*14ed50a4SSiva Durga Prasad Paladugu status = "disabled"; 48*14ed50a4SSiva Durga Prasad Paladugu clock-names = "ref_clk", "pclk"; 49*14ed50a4SSiva Durga Prasad Paladugu clocks = <&misc_clk &misc_clk>; 50*14ed50a4SSiva Durga Prasad Paladugu num-cs = <1>; 51*14ed50a4SSiva Durga Prasad Paladugu reg = <0x0 0xff0f0000 0x1000 0x0 0xc0000000 0x8000000>; 52*14ed50a4SSiva Durga Prasad Paladugu #address-cells = <1>; 53*14ed50a4SSiva Durga Prasad Paladugu #size-cells = <0>; 54*14ed50a4SSiva Durga Prasad Paladugu }; 55*14ed50a4SSiva Durga Prasad Paladugu 56*14ed50a4SSiva Durga Prasad Paladugu misc_clk: misc_clk { 57*14ed50a4SSiva Durga Prasad Paladugu compatible = "fixed-clock"; 58*14ed50a4SSiva Durga Prasad Paladugu #clock-cells = <0>; 59*14ed50a4SSiva Durga Prasad Paladugu clock-frequency = <125000000>; 60*14ed50a4SSiva Durga Prasad Paladugu }; 61*14ed50a4SSiva Durga Prasad Paladugu }; 62*14ed50a4SSiva Durga Prasad Paladugu}; 63*14ed50a4SSiva Durga Prasad Paladugu 64*14ed50a4SSiva Durga Prasad Paladugu&qspi { 65*14ed50a4SSiva Durga Prasad Paladugu status = "okay"; 66*14ed50a4SSiva Durga Prasad Paladugu flash@0 { 67*14ed50a4SSiva Durga Prasad Paladugu compatible = "n25q512a11"; 68*14ed50a4SSiva Durga Prasad Paladugu #address-cells = <1>; 69*14ed50a4SSiva Durga Prasad Paladugu #size-cells = <1>; 70*14ed50a4SSiva Durga Prasad Paladugu reg = <0x0>; 71*14ed50a4SSiva Durga Prasad Paladugu spi-tx-bus-width = <1>; 72*14ed50a4SSiva Durga Prasad Paladugu spi-rx-bus-width = <4>; 73*14ed50a4SSiva Durga Prasad Paladugu spi-max-frequency = <10000000>; 74*14ed50a4SSiva Durga Prasad Paladugu }; 75*14ed50a4SSiva Durga Prasad Paladugu}; 76*14ed50a4SSiva Durga Prasad Paladugu 77*14ed50a4SSiva Durga Prasad Paladugu&dcc { 78*14ed50a4SSiva Durga Prasad Paladugu status = "okay"; 79*14ed50a4SSiva Durga Prasad Paladugu}; 80