1d2423aa0SAkash Asthana# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2d2423aa0SAkash Asthana%YAML 1.2 3d2423aa0SAkash Asthana--- 499a7fa0eSKrzysztof Kozlowski$id: http://devicetree.org/schemas/spi/qcom,spi-qcom-qspi.yaml# 599a7fa0eSKrzysztof Kozlowski$schema: http://devicetree.org/meta-schemas/core.yaml# 6d2423aa0SAkash Asthana 7d2423aa0SAkash Asthanatitle: Qualcomm Quad Serial Peripheral Interface (QSPI) 8d2423aa0SAkash Asthana 9d2423aa0SAkash Asthanamaintainers: 1092298ea3SKrzysztof Kozlowski - Bjorn Andersson <bjorn.andersson@linaro.org> 11d2423aa0SAkash Asthana 129f60a65bSRob Herringdescription: The QSPI controller allows SPI protocol communication in single, 139f60a65bSRob Herring dual, or quad wire transmission modes for read/write access to slaves such 149f60a65bSRob Herring as NOR flash. 15d2423aa0SAkash Asthana 16d2423aa0SAkash AsthanaallOf: 1722a41e9aSRob Herring - $ref: /schemas/spi/spi-controller.yaml# 18d2423aa0SAkash Asthana 19d2423aa0SAkash Asthanaproperties: 20d2423aa0SAkash Asthana compatible: 21d2423aa0SAkash Asthana items: 22eca17cbaSRajesh Patil - enum: 23acde4081SRajesh Patil - qcom,sc7180-qspi 24eca17cbaSRajesh Patil - qcom,sc7280-qspi 25eca17cbaSRajesh Patil - qcom,sdm845-qspi 26eca17cbaSRajesh Patil 27d2423aa0SAkash Asthana - const: qcom,qspi-v1 28d2423aa0SAkash Asthana 29d2423aa0SAkash Asthana reg: 30d2423aa0SAkash Asthana maxItems: 1 31d2423aa0SAkash Asthana 32*64c05eb3SVijaya Krishna Nivarthi iommus: 33*64c05eb3SVijaya Krishna Nivarthi maxItems: 1 34*64c05eb3SVijaya Krishna Nivarthi 35d2423aa0SAkash Asthana interrupts: 36d2423aa0SAkash Asthana maxItems: 1 37d2423aa0SAkash Asthana 38d2423aa0SAkash Asthana clock-names: 39d2423aa0SAkash Asthana items: 40d2423aa0SAkash Asthana - const: iface 41d2423aa0SAkash Asthana - const: core 42d2423aa0SAkash Asthana 43d2423aa0SAkash Asthana clocks: 44d2423aa0SAkash Asthana items: 45d2423aa0SAkash Asthana - description: AHB clock 46d2423aa0SAkash Asthana - description: QSPI core clock 47d2423aa0SAkash Asthana 488f9c2915SAkash Asthana interconnects: 498f9c2915SAkash Asthana minItems: 1 508f9c2915SAkash Asthana maxItems: 2 518f9c2915SAkash Asthana 528f9c2915SAkash Asthana interconnect-names: 53e23d86c4SKuldeep Singh minItems: 1 548f9c2915SAkash Asthana items: 558f9c2915SAkash Asthana - const: qspi-config 568f9c2915SAkash Asthana - const: qspi-memory 578f9c2915SAkash Asthana 587234d746SKrzysztof Kozlowski operating-points-v2: true 597234d746SKrzysztof Kozlowski 607234d746SKrzysztof Kozlowski power-domains: 617234d746SKrzysztof Kozlowski maxItems: 1 627234d746SKrzysztof Kozlowski 63d2423aa0SAkash Asthanarequired: 64d2423aa0SAkash Asthana - compatible 65d2423aa0SAkash Asthana - reg 66d2423aa0SAkash Asthana - interrupts 67d2423aa0SAkash Asthana - clock-names 68d2423aa0SAkash Asthana - clocks 69d2423aa0SAkash Asthana 706fdc6e23SRob HerringunevaluatedProperties: false 716fdc6e23SRob Herring 72d2423aa0SAkash Asthanaexamples: 73d2423aa0SAkash Asthana - | 74d2423aa0SAkash Asthana #include <dt-bindings/clock/qcom,gcc-sdm845.h> 75d2423aa0SAkash Asthana #include <dt-bindings/interrupt-controller/arm-gic.h> 76d2423aa0SAkash Asthana 77f88d59fcSRob Herring soc: soc { 78d2423aa0SAkash Asthana #address-cells = <2>; 79d2423aa0SAkash Asthana #size-cells = <2>; 80d2423aa0SAkash Asthana 81d2423aa0SAkash Asthana qspi: spi@88df000 { 82d2423aa0SAkash Asthana compatible = "qcom,sdm845-qspi", "qcom,qspi-v1"; 83d2423aa0SAkash Asthana reg = <0 0x88df000 0 0x600>; 84d2423aa0SAkash Asthana #address-cells = <1>; 85d2423aa0SAkash Asthana #size-cells = <0>; 86d2423aa0SAkash Asthana interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 87d2423aa0SAkash Asthana clock-names = "iface", "core"; 88d2423aa0SAkash Asthana clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 89d2423aa0SAkash Asthana <&gcc GCC_QSPI_CORE_CLK>; 90d2423aa0SAkash Asthana 91d2423aa0SAkash Asthana flash@0 { 92d2423aa0SAkash Asthana compatible = "jedec,spi-nor"; 93d2423aa0SAkash Asthana reg = <0>; 94d2423aa0SAkash Asthana spi-max-frequency = <25000000>; 95d2423aa0SAkash Asthana spi-tx-bus-width = <2>; 96d2423aa0SAkash Asthana spi-rx-bus-width = <2>; 97d2423aa0SAkash Asthana }; 98d2423aa0SAkash Asthana }; 99d2423aa0SAkash Asthana }; 100d2423aa0SAkash Asthana... 101