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/openbmc/qemu/hw/acpi/
H A Dich9.c23 * Contributions after 2012-01-13 are licensed under the terms of the
41 #include "hw/mem/pc-dimm.h"
46 ICH9LPCPMRegs *pm = container_of(regs, ICH9LPCPMRegs, acpi_regs); in ich9_pm_update_sci_fn() local
47 acpi_update_sci(&pm->acpi_regs, pm->irq); in ich9_pm_update_sci_fn()
52 ICH9LPCPMRegs *pm = opaque; in ich9_gpe_readb() local
53 return acpi_gpe_ioport_readb(&pm->acpi_regs, addr); in ich9_gpe_readb()
59 ICH9LPCPMRegs *pm = opaque; in ich9_gpe_writeb() local
60 acpi_gpe_ioport_writeb(&pm->acpi_regs, addr, val); in ich9_gpe_writeb()
61 acpi_update_sci(&pm->acpi_regs, pm->irq); in ich9_gpe_writeb()
76 ICH9LPCPMRegs *pm = opaque; in ich9_smi_readl() local
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H A Dpiix4.c18 * Contributions after 2012-01-13 are licensed under the terms of the
27 #include "hw/qdev-properties.h"
39 #include "hw/mem/pc-dimm.h"
58 PCIBus *bus, PIIX4PMState *s);
66 acpi_update_sci(&s->ar, s->irq); in pm_tmr_timer()
75 acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE); in apm_ctrl_changed()
80 if (d->config[0x5b] & (1 << 1)) { in apm_ctrl_changed()
81 if (s->smi_irq) { in apm_ctrl_changed()
82 qemu_irq_raise(s->smi_irq); in apm_ctrl_changed()
91 s->io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x40)); in pm_io_space_update()
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/openbmc/qemu/hw/ppc/
H A Dpegasos2.c4 * Copyright (c) 2018-2021 BALATON Zoltan
17 #include "hw/or-irq.h"
18 #include "hw/pci-host/mv64361.h"
22 #include "hw/qdev-properties.h"
28 #include "hw/fw-path-provider.h"
31 #include "qemu/error-report.h"
34 #include "system/address-spaces.h"
35 #include "qom/qom-qobject.h"
55 #define H_PRIVILEGE -3 /* Caller not privileged */
56 #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */
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/openbmc/u-boot/drivers/spi/
H A Dfsl_espi.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright 2010-2011 Freescale Semiconductor, Inc.
19 unsigned int pm; member
65 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, in spi_setup_slave() argument
72 unsigned char pm = 0; in spi_setup_slave() local
74 if (!spi_cs_is_valid(bus, cs)) in spi_setup_slave()
77 fsl = spi_alloc_slave(struct fsl_spi_slave, bus, cs); in spi_setup_slave()
81 fsl->espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR); in spi_setup_slave()
82 fsl->mode = mode; in spi_setup_slave()
83 fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN; in spi_setup_slave()
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/openbmc/qemu/hw/i386/
H A Dacpi-build.c3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
26 #include "acpi-build.h"
27 #include "acpi-common.h"
29 #include "qemu/error-report.h"
35 #include "hw/acpi/acpi-defs.h"
39 #include "hw/acpi/bios-linker-loader.h"
52 #include "hw/mem/memory-device.h"
56 #include "hw/hyperv/vmbus-bridge.h"
64 #include "hw/pci-host/i440fx.h"
65 #include "hw/pci-host/q35.h"
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/openbmc/u-boot/arch/m68k/cpu/mcf5445x/
H A Dcpu_init.c1 // SPDX-License-Identifier: GPL-2.0+
4 * (C) Copyright 2000-2003
7 * (C) Copyright 2004-2007, 2012 Freescale Semiconductor, Inc.
8 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
31 out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE); in init_fbcs()
32 out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); in init_fbcs()
33 out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); in init_fbcs()
39 out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE); in init_fbcs()
40 out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); in init_fbcs()
41 out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK); in init_fbcs()
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/openbmc/qemu/hw/pci/
H A Dtrace-events4 …nst char *dev, uint32_t bus, uint32_t slot, uint32_t func, uint8_t old, uint8_t new) "%s %02x:%02x…
5 …n(const char *dev, uint32_t bus, uint32_t slot, uint32_t func, uint8_t old, uint8_t new) "%s %02x:…
6 pci_update_mappings_del(const char *dev, uint32_t bus, uint32_t slot, uint32_t func, int bar, uint6…
7 pci_update_mappings_add(const char *dev, uint32_t bus, uint32_t slot, uint32_t func, int bar, uint6…
8 … dev_irq, const char *dev_path, int parent_irq, const char *parent_path) "IRQ %d @%s -> IRQ %d @%s"
15 …_read(const char *dev, uint32_t bus, uint32_t slot, uint32_t func, unsigned offs, unsigned val) "%…
16 …write(const char *dev, uint32_t bus, uint32_t slot, uint32_t func, unsigned offs, unsigned val) "%…
27 …char *old_power, const char *new_power) "%s > %s: pds: %s, pic: %s->%s, aic: %s->%s, power: %s->%s"
30 …onst char *old_state, const char *new_state) "%s[%d] > %s: pic: %s->%s, aic: %s->%s, state: %s->%s"
/openbmc/u-boot/arch/x86/cpu/qemu/
H A Dqemu.c1 // SPDX-License-Identifier: GPL-2.0+
41 /* the endianness of data register is string-preserving */ in qemu_x86_fwcfg_read_entry_pio()
42 while (size--) in qemu_x86_fwcfg_read_entry_pio()
51 while (be32_to_cpu(dma->control) & ~FW_CFG_DMA_ERROR) in qemu_x86_fwcfg_read_entry_dma()
66 /* Set the PM I/O base */ in enable_pm_piix()
69 /* Enable access to the PM I/O space */ in enable_pm_piix()
74 /* PM I/O Space Enable (PMIOSE) */ in enable_pm_piix()
82 /* Set the PM I/O base */ in enable_pm_ich9()
167 int mp_determine_pci_dstirq(int bus, int dev, int func, int pirq) in mp_determine_pci_dstirq() argument
173 * Not like most x86 platforms, the PIRQ[A-D] on PIIX3 are not in mp_determine_pci_dstirq()
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/openbmc/qemu/hw/isa/
H A Dpiix.c33 #include "hw/qdev-properties.h"
43 qemu_set_irq(s->isa_irqs_in[pic_irq], in piix_set_irq_pic()
44 !!(s->pic_levels & in piix_set_irq_pic()
45 (((1ULL << PIIX_NUM_PIRQS) - 1) << in piix_set_irq_pic()
54 pic_irq = s->dev.config[PIIX_PIRQCA + pirq]; in piix_set_pci_irq_level_internal()
60 s->pic_levels &= ~mask; in piix_set_pci_irq_level_internal()
61 s->pic_levels |= mask * !!level; in piix_set_pci_irq_level_internal()
68 pic_irq = s->dev.config[PIIX_PIRQCA + pirq]; in piix_set_pci_irq_level()
87 qemu_set_irq(s->cpu_intr, level); in piix_request_i8259_irq()
93 int irq = pci_dev->config[PIIX_PIRQCA + pin]; in piix_route_intx_pin_to_irq()
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H A Dlpc_ich9.c48 #include "hw/qdev-properties.h"
90 /* D{25 - 31}IR, but D30IR is read only to 0. */ in ich9_cc_update()
95 ich9_cc_update_ir(lpc->irr[slot], in ich9_cc_update()
96 pci_get_word(lpc->chip_config + *offset)); in ich9_cc_update()
102 * the bridge are connected to pirq lines. Our choice is PIRQ[E-H]. in ich9_cc_update()
103 * INT[A-D] are connected to PIRQ[E-H] in ich9_cc_update()
106 lpc->irr[30][pci_intx] = pci_intx + 4; in ich9_cc_update()
121 * int[A-D] -> pirq[E-F] in ich9_cc_init()
122 * avoid pirq A-D because they are used for pci express port in ich9_cc_init()
126 lpc->irr[slot][intx] = (slot + intx) % 4 + 4; in ich9_cc_init()
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H A Dvt82c686.c4 * Copyright (c) 2008 yajin (yajin@vm-kernel.org)
9 * Contributions after 2012-01-13 are licensed under the terms of the
13 * Copyright (c) 2018-2020 BALATON Zoltan
19 #include "hw/char/parallel-isa.h"
20 #include "hw/char/serial-isa.h"
22 #include "hw/qdev-properties.h"
29 #include "hw/usb/hcd-uhci.h"
43 #define TYPE_VIA_PM "via-pm"
56 uint32_t pmbase = pci_get_long(s->dev.config + 0x48) & 0xff80UL; in pm_io_space_update()
59 memory_region_set_address(&s->io, pmbase); in pm_io_space_update()
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/openbmc/openbmc/meta-openembedded/meta-oe/recipes-support/pxaregs/pxaregs-1.14/
H A Dpxaregs.c2 * pxaregs - tool to display and modify PXA250's registers at runtime
4 * (c) Copyright 2002 by M&N Logistik-Lösungen Online GmbH
9 * Please send patches to h.schurig, working at mn-logistik.de
10 * - added fix from Bernhard Nemec
11 * - i2c registers from Stefan Eletzhofer
25 #include <linux/i2c-dev.h>
29 static int fd = -1;
44 { "IBMR", 0x40301680, 0, 0xffffffff, 'x', "I2C Bus Monitor Register" },
62 { "ICR_BEIE", 0x40301690, 10, 1, 'x', " enable bus error ints " },
73 { "ISR_IBB", 0x40301698, 3, 1, 'x', " bus busy " },
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/openbmc/u-boot/arch/x86/include/asm/arch-qemu/
H A Dqemu.h1 /* SPDX-License-Identifier: GPL-2.0+ */
15 /* X-Bus Chip Select Register */
35 /* PM registers */
/openbmc/u-boot/drivers/power/
H A Dtwl4030.c1 // SPDX-License-Identifier: GPL-2.0+
7 * git://git.omapzoom.com/repo/u-boot.git
9 * Copyright (C) 2007-2009 Texas Instruments, Inc.
13 * (C) Copyright 2004-2008
21 * Richard Woodruff <r-woodruff2 at ti.com>
54 /* PM master unlock (CFG and TST keys) */ in twl4030_power_off()
92 /* PM master lock */ in twl4030_power_off()
162 mdelay(100); /* ramp-up delay from Linux code */ in twl4030_power_mmc_init()
170 mdelay(100); /* ramp-up delay from Linux code */ in twl4030_power_mmc_init()
191 pr_err("unable to get I2C bus. ret %d\n", ret); in twl4030_i2c_write_u8()
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/openbmc/openpower-occ-control/
H A Docc_manager.hpp14 #include <sdbusplus/bus.hpp>
24 namespace sdbusRule = sdbusplus::bus::match::rules;
69 /** @brief Adds OCC pass-through and status objects on the bus
72 * @param[in] event - Unique ptr reference to sd_event
117 * @param[in] instance - the OCC instance id
123 * @param[out] ambientValid - true if ambientTemp is valid
124 * @param[out] ambient - ambient temperature in degrees C
125 * @param[out] altitude - altitude in meters
135 * @param[in] id - Id of the OCC.
141 * @param[in] id - Id of the OCC.
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H A Docc_manager.cpp10 #include <phosphor-logging/elog-errors.hpp>
11 #include <phosphor-logging/lg2.hpp>
31 const auto HOST_ON_FILE = "/run/openbmc/host@0-on";
77 // - create the PowerMode object to control OCC modes
78 // - create statusObjects for each OCC device found
79 // - waits for OCC Active sensors PDRs to become available
80 // - restart discoverTimer if all data is not available yet
110 discoverTimer->restartOnce(10s); in findAndCreateObjects()
132 obj->updateProcAssociation(); in findAndCreateObjects()
158 discoverTimer->restartOnce(30s); in findAndCreateObjects()
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/openbmc/qemu/include/standard-headers/linux/
H A Dpci_regs.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
5 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
11 * PCI Local Bus Specification
25 * Conventional PCI and PCI-X Mode 1 devices have 256 bytes of
26 * configuration space. PCI-X Mode 2 and PCIe devices have 4096 bytes of
43 #define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
50 #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
57 #define PCI_STATUS_66MHZ 0x20 /* Support 66 MHz PCI 2.1 bus */
59 #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
83 #define PCI_HEADER_TYPE_MFD 0x80 /* Multi-Function Device (possible) */
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/openbmc/u-boot/include/configs/
H A Dlx2160ardb.h1 /* SPDX-License-Identifier: GPL-2.0+ */
43 /* PM Bus commands code for LTC3882*/
H A Dlx2160aqds.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2018-2019 NXP
60 /* PM Bus commands code for LTC3882*/
87 #define CONFIG_ETHPRIME "DPMAC17@rgmii-id"
/openbmc/u-boot/arch/x86/include/asm/
H A Dspeedstep.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2007-2009 coresystems GmbH
16 * the \_PR_.CPU0 PM base address.
66 /* Looking at core2's spec, the highest normal bus ratio for an eist enabled
72 /* Table of p-states for EMTTM and ACPI by decreasing performance. */
/openbmc/u-boot/board/freescale/m5249evb/
H A Dm5249evb.c1 // SPDX-License-Identifier: GPL-2.0+
39 * RC = ([(RefreshTime/#rows) / (1/BusClk)] / 16) - 1 in dram_init()
57 * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=22 (562 bus clock cycles) in dram_init()
64 * PM=1 (continuous page mode) in dram_init()
67 /* RE=0 (keep auto-refresh disabled while setting up registers) */ in dram_init()
86 gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; in dram_init()
/openbmc/u-boot/arch/arm/dts/
H A Dam33xx.dtsi4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/pinctrl/am33xx.h>
13 #include <dt-bindings/clock/am3.h>
17 interrupt-parent = <&intc>;
18 #address-cells = <1>;
19 #size-cells = <1>;
32 d-can0 = &dcan0;
33 d-can1 = &dcan1;
45 #address-cells = <1>;
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/openbmc/u-boot/include/
H A DSA-1100.h2 * FILE SA-1100.h
8 * System StrongARM SA-1100
11 * SA-1100 microprocessor (Advanced RISC Machine (ARM)
13 * StrongARM SA-1100 data sheet version 2.2.
15 * Language-specific definitions are selected by the
33 #include <asm/arch-sa1100/bitfield.h>
181 * Universal Serial Bus (USB) Device Controller (UDC) control registers
184 * Ser0UDCCR Serial port 0 Universal Serial Bus (USB) Device
186 * Ser0UDCAR Serial port 0 Universal Serial Bus (USB) Device
188 * Ser0UDCOMP Serial port 0 Universal Serial Bus (USB) Device
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/openbmc/qemu/hw/ide/
H A Dvia.c36 #include "ide-internal.h"
46 return ((uint64_t)1 << (size * 8)) - 1; in bmdma_read()
51 val = bm->cmd; in bmdma_read()
54 val = bm->status; in bmdma_read()
95 memory_region_init(&d->bmdma_bar, OBJECT(d), "via-bmdma-container", 16); in bmdma_setup_bar()
96 for (i = 0; i < ARRAY_SIZE(d->bmdma); i++) { in bmdma_setup_bar()
97 BMDMAState *bm = &d->bmdma[i]; in bmdma_setup_bar()
99 memory_region_init_io(&bm->extra_io, OBJECT(d), &via_bmdma_ops, bm, in bmdma_setup_bar()
100 "via-bmdma", 4); in bmdma_setup_bar()
101 memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io); in bmdma_setup_bar()
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/openbmc/u-boot/drivers/usb/eth/
H A Dlan7x.c1 // SPDX-License-Identifier: GPL-2.0+
35 return -EIO; in lan7x_write_reg()
53 return -EIO; in lan7x_read_reg()
74 return -ETIMEDOUT; in lan7x_mdio_read()
84 return -ETIMEDOUT; in lan7x_mdio_read()
116 static int lan7x_phylib_mdio_read(struct mii_dev *bus, in lan7x_phylib_mdio_read() argument
119 struct usb_device *udev = dev_get_parent_priv(bus->priv); in lan7x_phylib_mdio_read()
124 static int lan7x_phylib_mdio_write(struct mii_dev *bus, in lan7x_phylib_mdio_write() argument
127 struct usb_device *udev = dev_get_parent_priv(bus->priv); in lan7x_phylib_mdio_write()
187 priv->mdiobus = mdio_alloc(); in lan7x_phylib_register()
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