1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0 */ 218739e2cSSimon Glass /* 318739e2cSSimon Glass * From Coreboot file of same name 418739e2cSSimon Glass * 518739e2cSSimon Glass * Copyright (C) 2007-2009 coresystems GmbH 618739e2cSSimon Glass * 2012 secunet Security Networks AG 718739e2cSSimon Glass */ 818739e2cSSimon Glass 918739e2cSSimon Glass #ifndef _ASM_SPEEDSTEP_H 1018739e2cSSimon Glass #define _ASM_SPEEDSTEP_H 1118739e2cSSimon Glass 1218739e2cSSimon Glass /* Magic value used to locate speedstep configuration in the device tree */ 1318739e2cSSimon Glass #define SPEEDSTEP_APIC_MAGIC 0xACAC 1418739e2cSSimon Glass 1518739e2cSSimon Glass /* MWAIT coordination I/O base address. This must match 1618739e2cSSimon Glass * the \_PR_.CPU0 PM base address. 1718739e2cSSimon Glass */ 1818739e2cSSimon Glass #define PMB0_BASE 0x510 1918739e2cSSimon Glass 2018739e2cSSimon Glass /* PMB1: I/O port that triggers SMI once cores are in the same state. 2118739e2cSSimon Glass * See CSM Trigger, at PMG_CST_CONFIG_CONTROL[6:4] 2218739e2cSSimon Glass */ 2318739e2cSSimon Glass #define PMB1_BASE 0x800 2418739e2cSSimon Glass 2518739e2cSSimon Glass struct sst_state { 2618739e2cSSimon Glass uint8_t dynfsb:1; /* whether this is SLFM */ 2718739e2cSSimon Glass uint8_t nonint:1; /* add .5 to ratio */ 2818739e2cSSimon Glass uint8_t ratio:6; 2918739e2cSSimon Glass uint8_t vid; 3018739e2cSSimon Glass uint8_t is_turbo; 3118739e2cSSimon Glass uint8_t is_slfm; 3218739e2cSSimon Glass uint32_t power; 3318739e2cSSimon Glass }; 3418739e2cSSimon Glass #define SPEEDSTEP_RATIO_SHIFT 8 3518739e2cSSimon Glass #define SPEEDSTEP_RATIO_DYNFSB_SHIFT (7 + SPEEDSTEP_RATIO_SHIFT) 3618739e2cSSimon Glass #define SPEEDSTEP_RATIO_DYNFSB (1 << SPEEDSTEP_RATIO_DYNFSB_SHIFT) 3718739e2cSSimon Glass #define SPEEDSTEP_RATIO_NONINT_SHIFT (6 + SPEEDSTEP_RATIO_SHIFT) 3818739e2cSSimon Glass #define SPEEDSTEP_RATIO_NONINT (1 << SPEEDSTEP_RATIO_NONINT_SHIFT) 3918739e2cSSimon Glass #define SPEEDSTEP_RATIO_VALUE_MASK (0x1f << SPEEDSTEP_RATIO_SHIFT) 4018739e2cSSimon Glass #define SPEEDSTEP_VID_MASK 0x3f 4118739e2cSSimon Glass #define SPEEDSTEP_STATE_FROM_MSR(val, mask) ((struct sst_state){ \ 4218739e2cSSimon Glass 0, /* dynfsb won't be read. */ \ 4318739e2cSSimon Glass ((val & mask) & SPEEDSTEP_RATIO_NONINT) ? 1 : 0, \ 4418739e2cSSimon Glass (((val & mask) & SPEEDSTEP_RATIO_VALUE_MASK) \ 4518739e2cSSimon Glass >> SPEEDSTEP_RATIO_SHIFT), \ 4618739e2cSSimon Glass (val & mask) & SPEEDSTEP_VID_MASK, \ 4718739e2cSSimon Glass 0, /* not turbo by default */ \ 4818739e2cSSimon Glass 0, /* not slfm by default */ \ 4918739e2cSSimon Glass 0 /* power is hardcoded in software. */ \ 5018739e2cSSimon Glass }) 5118739e2cSSimon Glass #define SPEEDSTEP_ENCODE_STATE(state) ( \ 5218739e2cSSimon Glass ((uint16_t)(state).dynfsb << SPEEDSTEP_RATIO_DYNFSB_SHIFT) | \ 5318739e2cSSimon Glass ((uint16_t)(state).nonint << SPEEDSTEP_RATIO_NONINT_SHIFT) | \ 5418739e2cSSimon Glass ((uint16_t)(state).ratio << SPEEDSTEP_RATIO_SHIFT) | \ 5518739e2cSSimon Glass ((uint16_t)(state).vid & SPEEDSTEP_VID_MASK)) 5618739e2cSSimon Glass #define SPEEDSTEP_DOUBLE_RATIO(state) ( \ 5718739e2cSSimon Glass ((uint8_t)(state).ratio * 2) + (state).nonint) 5818739e2cSSimon Glass 5918739e2cSSimon Glass struct sst_params { 6018739e2cSSimon Glass struct sst_state slfm; 6118739e2cSSimon Glass struct sst_state min; 6218739e2cSSimon Glass struct sst_state max; 6318739e2cSSimon Glass struct sst_state turbo; 6418739e2cSSimon Glass }; 6518739e2cSSimon Glass 6618739e2cSSimon Glass /* Looking at core2's spec, the highest normal bus ratio for an eist enabled 6718739e2cSSimon Glass processor is 14, the lowest is always 6. This makes 5 states with the 6818739e2cSSimon Glass minimal step width of 2. With turbo mode and super LFM we have at most 7. */ 6918739e2cSSimon Glass #define SPEEDSTEP_MAX_NORMAL_STATES 5 7018739e2cSSimon Glass #define SPEEDSTEP_MAX_STATES (SPEEDSTEP_MAX_NORMAL_STATES + 2) 7118739e2cSSimon Glass struct sst_table { 7218739e2cSSimon Glass /* Table of p-states for EMTTM and ACPI by decreasing performance. */ 7318739e2cSSimon Glass struct sst_state states[SPEEDSTEP_MAX_STATES]; 7418739e2cSSimon Glass int num_states; 7518739e2cSSimon Glass }; 7618739e2cSSimon Glass 7718739e2cSSimon Glass void speedstep_gen_pstates(struct sst_table *); 7818739e2cSSimon Glass 7918739e2cSSimon Glass #define SPEEDSTEP_MAX_POWER_YONAH 31000 8018739e2cSSimon Glass #define SPEEDSTEP_MIN_POWER_YONAH 13100 8118739e2cSSimon Glass #define SPEEDSTEP_MAX_POWER_MEROM 35000 8218739e2cSSimon Glass #define SPEEDSTEP_MIN_POWER_MEROM 25000 8318739e2cSSimon Glass #define SPEEDSTEP_SLFM_POWER_MEROM 12000 8418739e2cSSimon Glass #define SPEEDSTEP_MAX_POWER_PENRYN 35000 8518739e2cSSimon Glass #define SPEEDSTEP_MIN_POWER_PENRYN 15000 8618739e2cSSimon Glass #define SPEEDSTEP_SLFM_POWER_PENRYN 12000 8718739e2cSSimon Glass 8818739e2cSSimon Glass #endif 89