1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2a65b25d1SBin Meng /* 3a65b25d1SBin Meng * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> 4a65b25d1SBin Meng */ 5a65b25d1SBin Meng 6a65b25d1SBin Meng #ifndef _ARCH_QEMU_H_ 7a65b25d1SBin Meng #define _ARCH_QEMU_H_ 8a65b25d1SBin Meng 9cc7debc7SBin Meng /* Programmable Attribute Map (PAM) Registers */ 10cc7debc7SBin Meng #define I440FX_PAM 0x59 11cc7debc7SBin Meng #define Q35_PAM 0x90 12cc7debc7SBin Meng #define PAM_NUM 7 13cc7debc7SBin Meng #define PAM_RW 0x33 14cc7debc7SBin Meng 15e7cd070dSBin Meng /* X-Bus Chip Select Register */ 16e7cd070dSBin Meng #define XBCS 0x4e 17e7cd070dSBin Meng #define APIC_EN (1 << 8) 18e7cd070dSBin Meng 190fcb7acfSBin Meng /* IDE Timing Register */ 200fcb7acfSBin Meng #define IDE0_TIM 0x40 210fcb7acfSBin Meng #define IDE1_TIM 0x42 22e7cd070dSBin Meng #define IDE_DECODE_EN (1 << 15) 230fcb7acfSBin Meng 249830d2ebSBin Meng /* PCIe ECAM Base Address Register */ 259830d2ebSBin Meng #define PCIEX_BAR 0x60 269830d2ebSBin Meng #define BAR_EN (1 << 0) 279830d2ebSBin Meng 28a65b25d1SBin Meng /* I/O Ports */ 29a65b25d1SBin Meng #define CMOS_ADDR_PORT 0x70 30a65b25d1SBin Meng #define CMOS_DATA_PORT 0x71 31a65b25d1SBin Meng 32a65b25d1SBin Meng #define LOW_RAM_ADDR 0x34 33a65b25d1SBin Meng #define HIGH_RAM_ADDR 0x35 34a65b25d1SBin Meng 35a3b15a05SMiao Yan /* PM registers */ 36a3b15a05SMiao Yan #define PMBA 0x40 37a3b15a05SMiao Yan #define PMREGMISC 0x80 38a3b15a05SMiao Yan #define PMIOSE (1 << 0) 39a3b15a05SMiao Yan 40a65b25d1SBin Meng #endif /* _ARCH_QEMU_H_ */ 41