1*3b58acd4Swdenk /* 2*3b58acd4Swdenk * FILE SA-1100.h 3*3b58acd4Swdenk * 4*3b58acd4Swdenk * Version 1.2 5*3b58acd4Swdenk * Author Copyright (c) Marc A. Viredaz, 1998 6*3b58acd4Swdenk * DEC Western Research Laboratory, Palo Alto, CA 7*3b58acd4Swdenk * Date January 1998 (April 1997) 8*3b58acd4Swdenk * System StrongARM SA-1100 9*3b58acd4Swdenk * Language C or ARM Assembly 10*3b58acd4Swdenk * Purpose Definition of constants related to the StrongARM 11*3b58acd4Swdenk * SA-1100 microprocessor (Advanced RISC Machine (ARM) 12*3b58acd4Swdenk * architecture version 4). This file is based on the 13*3b58acd4Swdenk * StrongARM SA-1100 data sheet version 2.2. 14*3b58acd4Swdenk * 15*3b58acd4Swdenk * Language-specific definitions are selected by the 16*3b58acd4Swdenk * macro "LANGUAGE", which should be defined as either 17*3b58acd4Swdenk * "C" (default) or "Assembly". 18*3b58acd4Swdenk */ 19*3b58acd4Swdenk 20*3b58acd4Swdenk 21*3b58acd4Swdenk #ifndef LANGUAGE 22*3b58acd4Swdenk # ifdef __ASSEMBLY__ 23*3b58acd4Swdenk # define LANGUAGE Assembly 24*3b58acd4Swdenk # else 25*3b58acd4Swdenk # define LANGUAGE C 26*3b58acd4Swdenk # endif 27*3b58acd4Swdenk #endif 28*3b58acd4Swdenk 29*3b58acd4Swdenk #ifndef io_p2v 30*3b58acd4Swdenk #define io_p2v(PhAdd) (PhAdd) 31*3b58acd4Swdenk #endif 32*3b58acd4Swdenk 33*3b58acd4Swdenk #include <asm/arch-sa1100/bitfield.h> 34*3b58acd4Swdenk 35*3b58acd4Swdenk #define C 0 36*3b58acd4Swdenk #define Assembly 1 37*3b58acd4Swdenk 38*3b58acd4Swdenk 39*3b58acd4Swdenk #if LANGUAGE == C 40*3b58acd4Swdenk typedef unsigned short Word16 ; 41*3b58acd4Swdenk typedef unsigned int Word32 ; 42*3b58acd4Swdenk typedef Word32 Word ; 43*3b58acd4Swdenk typedef Word Quad [4] ; 44*3b58acd4Swdenk typedef void *Address ; 45*3b58acd4Swdenk typedef void (*ExcpHndlr) (void) ; 46*3b58acd4Swdenk #endif /* LANGUAGE == C */ 47*3b58acd4Swdenk 48*3b58acd4Swdenk 49*3b58acd4Swdenk /* 50*3b58acd4Swdenk * Memory 51*3b58acd4Swdenk */ 52*3b58acd4Swdenk 53*3b58acd4Swdenk #define MemBnkSp 0x08000000 /* Memory Bank Space [byte] */ 54*3b58acd4Swdenk 55*3b58acd4Swdenk #define StMemBnkSp MemBnkSp /* Static Memory Bank Space [byte] */ 56*3b58acd4Swdenk #define StMemBnk0Sp StMemBnkSp /* Static Memory Bank 0 Space */ 57*3b58acd4Swdenk /* [byte] */ 58*3b58acd4Swdenk #define StMemBnk1Sp StMemBnkSp /* Static Memory Bank 1 Space */ 59*3b58acd4Swdenk /* [byte] */ 60*3b58acd4Swdenk #define StMemBnk2Sp StMemBnkSp /* Static Memory Bank 2 Space */ 61*3b58acd4Swdenk /* [byte] */ 62*3b58acd4Swdenk #define StMemBnk3Sp StMemBnkSp /* Static Memory Bank 3 Space */ 63*3b58acd4Swdenk /* [byte] */ 64*3b58acd4Swdenk 65*3b58acd4Swdenk #define DRAMBnkSp MemBnkSp /* DRAM Bank Space [byte] */ 66*3b58acd4Swdenk #define DRAMBnk0Sp DRAMBnkSp /* DRAM Bank 0 Space [byte] */ 67*3b58acd4Swdenk #define DRAMBnk1Sp DRAMBnkSp /* DRAM Bank 1 Space [byte] */ 68*3b58acd4Swdenk #define DRAMBnk2Sp DRAMBnkSp /* DRAM Bank 2 Space [byte] */ 69*3b58acd4Swdenk #define DRAMBnk3Sp DRAMBnkSp /* DRAM Bank 3 Space [byte] */ 70*3b58acd4Swdenk 71*3b58acd4Swdenk #define ZeroMemSp MemBnkSp /* Zero Memory bank Space [byte] */ 72*3b58acd4Swdenk 73*3b58acd4Swdenk #define _StMemBnk(Nb) /* Static Memory Bank [0..3] */ \ 74*3b58acd4Swdenk (0x00000000 + (Nb)*StMemBnkSp) 75*3b58acd4Swdenk #define _StMemBnk0 _StMemBnk (0) /* Static Memory Bank 0 */ 76*3b58acd4Swdenk #define _StMemBnk1 _StMemBnk (1) /* Static Memory Bank 1 */ 77*3b58acd4Swdenk #define _StMemBnk2 _StMemBnk (2) /* Static Memory Bank 2 */ 78*3b58acd4Swdenk #define _StMemBnk3 _StMemBnk (3) /* Static Memory Bank 3 */ 79*3b58acd4Swdenk 80*3b58acd4Swdenk #if LANGUAGE == C 81*3b58acd4Swdenk typedef Quad StMemBnkType [StMemBnkSp/sizeof (Quad)] ; 82*3b58acd4Swdenk #define StMemBnk /* Static Memory Bank [0..3] */ \ 83*3b58acd4Swdenk ((StMemBnkType *) io_p2v (_StMemBnk (0))) 84*3b58acd4Swdenk #define StMemBnk0 (StMemBnk [0]) /* Static Memory Bank 0 */ 85*3b58acd4Swdenk #define StMemBnk1 (StMemBnk [1]) /* Static Memory Bank 1 */ 86*3b58acd4Swdenk #define StMemBnk2 (StMemBnk [2]) /* Static Memory Bank 2 */ 87*3b58acd4Swdenk #define StMemBnk3 (StMemBnk [3]) /* Static Memory Bank 3 */ 88*3b58acd4Swdenk #endif /* LANGUAGE == C */ 89*3b58acd4Swdenk 90*3b58acd4Swdenk #define _DRAMBnk(Nb) /* DRAM Bank [0..3] */ \ 91*3b58acd4Swdenk (0xC0000000 + (Nb)*DRAMBnkSp) 92*3b58acd4Swdenk #define _DRAMBnk0 _DRAMBnk (0) /* DRAM Bank 0 */ 93*3b58acd4Swdenk #define _DRAMBnk1 _DRAMBnk (1) /* DRAM Bank 1 */ 94*3b58acd4Swdenk #define _DRAMBnk2 _DRAMBnk (2) /* DRAM Bank 2 */ 95*3b58acd4Swdenk #define _DRAMBnk3 _DRAMBnk (3) /* DRAM Bank 3 */ 96*3b58acd4Swdenk 97*3b58acd4Swdenk #if LANGUAGE == C 98*3b58acd4Swdenk typedef Quad DRAMBnkType [DRAMBnkSp/sizeof (Quad)] ; 99*3b58acd4Swdenk #define DRAMBnk /* DRAM Bank [0..3] */ \ 100*3b58acd4Swdenk ((DRAMBnkType *) io_p2v (_DRAMBnk (0))) 101*3b58acd4Swdenk #define DRAMBnk0 (DRAMBnk [0]) /* DRAM Bank 0 */ 102*3b58acd4Swdenk #define DRAMBnk1 (DRAMBnk [1]) /* DRAM Bank 1 */ 103*3b58acd4Swdenk #define DRAMBnk2 (DRAMBnk [2]) /* DRAM Bank 2 */ 104*3b58acd4Swdenk #define DRAMBnk3 (DRAMBnk [3]) /* DRAM Bank 3 */ 105*3b58acd4Swdenk #endif /* LANGUAGE == C */ 106*3b58acd4Swdenk 107*3b58acd4Swdenk #define _ZeroMem 0xE0000000 /* Zero Memory bank */ 108*3b58acd4Swdenk 109*3b58acd4Swdenk #if LANGUAGE == C 110*3b58acd4Swdenk typedef Quad ZeroMemType [ZeroMemSp/sizeof (Quad)] ; 111*3b58acd4Swdenk #define ZeroMem /* Zero Memory bank */ \ 112*3b58acd4Swdenk (*((ZeroMemType *) io_p2v (_ZeroMem))) 113*3b58acd4Swdenk #endif /* LANGUAGE == C */ 114*3b58acd4Swdenk 115*3b58acd4Swdenk 116*3b58acd4Swdenk /* 117*3b58acd4Swdenk * Personal Computer Memory Card International Association (PCMCIA) sockets 118*3b58acd4Swdenk */ 119*3b58acd4Swdenk 120*3b58acd4Swdenk #define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */ 121*3b58acd4Swdenk #define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */ 122*3b58acd4Swdenk #define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */ 123*3b58acd4Swdenk #define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */ 124*3b58acd4Swdenk #define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */ 125*3b58acd4Swdenk 126*3b58acd4Swdenk #define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */ 127*3b58acd4Swdenk #define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */ 128*3b58acd4Swdenk #define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */ 129*3b58acd4Swdenk #define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */ 130*3b58acd4Swdenk 131*3b58acd4Swdenk #define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */ 132*3b58acd4Swdenk #define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */ 133*3b58acd4Swdenk #define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */ 134*3b58acd4Swdenk #define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */ 135*3b58acd4Swdenk 136*3b58acd4Swdenk #define _PCMCIA(Nb) /* PCMCIA [0..1] */ \ 137*3b58acd4Swdenk (0x20000000 + (Nb)*PCMCIASp) 138*3b58acd4Swdenk #define _PCMCIAIO(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */ 139*3b58acd4Swdenk #define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \ 140*3b58acd4Swdenk (_PCMCIA (Nb) + 2*PCMCIAPrtSp) 141*3b58acd4Swdenk #define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \ 142*3b58acd4Swdenk (_PCMCIA (Nb) + 3*PCMCIAPrtSp) 143*3b58acd4Swdenk 144*3b58acd4Swdenk #define _PCMCIA0 _PCMCIA (0) /* PCMCIA 0 */ 145*3b58acd4Swdenk #define _PCMCIA0IO _PCMCIAIO (0) /* PCMCIA 0 I/O */ 146*3b58acd4Swdenk #define _PCMCIA0Attr _PCMCIAAttr (0) /* PCMCIA 0 Attribute */ 147*3b58acd4Swdenk #define _PCMCIA0Mem _PCMCIAMem (0) /* PCMCIA 0 Memory */ 148*3b58acd4Swdenk 149*3b58acd4Swdenk #define _PCMCIA1 _PCMCIA (1) /* PCMCIA 1 */ 150*3b58acd4Swdenk #define _PCMCIA1IO _PCMCIAIO (1) /* PCMCIA 1 I/O */ 151*3b58acd4Swdenk #define _PCMCIA1Attr _PCMCIAAttr (1) /* PCMCIA 1 Attribute */ 152*3b58acd4Swdenk #define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */ 153*3b58acd4Swdenk 154*3b58acd4Swdenk #if LANGUAGE == C 155*3b58acd4Swdenk 156*3b58acd4Swdenk typedef Quad PCMCIAPrtType [PCMCIAPrtSp/sizeof (Quad)] ; 157*3b58acd4Swdenk typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; 158*3b58acd4Swdenk 159*3b58acd4Swdenk #define PCMCIA0 /* PCMCIA 0 */ \ 160*3b58acd4Swdenk (*((PCMCIAType *) io_p2v (_PCMCIA0))) 161*3b58acd4Swdenk #define PCMCIA0IO /* PCMCIA 0 I/O */ \ 162*3b58acd4Swdenk (*((PCMCIAPrtType *) io_p2v (_PCMCIA0IO))) 163*3b58acd4Swdenk #define PCMCIA0Attr /* PCMCIA 0 Attribute */ \ 164*3b58acd4Swdenk (*((PCMCIAPrtType *) io_p2v (_PCMCIA0Attr))) 165*3b58acd4Swdenk #define PCMCIA0Mem /* PCMCIA 0 Memory */ \ 166*3b58acd4Swdenk (*((PCMCIAPrtType *) io_p2v (_PCMCIA0Mem))) 167*3b58acd4Swdenk 168*3b58acd4Swdenk #define PCMCIA1 /* PCMCIA 1 */ \ 169*3b58acd4Swdenk (*((PCMCIAType *) io_p2v (_PCMCIA1))) 170*3b58acd4Swdenk #define PCMCIA1IO /* PCMCIA 1 I/O */ \ 171*3b58acd4Swdenk (*((PCMCIAPrtType *) io_p2v (_PCMCIA1IO))) 172*3b58acd4Swdenk #define PCMCIA1Attr /* PCMCIA 1 Attribute */ \ 173*3b58acd4Swdenk (*((PCMCIAPrtType *) io_p2v (_PCMCIA1Attr))) 174*3b58acd4Swdenk #define PCMCIA1Mem /* PCMCIA 1 Memory */ \ 175*3b58acd4Swdenk (*((PCMCIAPrtType *) io_p2v (_PCMCIA1Mem))) 176*3b58acd4Swdenk 177*3b58acd4Swdenk #endif /* LANGUAGE == C */ 178*3b58acd4Swdenk 179*3b58acd4Swdenk 180*3b58acd4Swdenk /* 181*3b58acd4Swdenk * Universal Serial Bus (USB) Device Controller (UDC) control registers 182*3b58acd4Swdenk * 183*3b58acd4Swdenk * Registers 184*3b58acd4Swdenk * Ser0UDCCR Serial port 0 Universal Serial Bus (USB) Device 185*3b58acd4Swdenk * Controller (UDC) Control Register (read/write). 186*3b58acd4Swdenk * Ser0UDCAR Serial port 0 Universal Serial Bus (USB) Device 187*3b58acd4Swdenk * Controller (UDC) Address Register (read/write). 188*3b58acd4Swdenk * Ser0UDCOMP Serial port 0 Universal Serial Bus (USB) Device 189*3b58acd4Swdenk * Controller (UDC) Output Maximum Packet size register 190*3b58acd4Swdenk * (read/write). 191*3b58acd4Swdenk * Ser0UDCIMP Serial port 0 Universal Serial Bus (USB) Device 192*3b58acd4Swdenk * Controller (UDC) Input Maximum Packet size register 193*3b58acd4Swdenk * (read/write). 194*3b58acd4Swdenk * Ser0UDCCS0 Serial port 0 Universal Serial Bus (USB) Device 195*3b58acd4Swdenk * Controller (UDC) Control/Status register end-point 0 196*3b58acd4Swdenk * (read/write). 197*3b58acd4Swdenk * Ser0UDCCS1 Serial port 0 Universal Serial Bus (USB) Device 198*3b58acd4Swdenk * Controller (UDC) Control/Status register end-point 1 199*3b58acd4Swdenk * (output, read/write). 200*3b58acd4Swdenk * Ser0UDCCS2 Serial port 0 Universal Serial Bus (USB) Device 201*3b58acd4Swdenk * Controller (UDC) Control/Status register end-point 2 202*3b58acd4Swdenk * (input, read/write). 203*3b58acd4Swdenk * Ser0UDCD0 Serial port 0 Universal Serial Bus (USB) Device 204*3b58acd4Swdenk * Controller (UDC) Data register end-point 0 205*3b58acd4Swdenk * (read/write). 206*3b58acd4Swdenk * Ser0UDCWC Serial port 0 Universal Serial Bus (USB) Device 207*3b58acd4Swdenk * Controller (UDC) Write Count register end-point 0 208*3b58acd4Swdenk * (read). 209*3b58acd4Swdenk * Ser0UDCDR Serial port 0 Universal Serial Bus (USB) Device 210*3b58acd4Swdenk * Controller (UDC) Data Register (read/write). 211*3b58acd4Swdenk * Ser0UDCSR Serial port 0 Universal Serial Bus (USB) Device 212*3b58acd4Swdenk * Controller (UDC) Status Register (read/write). 213*3b58acd4Swdenk */ 214*3b58acd4Swdenk 215*3b58acd4Swdenk #define _Ser0UDCCR 0x80000000 /* Ser. port 0 UDC Control Reg. */ 216*3b58acd4Swdenk #define _Ser0UDCAR 0x80000004 /* Ser. port 0 UDC Address Reg. */ 217*3b58acd4Swdenk #define _Ser0UDCOMP 0x80000008 /* Ser. port 0 UDC Output Maximum */ 218*3b58acd4Swdenk /* Packet size reg. */ 219*3b58acd4Swdenk #define _Ser0UDCIMP 0x8000000C /* Ser. port 0 UDC Input Maximum */ 220*3b58acd4Swdenk /* Packet size reg. */ 221*3b58acd4Swdenk #define _Ser0UDCCS0 0x80000010 /* Ser. port 0 UDC Control/Status */ 222*3b58acd4Swdenk /* reg. end-point 0 */ 223*3b58acd4Swdenk #define _Ser0UDCCS1 0x80000014 /* Ser. port 0 UDC Control/Status */ 224*3b58acd4Swdenk /* reg. end-point 1 (output) */ 225*3b58acd4Swdenk #define _Ser0UDCCS2 0x80000018 /* Ser. port 0 UDC Control/Status */ 226*3b58acd4Swdenk /* reg. end-point 2 (input) */ 227*3b58acd4Swdenk #define _Ser0UDCD0 0x8000001C /* Ser. port 0 UDC Data reg. */ 228*3b58acd4Swdenk /* end-point 0 */ 229*3b58acd4Swdenk #define _Ser0UDCWC 0x80000020 /* Ser. port 0 UDC Write Count */ 230*3b58acd4Swdenk /* reg. end-point 0 */ 231*3b58acd4Swdenk #define _Ser0UDCDR 0x80000028 /* Ser. port 0 UDC Data Reg. */ 232*3b58acd4Swdenk #define _Ser0UDCSR 0x80000030 /* Ser. port 0 UDC Status Reg. */ 233*3b58acd4Swdenk 234*3b58acd4Swdenk #if LANGUAGE == C 235*3b58acd4Swdenk #define Ser0UDCCR /* Ser. port 0 UDC Control Reg. */ \ 236*3b58acd4Swdenk (*((volatile Word *) io_p2v (_Ser0UDCCR))) 237*3b58acd4Swdenk #define Ser0UDCAR /* Ser. port 0 UDC Address Reg. */ \ 238*3b58acd4Swdenk (*((volatile Word *) io_p2v (_Ser0UDCAR))) 239*3b58acd4Swdenk #define Ser0UDCOMP /* Ser. port 0 UDC Output Maximum */ \ 240*3b58acd4Swdenk /* Packet size reg. */ \ 241*3b58acd4Swdenk (*((volatile Word *) io_p2v (_Ser0UDCOMP))) 242*3b58acd4Swdenk #define Ser0UDCIMP /* Ser. port 0 UDC Input Maximum */ \ 243*3b58acd4Swdenk /* Packet size reg. */ \ 244*3b58acd4Swdenk (*((volatile Word *) io_p2v (_Ser0UDCIMP))) 245*3b58acd4Swdenk #define Ser0UDCCS0 /* Ser. port 0 UDC Control/Status */ \ 246*3b58acd4Swdenk /* reg. end-point 0 */ \ 247*3b58acd4Swdenk (*((volatile Word *) io_p2v (_Ser0UDCCS0))) 248*3b58acd4Swdenk #define Ser0UDCCS1 /* Ser. port 0 UDC Control/Status */ \ 249*3b58acd4Swdenk /* reg. end-point 1 (output) */ \ 250*3b58acd4Swdenk (*((volatile Word *) io_p2v (_Ser0UDCCS1))) 251*3b58acd4Swdenk #define Ser0UDCCS2 /* Ser. port 0 UDC Control/Status */ \ 252*3b58acd4Swdenk /* reg. end-point 2 (input) */ \ 253*3b58acd4Swdenk (*((volatile Word *) io_p2v (_Ser0UDCCS2))) 254*3b58acd4Swdenk #define Ser0UDCD0 /* Ser. port 0 UDC Data reg. */ \ 255*3b58acd4Swdenk /* end-point 0 */ \ 256*3b58acd4Swdenk (*((volatile Word *) io_p2v (_Ser0UDCD0))) 257*3b58acd4Swdenk #define Ser0UDCWC /* Ser. port 0 UDC Write Count */ \ 258*3b58acd4Swdenk /* reg. end-point 0 */ \ 259*3b58acd4Swdenk (*((volatile Word *) io_p2v (_Ser0UDCWC))) 260*3b58acd4Swdenk #define Ser0UDCDR /* Ser. port 0 UDC Data Reg. */ \ 261*3b58acd4Swdenk (*((volatile Word *) io_p2v (_Ser0UDCDR))) 262*3b58acd4Swdenk #define Ser0UDCSR /* Ser. port 0 UDC Status Reg. */ \ 263*3b58acd4Swdenk (*((volatile Word *) io_p2v (_Ser0UDCSR))) 264*3b58acd4Swdenk #endif /* LANGUAGE == C */ 265*3b58acd4Swdenk 266*3b58acd4Swdenk #define UDCCR_UDD 0x00000001 /* UDC Disable */ 267*3b58acd4Swdenk #define UDCCR_UDA 0x00000002 /* UDC Active (read) */ 268*3b58acd4Swdenk #define UDCCR_RESIM 0x00000004 /* Resume Interrupt Mask, per errata */ 269*3b58acd4Swdenk #define UDCCR_EIM 0x00000008 /* End-point 0 Interrupt Mask */ 270*3b58acd4Swdenk /* (disable) */ 271*3b58acd4Swdenk #define UDCCR_RIM 0x00000010 /* Receive Interrupt Mask */ 272*3b58acd4Swdenk /* (disable) */ 273*3b58acd4Swdenk #define UDCCR_TIM 0x00000020 /* Transmit Interrupt Mask */ 274*3b58acd4Swdenk /* (disable) */ 275*3b58acd4Swdenk #define UDCCR_SRM 0x00000040 /* Suspend/Resume interrupt Mask */ 276*3b58acd4Swdenk /* (disable) */ 277*3b58acd4Swdenk #define UDCCR_SUSIM UDCCR_SRM /* Per errata, SRM just masks suspend */ 278*3b58acd4Swdenk #define UDCCR_REM 0x00000080 /* REset interrupt Mask (disable) */ 279*3b58acd4Swdenk 280*3b58acd4Swdenk #define UDCAR_ADD Fld (7, 0) /* function ADDress */ 281*3b58acd4Swdenk 282*3b58acd4Swdenk #define UDCOMP_OUTMAXP Fld (8, 0) /* OUTput MAXimum Packet size - 1 */ 283*3b58acd4Swdenk /* [byte] */ 284*3b58acd4Swdenk #define UDCOMP_OutMaxPkt(Size) /* Output Maximum Packet size */ \ 285*3b58acd4Swdenk /* [1..256 byte] */ \ 286*3b58acd4Swdenk (((Size) - 1) << FShft (UDCOMP_OUTMAXP)) 287*3b58acd4Swdenk 288*3b58acd4Swdenk #define UDCIMP_INMAXP Fld (8, 0) /* INput MAXimum Packet size - 1 */ 289*3b58acd4Swdenk /* [byte] */ 290*3b58acd4Swdenk #define UDCIMP_InMaxPkt(Size) /* Input Maximum Packet size */ \ 291*3b58acd4Swdenk /* [1..256 byte] */ \ 292*3b58acd4Swdenk (((Size) - 1) << FShft (UDCIMP_INMAXP)) 293*3b58acd4Swdenk 294*3b58acd4Swdenk #define UDCCS0_OPR 0x00000001 /* Output Packet Ready (read) */ 295*3b58acd4Swdenk #define UDCCS0_IPR 0x00000002 /* Input Packet Ready */ 296*3b58acd4Swdenk #define UDCCS0_SST 0x00000004 /* Sent STall */ 297*3b58acd4Swdenk #define UDCCS0_FST 0x00000008 /* Force STall */ 298*3b58acd4Swdenk #define UDCCS0_DE 0x00000010 /* Data End */ 299*3b58acd4Swdenk #define UDCCS0_SE 0x00000020 /* Setup End (read) */ 300*3b58acd4Swdenk #define UDCCS0_SO 0x00000040 /* Serviced Output packet ready */ 301*3b58acd4Swdenk /* (write) */ 302*3b58acd4Swdenk #define UDCCS0_SSE 0x00000080 /* Serviced Setup End (write) */ 303*3b58acd4Swdenk 304*3b58acd4Swdenk #define UDCCS1_RFS 0x00000001 /* Receive FIFO 12-bytes or more */ 305*3b58acd4Swdenk /* Service request (read) */ 306*3b58acd4Swdenk #define UDCCS1_RPC 0x00000002 /* Receive Packet Complete */ 307*3b58acd4Swdenk #define UDCCS1_RPE 0x00000004 /* Receive Packet Error (read) */ 308*3b58acd4Swdenk #define UDCCS1_SST 0x00000008 /* Sent STall */ 309*3b58acd4Swdenk #define UDCCS1_FST 0x00000010 /* Force STall */ 310*3b58acd4Swdenk #define UDCCS1_RNE 0x00000020 /* Receive FIFO Not Empty (read) */ 311*3b58acd4Swdenk 312*3b58acd4Swdenk #define UDCCS2_TFS 0x00000001 /* Transmit FIFO 8-bytes or less */ 313*3b58acd4Swdenk /* Service request (read) */ 314*3b58acd4Swdenk #define UDCCS2_TPC 0x00000002 /* Transmit Packet Complete */ 315*3b58acd4Swdenk #define UDCCS2_TPE 0x00000004 /* Transmit Packet Error (read) */ 316*3b58acd4Swdenk #define UDCCS2_TUR 0x00000008 /* Transmit FIFO Under-Run */ 317*3b58acd4Swdenk #define UDCCS2_SST 0x00000010 /* Sent STall */ 318*3b58acd4Swdenk #define UDCCS2_FST 0x00000020 /* Force STall */ 319*3b58acd4Swdenk 320*3b58acd4Swdenk #define UDCD0_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ 321*3b58acd4Swdenk 322*3b58acd4Swdenk #define UDCWC_WC Fld (4, 0) /* Write Count */ 323*3b58acd4Swdenk 324*3b58acd4Swdenk #define UDCDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ 325*3b58acd4Swdenk 326*3b58acd4Swdenk #define UDCSR_EIR 0x00000001 /* End-point 0 Interrupt Request */ 327*3b58acd4Swdenk #define UDCSR_RIR 0x00000002 /* Receive Interrupt Request */ 328*3b58acd4Swdenk #define UDCSR_TIR 0x00000004 /* Transmit Interrupt Request */ 329*3b58acd4Swdenk #define UDCSR_SUSIR 0x00000008 /* SUSpend Interrupt Request */ 330*3b58acd4Swdenk #define UDCSR_RESIR 0x00000010 /* RESume Interrupt Request */ 331*3b58acd4Swdenk #define UDCSR_RSTIR 0x00000020 /* ReSeT Interrupt Request */ 332*3b58acd4Swdenk 333*3b58acd4Swdenk 334*3b58acd4Swdenk /* 335*3b58acd4Swdenk * Universal Asynchronous Receiver/Transmitter (UART) control registers 336*3b58acd4Swdenk * 337*3b58acd4Swdenk * Registers 338*3b58acd4Swdenk * Ser1UTCR0 Serial port 1 Universal Asynchronous 339*3b58acd4Swdenk * Receiver/Transmitter (UART) Control Register 0 340*3b58acd4Swdenk * (read/write). 341*3b58acd4Swdenk * Ser1UTCR1 Serial port 1 Universal Asynchronous 342*3b58acd4Swdenk * Receiver/Transmitter (UART) Control Register 1 343*3b58acd4Swdenk * (read/write). 344*3b58acd4Swdenk * Ser1UTCR2 Serial port 1 Universal Asynchronous 345*3b58acd4Swdenk * Receiver/Transmitter (UART) Control Register 2 346*3b58acd4Swdenk * (read/write). 347*3b58acd4Swdenk * Ser1UTCR3 Serial port 1 Universal Asynchronous 348*3b58acd4Swdenk * Receiver/Transmitter (UART) Control Register 3 349*3b58acd4Swdenk * (read/write). 350*3b58acd4Swdenk * Ser1UTDR Serial port 1 Universal Asynchronous 351*3b58acd4Swdenk * Receiver/Transmitter (UART) Data Register 352*3b58acd4Swdenk * (read/write). 353*3b58acd4Swdenk * Ser1UTSR0 Serial port 1 Universal Asynchronous 354*3b58acd4Swdenk * Receiver/Transmitter (UART) Status Register 0 355*3b58acd4Swdenk * (read/write). 356*3b58acd4Swdenk * Ser1UTSR1 Serial port 1 Universal Asynchronous 357*3b58acd4Swdenk * Receiver/Transmitter (UART) Status Register 1 (read). 358*3b58acd4Swdenk * 359*3b58acd4Swdenk * Ser2UTCR0 Serial port 2 Universal Asynchronous 360*3b58acd4Swdenk * Receiver/Transmitter (UART) Control Register 0 361*3b58acd4Swdenk * (read/write). 362*3b58acd4Swdenk * Ser2UTCR1 Serial port 2 Universal Asynchronous 363*3b58acd4Swdenk * Receiver/Transmitter (UART) Control Register 1 364*3b58acd4Swdenk * (read/write). 365*3b58acd4Swdenk * Ser2UTCR2 Serial port 2 Universal Asynchronous 366*3b58acd4Swdenk * Receiver/Transmitter (UART) Control Register 2 367*3b58acd4Swdenk * (read/write). 368*3b58acd4Swdenk * Ser2UTCR3 Serial port 2 Universal Asynchronous 369*3b58acd4Swdenk * Receiver/Transmitter (UART) Control Register 3 370*3b58acd4Swdenk * (read/write). 371*3b58acd4Swdenk * Ser2UTCR4 Serial port 2 Universal Asynchronous 372*3b58acd4Swdenk * Receiver/Transmitter (UART) Control Register 4 373*3b58acd4Swdenk * (read/write). 374*3b58acd4Swdenk * Ser2UTDR Serial port 2 Universal Asynchronous 375*3b58acd4Swdenk * Receiver/Transmitter (UART) Data Register 376*3b58acd4Swdenk * (read/write). 377*3b58acd4Swdenk * Ser2UTSR0 Serial port 2 Universal Asynchronous 378*3b58acd4Swdenk * Receiver/Transmitter (UART) Status Register 0 379*3b58acd4Swdenk * (read/write). 380*3b58acd4Swdenk * Ser2UTSR1 Serial port 2 Universal Asynchronous 381*3b58acd4Swdenk * Receiver/Transmitter (UART) Status Register 1 (read). 382*3b58acd4Swdenk * 383*3b58acd4Swdenk * Ser3UTCR0 Serial port 3 Universal Asynchronous 384*3b58acd4Swdenk * Receiver/Transmitter (UART) Control Register 0 385*3b58acd4Swdenk * (read/write). 386*3b58acd4Swdenk * Ser3UTCR1 Serial port 3 Universal Asynchronous 387*3b58acd4Swdenk * Receiver/Transmitter (UART) Control Register 1 388*3b58acd4Swdenk * (read/write). 389*3b58acd4Swdenk * Ser3UTCR2 Serial port 3 Universal Asynchronous 390*3b58acd4Swdenk * Receiver/Transmitter (UART) Control Register 2 391*3b58acd4Swdenk * (read/write). 392*3b58acd4Swdenk * Ser3UTCR3 Serial port 3 Universal Asynchronous 393*3b58acd4Swdenk * Receiver/Transmitter (UART) Control Register 3 394*3b58acd4Swdenk * (read/write). 395*3b58acd4Swdenk * Ser3UTDR Serial port 3 Universal Asynchronous 396*3b58acd4Swdenk * Receiver/Transmitter (UART) Data Register 397*3b58acd4Swdenk * (read/write). 398*3b58acd4Swdenk * Ser3UTSR0 Serial port 3 Universal Asynchronous 399*3b58acd4Swdenk * Receiver/Transmitter (UART) Status Register 0 400*3b58acd4Swdenk * (read/write). 401*3b58acd4Swdenk * Ser3UTSR1 Serial port 3 Universal Asynchronous 402*3b58acd4Swdenk * Receiver/Transmitter (UART) Status Register 1 (read). 403*3b58acd4Swdenk * 404*3b58acd4Swdenk * Clocks 405*3b58acd4Swdenk * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz 406*3b58acd4Swdenk * or 3.5795 MHz). 407*3b58acd4Swdenk * fua, Tua Frequency, period of the UART communication. 408*3b58acd4Swdenk */ 409*3b58acd4Swdenk 410*3b58acd4Swdenk #define _UTCR0(Nb) /* UART Control Reg. 0 [1..3] */ \ 411*3b58acd4Swdenk (0x80010000 + ((Nb) - 1)*0x00020000) 412*3b58acd4Swdenk #define _UTCR1(Nb) /* UART Control Reg. 1 [1..3] */ \ 413*3b58acd4Swdenk (0x80010004 + ((Nb) - 1)*0x00020000) 414*3b58acd4Swdenk #define _UTCR2(Nb) /* UART Control Reg. 2 [1..3] */ \ 415*3b58acd4Swdenk (0x80010008 + ((Nb) - 1)*0x00020000) 416*3b58acd4Swdenk #define _UTCR3(Nb) /* UART Control Reg. 3 [1..3] */ \ 417*3b58acd4Swdenk (0x8001000C + ((Nb) - 1)*0x00020000) 418*3b58acd4Swdenk #define _UTCR4(Nb) /* UART Control Reg. 4 [2] */ \ 419*3b58acd4Swdenk (0x80010010 + ((Nb) - 1)*0x00020000) 420*3b58acd4Swdenk #define _UTDR(Nb) /* UART Data Reg. [1..3] */ \ 421*3b58acd4Swdenk (0x80010014 + ((Nb) - 1)*0x00020000) 422*3b58acd4Swdenk #define _UTSR0(Nb) /* UART Status Reg. 0 [1..3] */ \ 423*3b58acd4Swdenk (0x8001001C + ((Nb) - 1)*0x00020000) 424*3b58acd4Swdenk #define _UTSR1(Nb) /* UART Status Reg. 1 [1..3] */ \ 425*3b58acd4Swdenk (0x80010020 + ((Nb) - 1)*0x00020000) 426*3b58acd4Swdenk 427*3b58acd4Swdenk #define _Ser1UTCR0 _UTCR0 (1) /* Ser. port 1 UART Control Reg. 0 */ 428*3b58acd4Swdenk #define _Ser1UTCR1 _UTCR1 (1) /* Ser. port 1 UART Control Reg. 1 */ 429*3b58acd4Swdenk #define _Ser1UTCR2 _UTCR2 (1) /* Ser. port 1 UART Control Reg. 2 */ 430*3b58acd4Swdenk #define _Ser1UTCR3 _UTCR3 (1) /* Ser. port 1 UART Control Reg. 3 */ 431*3b58acd4Swdenk #define _Ser1UTDR _UTDR (1) /* Ser. port 1 UART Data Reg. */ 432*3b58acd4Swdenk #define _Ser1UTSR0 _UTSR0 (1) /* Ser. port 1 UART Status Reg. 0 */ 433*3b58acd4Swdenk #define _Ser1UTSR1 _UTSR1 (1) /* Ser. port 1 UART Status Reg. 1 */ 434*3b58acd4Swdenk 435*3b58acd4Swdenk #define _Ser2UTCR0 _UTCR0 (2) /* Ser. port 2 UART Control Reg. 0 */ 436*3b58acd4Swdenk #define _Ser2UTCR1 _UTCR1 (2) /* Ser. port 2 UART Control Reg. 1 */ 437*3b58acd4Swdenk #define _Ser2UTCR2 _UTCR2 (2) /* Ser. port 2 UART Control Reg. 2 */ 438*3b58acd4Swdenk #define _Ser2UTCR3 _UTCR3 (2) /* Ser. port 2 UART Control Reg. 3 */ 439*3b58acd4Swdenk #define _Ser2UTCR4 _UTCR4 (2) /* Ser. port 2 UART Control Reg. 4 */ 440*3b58acd4Swdenk #define _Ser2UTDR _UTDR (2) /* Ser. port 2 UART Data Reg. */ 441*3b58acd4Swdenk #define _Ser2UTSR0 _UTSR0 (2) /* Ser. port 2 UART Status Reg. 0 */ 442*3b58acd4Swdenk #define _Ser2UTSR1 _UTSR1 (2) /* Ser. port 2 UART Status Reg. 1 */ 443*3b58acd4Swdenk 444*3b58acd4Swdenk #define _Ser3UTCR0 _UTCR0 (3) /* Ser. port 3 UART Control Reg. 0 */ 445*3b58acd4Swdenk #define _Ser3UTCR1 _UTCR1 (3) /* Ser. port 3 UART Control Reg. 1 */ 446*3b58acd4Swdenk #define _Ser3UTCR2 _UTCR2 (3) /* Ser. port 3 UART Control Reg. 2 */ 447*3b58acd4Swdenk #define _Ser3UTCR3 _UTCR3 (3) /* Ser. port 3 UART Control Reg. 3 */ 448*3b58acd4Swdenk #define _Ser3UTDR _UTDR (3) /* Ser. port 3 UART Data Reg. */ 449*3b58acd4Swdenk #define _Ser3UTSR0 _UTSR0 (3) /* Ser. port 3 UART Status Reg. 0 */ 450*3b58acd4Swdenk #define _Ser3UTSR1 _UTSR1 (3) /* Ser. port 3 UART Status Reg. 1 */ 451*3b58acd4Swdenk 452*3b58acd4Swdenk #if LANGUAGE == C 453*3b58acd4Swdenk 454*3b58acd4Swdenk #define Ser1UTCR0 /* Ser. port 1 UART Control Reg. 0 */ \ 455*3b58acd4Swdenk (*((volatile Word *) io_p2v (_Ser1UTCR0))) 456*3b58acd4Swdenk #define Ser1UTCR1 /* Ser. port 1 UART Control Reg. 1 */ \ 457*3b58acd4Swdenk (*((volatile Word *) io_p2v (_Ser1UTCR1))) 458*3b58acd4Swdenk #define Ser1UTCR2 /* Ser. port 1 UART Control Reg. 2 */ \ 459*3b58acd4Swdenk (*((volatile Word *) io_p2v (_Ser1UTCR2))) 460*3b58acd4Swdenk #define Ser1UTCR3 /* Ser. port 1 UART Control Reg. 3 */ \ 461*3b58acd4Swdenk (*((volatile Word *) io_p2v (_Ser1UTCR3))) 462*3b58acd4Swdenk #define Ser1UTDR /* Ser. port 1 UART Data Reg. */ \ 463*3b58acd4Swdenk (*((volatile Word *) io_p2v (_Ser1UTDR))) 464*3b58acd4Swdenk #define Ser1UTSR0 /* Ser. port 1 UART Status Reg. 0 */ \ 465*3b58acd4Swdenk (*((volatile Word *) io_p2v (_Ser1UTSR0))) 466*3b58acd4Swdenk #define Ser1UTSR1 /* Ser. port 1 UART Status Reg. 1 */ \ 467*3b58acd4Swdenk (*((volatile Word *) io_p2v (_Ser1UTSR1))) 468*3b58acd4Swdenk 469*3b58acd4Swdenk #define Ser2UTCR0 /* Ser. port 2 UART Control Reg. 0 */ \ 470*3b58acd4Swdenk (*((volatile Word *) io_p2v (_Ser2UTCR0))) 471*3b58acd4Swdenk #define Ser2UTCR1 /* Ser. port 2 UART Control Reg. 1 */ \ 472*3b58acd4Swdenk (*((volatile Word *) io_p2v (_Ser2UTCR1))) 473*3b58acd4Swdenk #define Ser2UTCR2 /* Ser. port 2 UART Control Reg. 2 */ \ 474*3b58acd4Swdenk (*((volatile Word *) io_p2v (_Ser2UTCR2))) 475*3b58acd4Swdenk #define Ser2UTCR3 /* Ser. port 2 UART Control Reg. 3 */ \ 476*3b58acd4Swdenk (*((volatile Word *) io_p2v (_Ser2UTCR3))) 477*3b58acd4Swdenk #define Ser2UTCR4 /* Ser. port 2 UART Control Reg. 4 */ \ 478*3b58acd4Swdenk (*((volatile Word *) io_p2v (_Ser2UTCR4))) 479*3b58acd4Swdenk #define Ser2UTDR /* Ser. port 2 UART Data Reg. */ \ 480*3b58acd4Swdenk (*((volatile Word *) io_p2v (_Ser2UTDR))) 481*3b58acd4Swdenk #define Ser2UTSR0 /* Ser. port 2 UART Status Reg. 0 */ \ 482*3b58acd4Swdenk (*((volatile Word *) io_p2v (_Ser2UTSR0))) 483*3b58acd4Swdenk #define Ser2UTSR1 /* Ser. port 2 UART Status Reg. 1 */ \ 484*3b58acd4Swdenk (*((volatile Word *) io_p2v (_Ser2UTSR1))) 485*3b58acd4Swdenk 486*3b58acd4Swdenk #define Ser3UTCR0 /* Ser. port 3 UART Control Reg. 0 */ \ 487*3b58acd4Swdenk (*((volatile Word *) io_p2v (_Ser3UTCR0))) 488*3b58acd4Swdenk #define Ser3UTCR1 /* Ser. port 3 UART Control Reg. 1 */ \ 489*3b58acd4Swdenk (*((volatile Word *) io_p2v (_Ser3UTCR1))) 490*3b58acd4Swdenk #define Ser3UTCR2 /* Ser. port 3 UART Control Reg. 2 */ \ 491*3b58acd4Swdenk (*((volatile Word *) io_p2v (_Ser3UTCR2))) 492*3b58acd4Swdenk #define Ser3UTCR3 /* Ser. port 3 UART Control Reg. 3 */ \ 493*3b58acd4Swdenk (*((volatile Word *) io_p2v (_Ser3UTCR3))) 494*3b58acd4Swdenk #define Ser3UTDR /* Ser. port 3 UART Data Reg. */ \ 495*3b58acd4Swdenk (*((volatile Word *) io_p2v (_Ser3UTDR))) 496*3b58acd4Swdenk #define Ser3UTSR0 /* Ser. port 3 UART Status Reg. 0 */ \ 497*3b58acd4Swdenk (*((volatile Word *) io_p2v (_Ser3UTSR0))) 498*3b58acd4Swdenk #define Ser3UTSR1 /* Ser. port 3 UART Status Reg. 1 */ \ 499*3b58acd4Swdenk (*((volatile Word *) io_p2v (_Ser3UTSR1))) 500*3b58acd4Swdenk 501*3b58acd4Swdenk #elif LANGUAGE == Assembly 502*3b58acd4Swdenk #define Ser1UTCR0 ( io_p2v (_Ser1UTCR0)) 503*3b58acd4Swdenk #define Ser1UTCR1 ( io_p2v (_Ser1UTCR1)) 504*3b58acd4Swdenk #define Ser1UTCR2 ( io_p2v (_Ser1UTCR2)) 505*3b58acd4Swdenk #define Ser1UTCR3 ( io_p2v (_Ser1UTCR3)) 506*3b58acd4Swdenk #define Ser1UTDR ( io_p2v (_Ser1UTDR)) 507*3b58acd4Swdenk #define Ser1UTSR0 ( io_p2v (_Ser1UTSR0)) 508*3b58acd4Swdenk #define Ser1UTSR1 ( io_p2v (_Ser1UTSR1)) 509*3b58acd4Swdenk 510*3b58acd4Swdenk #define Ser2UTCR0 ( io_p2v (_Ser2UTCR0)) 511*3b58acd4Swdenk #define Ser2UTCR1 ( io_p2v (_Ser2UTCR1)) 512*3b58acd4Swdenk #define Ser2UTCR2 ( io_p2v (_Ser2UTCR2)) 513*3b58acd4Swdenk #define Ser2UTCR3 ( io_p2v (_Ser2UTCR3)) 514*3b58acd4Swdenk #define Ser2UTCR4 ( io_p2v (_Ser2UTCR4)) 515*3b58acd4Swdenk #define Ser2UTDR ( io_p2v (_Ser2UTDR)) 516*3b58acd4Swdenk #define Ser2UTSR0 ( io_p2v (_Ser2UTSR0)) 517*3b58acd4Swdenk #define Ser2UTSR1 ( io_p2v (_Ser2UTSR1)) 518*3b58acd4Swdenk 519*3b58acd4Swdenk #define Ser3UTCR0 ( io_p2v (_Ser3UTCR0)) 520*3b58acd4Swdenk #define Ser3UTCR1 ( io_p2v (_Ser3UTCR1)) 521*3b58acd4Swdenk #define Ser3UTCR2 ( io_p2v (_Ser3UTCR2)) 522*3b58acd4Swdenk #define Ser3UTCR3 ( io_p2v (_Ser3UTCR3)) 523*3b58acd4Swdenk #define Ser3UTDR ( io_p2v (_Ser3UTDR)) 524*3b58acd4Swdenk #define Ser3UTSR0 ( io_p2v (_Ser3UTSR0)) 525*3b58acd4Swdenk #define Ser3UTSR1 ( io_p2v (_Ser3UTSR1)) 526*3b58acd4Swdenk 527*3b58acd4Swdenk #endif /* LANGUAGE == C */ 528*3b58acd4Swdenk 529*3b58acd4Swdenk #define UTCR0_PE 0x00000001 /* Parity Enable */ 530*3b58acd4Swdenk #define UTCR0_OES 0x00000002 /* Odd/Even parity Select */ 531*3b58acd4Swdenk #define UTCR0_OddPar (UTCR0_OES*0) /* Odd Parity */ 532*3b58acd4Swdenk #define UTCR0_EvenPar (UTCR0_OES*1) /* Even Parity */ 533*3b58acd4Swdenk #define UTCR0_SBS 0x00000004 /* Stop Bit Select */ 534*3b58acd4Swdenk #define UTCR0_1StpBit (UTCR0_SBS*0) /* 1 Stop Bit per frame */ 535*3b58acd4Swdenk #define UTCR0_2StpBit (UTCR0_SBS*1) /* 2 Stop Bits per frame */ 536*3b58acd4Swdenk #define UTCR0_DSS 0x00000008 /* Data Size Select */ 537*3b58acd4Swdenk #define UTCR0_7BitData (UTCR0_DSS*0) /* 7-Bit Data */ 538*3b58acd4Swdenk #define UTCR0_8BitData (UTCR0_DSS*1) /* 8-Bit Data */ 539*3b58acd4Swdenk #define UTCR0_SCE 0x00000010 /* Sample Clock Enable */ 540*3b58acd4Swdenk /* (ser. port 1: GPIO [18], */ 541*3b58acd4Swdenk /* ser. port 3: GPIO [20]) */ 542*3b58acd4Swdenk #define UTCR0_RCE 0x00000020 /* Receive Clock Edge select */ 543*3b58acd4Swdenk #define UTCR0_RcRsEdg (UTCR0_RCE*0) /* Receive clock Rising-Edge */ 544*3b58acd4Swdenk #define UTCR0_RcFlEdg (UTCR0_RCE*1) /* Receive clock Falling-Edge */ 545*3b58acd4Swdenk #define UTCR0_TCE 0x00000040 /* Transmit Clock Edge select */ 546*3b58acd4Swdenk #define UTCR0_TrRsEdg (UTCR0_TCE*0) /* Transmit clock Rising-Edge */ 547*3b58acd4Swdenk #define UTCR0_TrFlEdg (UTCR0_TCE*1) /* Transmit clock Falling-Edge */ 548*3b58acd4Swdenk #define UTCR0_Ser2IrDA /* Ser. port 2 IrDA settings */ \ 549*3b58acd4Swdenk (UTCR0_1StpBit + UTCR0_8BitData) 550*3b58acd4Swdenk 551*3b58acd4Swdenk #define UTCR1_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */ 552*3b58acd4Swdenk #define UTCR2_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */ 553*3b58acd4Swdenk /* fua = fxtl/(16*(BRD[11:0] + 1)) */ 554*3b58acd4Swdenk /* Tua = 16*(BRD [11:0] + 1)*Txtl */ 555*3b58acd4Swdenk #define UTCR1_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ 556*3b58acd4Swdenk (((Div) - 16)/16 >> FSize (UTCR2_BRD) << \ 557*3b58acd4Swdenk FShft (UTCR1_BRD)) 558*3b58acd4Swdenk #define UTCR2_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ 559*3b58acd4Swdenk (((Div) - 16)/16 & FAlnMsk (UTCR2_BRD) << \ 560*3b58acd4Swdenk FShft (UTCR2_BRD)) 561*3b58acd4Swdenk /* fua = fxtl/(16*Floor (Div/16)) */ 562*3b58acd4Swdenk /* Tua = 16*Floor (Div/16)*Txtl */ 563*3b58acd4Swdenk #define UTCR1_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ 564*3b58acd4Swdenk (((Div) - 1)/16 >> FSize (UTCR2_BRD) << \ 565*3b58acd4Swdenk FShft (UTCR1_BRD)) 566*3b58acd4Swdenk #define UTCR2_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ 567*3b58acd4Swdenk (((Div) - 1)/16 & FAlnMsk (UTCR2_BRD) << \ 568*3b58acd4Swdenk FShft (UTCR2_BRD)) 569*3b58acd4Swdenk /* fua = fxtl/(16*Ceil (Div/16)) */ 570*3b58acd4Swdenk /* Tua = 16*Ceil (Div/16)*Txtl */ 571*3b58acd4Swdenk 572*3b58acd4Swdenk #define UTCR3_RXE 0x00000001 /* Receive Enable */ 573*3b58acd4Swdenk #define UTCR3_TXE 0x00000002 /* Transmit Enable */ 574*3b58acd4Swdenk #define UTCR3_BRK 0x00000004 /* BReaK mode */ 575*3b58acd4Swdenk #define UTCR3_RIE 0x00000008 /* Receive FIFO 1/3-to-2/3-full or */ 576*3b58acd4Swdenk /* more Interrupt Enable */ 577*3b58acd4Swdenk #define UTCR3_TIE 0x00000010 /* Transmit FIFO 1/2-full or less */ 578*3b58acd4Swdenk /* Interrupt Enable */ 579*3b58acd4Swdenk #define UTCR3_LBM 0x00000020 /* Look-Back Mode */ 580*3b58acd4Swdenk #define UTCR3_Ser2IrDA /* Ser. port 2 IrDA settings (RIE, */ \ 581*3b58acd4Swdenk /* TIE, LBM can be set or cleared) */ \ 582*3b58acd4Swdenk (UTCR3_RXE + UTCR3_TXE) 583*3b58acd4Swdenk 584*3b58acd4Swdenk #define UTCR4_HSE 0x00000001 /* Hewlett-Packard Serial InfraRed */ 585*3b58acd4Swdenk /* (HP-SIR) modulation Enable */ 586*3b58acd4Swdenk #define UTCR4_NRZ (UTCR4_HSE*0) /* Non-Return to Zero modulation */ 587*3b58acd4Swdenk #define UTCR4_HPSIR (UTCR4_HSE*1) /* HP-SIR modulation */ 588*3b58acd4Swdenk #define UTCR4_LPM 0x00000002 /* Low-Power Mode */ 589*3b58acd4Swdenk #define UTCR4_Z3_16Bit (UTCR4_LPM*0) /* Zero pulse = 3/16 Bit time */ 590*3b58acd4Swdenk #define UTCR4_Z1_6us (UTCR4_LPM*1) /* Zero pulse = 1.6 us */ 591*3b58acd4Swdenk 592*3b58acd4Swdenk #define UTDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ 593*3b58acd4Swdenk #if 0 /* Hidden receive FIFO bits */ 594*3b58acd4Swdenk #define UTDR_PRE 0x00000100 /* receive PaRity Error (read) */ 595*3b58acd4Swdenk #define UTDR_FRE 0x00000200 /* receive FRaming Error (read) */ 596*3b58acd4Swdenk #define UTDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */ 597*3b58acd4Swdenk #endif /* 0 */ 598*3b58acd4Swdenk 599*3b58acd4Swdenk #define UTSR0_TFS 0x00000001 /* Transmit FIFO 1/2-full or less */ 600*3b58acd4Swdenk /* Service request (read) */ 601*3b58acd4Swdenk #define UTSR0_RFS 0x00000002 /* Receive FIFO 1/3-to-2/3-full or */ 602*3b58acd4Swdenk /* more Service request (read) */ 603*3b58acd4Swdenk #define UTSR0_RID 0x00000004 /* Receiver IDle */ 604*3b58acd4Swdenk #define UTSR0_RBB 0x00000008 /* Receive Beginning of Break */ 605*3b58acd4Swdenk #define UTSR0_REB 0x00000010 /* Receive End of Break */ 606*3b58acd4Swdenk #define UTSR0_EIF 0x00000020 /* Error In FIFO (read) */ 607*3b58acd4Swdenk 608*3b58acd4Swdenk #define UTSR1_TBY 0x00000001 /* Transmitter BusY (read) */ 609*3b58acd4Swdenk #define UTSR1_RNE 0x00000002 /* Receive FIFO Not Empty (read) */ 610*3b58acd4Swdenk #define UTSR1_TNF 0x00000004 /* Transmit FIFO Not Full (read) */ 611*3b58acd4Swdenk #define UTSR1_PRE 0x00000008 /* receive PaRity Error (read) */ 612*3b58acd4Swdenk #define UTSR1_FRE 0x00000010 /* receive FRaming Error (read) */ 613*3b58acd4Swdenk #define UTSR1_ROR 0x00000020 /* Receive FIFO Over-Run (read) */ 614*3b58acd4Swdenk 615*3b58acd4Swdenk 616*3b58acd4Swdenk /* 617*3b58acd4Swdenk * Synchronous Data Link Controller (SDLC) control registers 618*3b58acd4Swdenk * 619*3b58acd4Swdenk * Registers 620*3b58acd4Swdenk * Ser1SDCR0 Serial port 1 Synchronous Data Link Controller (SDLC) 621*3b58acd4Swdenk * Control Register 0 (read/write). 622*3b58acd4Swdenk * Ser1SDCR1 Serial port 1 Synchronous Data Link Controller (SDLC) 623*3b58acd4Swdenk * Control Register 1 (read/write). 624*3b58acd4Swdenk * Ser1SDCR2 Serial port 1 Synchronous Data Link Controller (SDLC) 625*3b58acd4Swdenk * Control Register 2 (read/write). 626*3b58acd4Swdenk * Ser1SDCR3 Serial port 1 Synchronous Data Link Controller (SDLC) 627*3b58acd4Swdenk * Control Register 3 (read/write). 628*3b58acd4Swdenk * Ser1SDCR4 Serial port 1 Synchronous Data Link Controller (SDLC) 629*3b58acd4Swdenk * Control Register 4 (read/write). 630*3b58acd4Swdenk * Ser1SDDR Serial port 1 Synchronous Data Link Controller (SDLC) 631*3b58acd4Swdenk * Data Register (read/write). 632*3b58acd4Swdenk * Ser1SDSR0 Serial port 1 Synchronous Data Link Controller (SDLC) 633*3b58acd4Swdenk * Status Register 0 (read/write). 634*3b58acd4Swdenk * Ser1SDSR1 Serial port 1 Synchronous Data Link Controller (SDLC) 635*3b58acd4Swdenk * Status Register 1 (read/write). 636*3b58acd4Swdenk * 637*3b58acd4Swdenk * Clocks 638*3b58acd4Swdenk * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz 639*3b58acd4Swdenk * or 3.5795 MHz). 640*3b58acd4Swdenk * fsd, Tsd Frequency, period of the SDLC communication. 641*3b58acd4Swdenk */ 642*3b58acd4Swdenk 643*3b58acd4Swdenk #define _Ser1SDCR0 0x80020060 /* Ser. port 1 SDLC Control Reg. 0 */ 644*3b58acd4Swdenk #define _Ser1SDCR1 0x80020064 /* Ser. port 1 SDLC Control Reg. 1 */ 645*3b58acd4Swdenk #define _Ser1SDCR2 0x80020068 /* Ser. port 1 SDLC Control Reg. 2 */ 646*3b58acd4Swdenk #define _Ser1SDCR3 0x8002006C /* Ser. port 1 SDLC Control Reg. 3 */ 647*3b58acd4Swdenk #define _Ser1SDCR4 0x80020070 /* Ser. port 1 SDLC Control Reg. 4 */ 648*3b58acd4Swdenk #define _Ser1SDDR 0x80020078 /* Ser. port 1 SDLC Data Reg. */ 649*3b58acd4Swdenk #define _Ser1SDSR0 0x80020080 /* Ser. port 1 SDLC Status Reg. 0 */ 650*3b58acd4Swdenk #define _Ser1SDSR1 0x80020084 /* Ser. port 1 SDLC Status Reg. 1 */ 651*3b58acd4Swdenk 652*3b58acd4Swdenk #if LANGUAGE == C 653*3b58acd4Swdenk #define Ser1SDCR0 /* Ser. port 1 SDLC Control Reg. 0 */ \ 654*3b58acd4Swdenk (*((volatile Word *) io_p2v (_Ser1SDCR0))) 655*3b58acd4Swdenk #define Ser1SDCR1 /* Ser. port 1 SDLC Control Reg. 1 */ \ 656*3b58acd4Swdenk (*((volatile Word *) io_p2v (_Ser1SDCR1))) 657*3b58acd4Swdenk #define Ser1SDCR2 /* Ser. port 1 SDLC Control Reg. 2 */ \ 658*3b58acd4Swdenk (*((volatile Word *) io_p2v (_Ser1SDCR2))) 659*3b58acd4Swdenk #define Ser1SDCR3 /* Ser. port 1 SDLC Control Reg. 3 */ \ 660*3b58acd4Swdenk (*((volatile Word *) io_p2v (_Ser1SDCR3))) 661*3b58acd4Swdenk #define Ser1SDCR4 /* Ser. port 1 SDLC Control Reg. 4 */ \ 662*3b58acd4Swdenk (*((volatile Word *) io_p2v (_Ser1SDCR4))) 663*3b58acd4Swdenk #define Ser1SDDR /* Ser. port 1 SDLC Data Reg. */ \ 664*3b58acd4Swdenk (*((volatile Word *) io_p2v (_Ser1SDDR))) 665*3b58acd4Swdenk #define Ser1SDSR0 /* Ser. port 1 SDLC Status Reg. 0 */ \ 666*3b58acd4Swdenk (*((volatile Word *) io_p2v (_Ser1SDSR0))) 667*3b58acd4Swdenk #define Ser1SDSR1 /* Ser. port 1 SDLC Status Reg. 1 */ \ 668*3b58acd4Swdenk (*((volatile Word *) io_p2v (_Ser1SDSR1))) 669*3b58acd4Swdenk #endif /* LANGUAGE == C */ 670*3b58acd4Swdenk 671*3b58acd4Swdenk #define SDCR0_SUS 0x00000001 /* SDLC/UART Select */ 672*3b58acd4Swdenk #define SDCR0_SDLC (SDCR0_SUS*0) /* SDLC mode (TXD1 & RXD1) */ 673*3b58acd4Swdenk #define SDCR0_UART (SDCR0_SUS*1) /* UART mode (TXD1 & RXD1) */ 674*3b58acd4Swdenk #define SDCR0_SDF 0x00000002 /* Single/Double start Flag select */ 675*3b58acd4Swdenk #define SDCR0_SglFlg (SDCR0_SDF*0) /* Single start Flag */ 676*3b58acd4Swdenk #define SDCR0_DblFlg (SDCR0_SDF*1) /* Double start Flag */ 677*3b58acd4Swdenk #define SDCR0_LBM 0x00000004 /* Look-Back Mode */ 678*3b58acd4Swdenk #define SDCR0_BMS 0x00000008 /* Bit Modulation Select */ 679*3b58acd4Swdenk #define SDCR0_FM0 (SDCR0_BMS*0) /* Freq. Modulation zero (0) */ 680*3b58acd4Swdenk #define SDCR0_NRZ (SDCR0_BMS*1) /* Non-Return to Zero modulation */ 681*3b58acd4Swdenk #define SDCR0_SCE 0x00000010 /* Sample Clock Enable (GPIO [16]) */ 682*3b58acd4Swdenk #define SDCR0_SCD 0x00000020 /* Sample Clock Direction select */ 683*3b58acd4Swdenk /* (GPIO [16]) */ 684*3b58acd4Swdenk #define SDCR0_SClkIn (SDCR0_SCD*0) /* Sample Clock Input */ 685*3b58acd4Swdenk #define SDCR0_SClkOut (SDCR0_SCD*1) /* Sample Clock Output */ 686*3b58acd4Swdenk #define SDCR0_RCE 0x00000040 /* Receive Clock Edge select */ 687*3b58acd4Swdenk #define SDCR0_RcRsEdg (SDCR0_RCE*0) /* Receive clock Rising-Edge */ 688*3b58acd4Swdenk #define SDCR0_RcFlEdg (SDCR0_RCE*1) /* Receive clock Falling-Edge */ 689*3b58acd4Swdenk #define SDCR0_TCE 0x00000080 /* Transmit Clock Edge select */ 690*3b58acd4Swdenk #define SDCR0_TrRsEdg (SDCR0_TCE*0) /* Transmit clock Rising-Edge */ 691*3b58acd4Swdenk #define SDCR0_TrFlEdg (SDCR0_TCE*1) /* Transmit clock Falling-Edge */ 692*3b58acd4Swdenk 693*3b58acd4Swdenk #define SDCR1_AAF 0x00000001 /* Abort After Frame enable */ 694*3b58acd4Swdenk /* (GPIO [17]) */ 695*3b58acd4Swdenk #define SDCR1_TXE 0x00000002 /* Transmit Enable */ 696*3b58acd4Swdenk #define SDCR1_RXE 0x00000004 /* Receive Enable */ 697*3b58acd4Swdenk #define SDCR1_RIE 0x00000008 /* Receive FIFO 1/3-to-2/3-full or */ 698*3b58acd4Swdenk /* more Interrupt Enable */ 699*3b58acd4Swdenk #define SDCR1_TIE 0x00000010 /* Transmit FIFO 1/2-full or less */ 700*3b58acd4Swdenk /* Interrupt Enable */ 701*3b58acd4Swdenk #define SDCR1_AME 0x00000020 /* Address Match Enable */ 702*3b58acd4Swdenk #define SDCR1_TUS 0x00000040 /* Transmit FIFO Under-run Select */ 703*3b58acd4Swdenk #define SDCR1_EFrmURn (SDCR1_TUS*0) /* End Frame on Under-Run */ 704*3b58acd4Swdenk #define SDCR1_AbortURn (SDCR1_TUS*1) /* Abort on Under-Run */ 705*3b58acd4Swdenk #define SDCR1_RAE 0x00000080 /* Receive Abort interrupt Enable */ 706*3b58acd4Swdenk 707*3b58acd4Swdenk #define SDCR2_AMV Fld (8, 0) /* Address Match Value */ 708*3b58acd4Swdenk 709*3b58acd4Swdenk #define SDCR3_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */ 710*3b58acd4Swdenk #define SDCR4_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */ 711*3b58acd4Swdenk /* fsd = fxtl/(16*(BRD[11:0] + 1)) */ 712*3b58acd4Swdenk /* Tsd = 16*(BRD[11:0] + 1)*Txtl */ 713*3b58acd4Swdenk #define SDCR3_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ 714*3b58acd4Swdenk (((Div) - 16)/16 >> FSize (SDCR4_BRD) << \ 715*3b58acd4Swdenk FShft (SDCR3_BRD)) 716*3b58acd4Swdenk #define SDCR4_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ 717*3b58acd4Swdenk (((Div) - 16)/16 & FAlnMsk (SDCR4_BRD) << \ 718*3b58acd4Swdenk FShft (SDCR4_BRD)) 719*3b58acd4Swdenk /* fsd = fxtl/(16*Floor (Div/16)) */ 720*3b58acd4Swdenk /* Tsd = 16*Floor (Div/16)*Txtl */ 721*3b58acd4Swdenk #define SDCR3_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ 722*3b58acd4Swdenk (((Div) - 1)/16 >> FSize (SDCR4_BRD) << \ 723*3b58acd4Swdenk FShft (SDCR3_BRD)) 724*3b58acd4Swdenk #define SDCR4_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ 725*3b58acd4Swdenk (((Div) - 1)/16 & FAlnMsk (SDCR4_BRD) << \ 726*3b58acd4Swdenk FShft (SDCR4_BRD)) 727*3b58acd4Swdenk /* fsd = fxtl/(16*Ceil (Div/16)) */ 728*3b58acd4Swdenk /* Tsd = 16*Ceil (Div/16)*Txtl */ 729*3b58acd4Swdenk 730*3b58acd4Swdenk #define SDDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ 731*3b58acd4Swdenk #if 0 /* Hidden receive FIFO bits */ 732*3b58acd4Swdenk #define SDDR_EOF 0x00000100 /* receive End-Of-Frame (read) */ 733*3b58acd4Swdenk #define SDDR_CRE 0x00000200 /* receive CRC Error (read) */ 734*3b58acd4Swdenk #define SDDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */ 735*3b58acd4Swdenk #endif /* 0 */ 736*3b58acd4Swdenk 737*3b58acd4Swdenk #define SDSR0_EIF 0x00000001 /* Error In FIFO (read) */ 738*3b58acd4Swdenk #define SDSR0_TUR 0x00000002 /* Transmit FIFO Under-Run */ 739*3b58acd4Swdenk #define SDSR0_RAB 0x00000004 /* Receive ABort */ 740*3b58acd4Swdenk #define SDSR0_TFS 0x00000008 /* Transmit FIFO 1/2-full or less */ 741*3b58acd4Swdenk /* Service request (read) */ 742*3b58acd4Swdenk #define SDSR0_RFS 0x00000010 /* Receive FIFO 1/3-to-2/3-full or */ 743*3b58acd4Swdenk /* more Service request (read) */ 744*3b58acd4Swdenk 745*3b58acd4Swdenk #define SDSR1_RSY 0x00000001 /* Receiver SYnchronized (read) */ 746*3b58acd4Swdenk #define SDSR1_TBY 0x00000002 /* Transmitter BusY (read) */ 747*3b58acd4Swdenk #define SDSR1_RNE 0x00000004 /* Receive FIFO Not Empty (read) */ 748*3b58acd4Swdenk #define SDSR1_TNF 0x00000008 /* Transmit FIFO Not Full (read) */ 749*3b58acd4Swdenk #define SDSR1_RTD 0x00000010 /* Receive Transition Detected */ 750*3b58acd4Swdenk #define SDSR1_EOF 0x00000020 /* receive End-Of-Frame (read) */ 751*3b58acd4Swdenk #define SDSR1_CRE 0x00000040 /* receive CRC Error (read) */ 752*3b58acd4Swdenk #define SDSR1_ROR 0x00000080 /* Receive FIFO Over-Run (read) */ 753*3b58acd4Swdenk 754*3b58acd4Swdenk 755*3b58acd4Swdenk /* 756*3b58acd4Swdenk * High-Speed Serial to Parallel controller (HSSP) control registers 757*3b58acd4Swdenk * 758*3b58acd4Swdenk * Registers 759*3b58acd4Swdenk * Ser2HSCR0 Serial port 2 High-Speed Serial to Parallel 760*3b58acd4Swdenk * controller (HSSP) Control Register 0 (read/write). 761*3b58acd4Swdenk * Ser2HSCR1 Serial port 2 High-Speed Serial to Parallel 762*3b58acd4Swdenk * controller (HSSP) Control Register 1 (read/write). 763*3b58acd4Swdenk * Ser2HSDR Serial port 2 High-Speed Serial to Parallel 764*3b58acd4Swdenk * controller (HSSP) Data Register (read/write). 765*3b58acd4Swdenk * Ser2HSSR0 Serial port 2 High-Speed Serial to Parallel 766*3b58acd4Swdenk * controller (HSSP) Status Register 0 (read/write). 767*3b58acd4Swdenk * Ser2HSSR1 Serial port 2 High-Speed Serial to Parallel 768*3b58acd4Swdenk * controller (HSSP) Status Register 1 (read). 769*3b58acd4Swdenk * Ser2HSCR2 Serial port 2 High-Speed Serial to Parallel 770*3b58acd4Swdenk * controller (HSSP) Control Register 2 (read/write). 771*3b58acd4Swdenk * [The HSCR2 register is only implemented in 772*3b58acd4Swdenk * versions 2.0 (rev. = 8) and higher of the StrongARM 773*3b58acd4Swdenk * SA-1100.] 774*3b58acd4Swdenk */ 775*3b58acd4Swdenk 776*3b58acd4Swdenk #define _Ser2HSCR0 0x80040060 /* Ser. port 2 HSSP Control Reg. 0 */ 777*3b58acd4Swdenk #define _Ser2HSCR1 0x80040064 /* Ser. port 2 HSSP Control Reg. 1 */ 778*3b58acd4Swdenk #define _Ser2HSDR 0x8004006C /* Ser. port 2 HSSP Data Reg. */ 779*3b58acd4Swdenk #define _Ser2HSSR0 0x80040074 /* Ser. port 2 HSSP Status Reg. 0 */ 780*3b58acd4Swdenk #define _Ser2HSSR1 0x80040078 /* Ser. port 2 HSSP Status Reg. 1 */ 781*3b58acd4Swdenk #define _Ser2HSCR2 0x90060028 /* Ser. port 2 HSSP Control Reg. 2 */ 782*3b58acd4Swdenk 783*3b58acd4Swdenk #if LANGUAGE == C 784*3b58acd4Swdenk #define Ser2HSCR0 /* Ser. port 2 HSSP Control Reg. 0 */ \ 785*3b58acd4Swdenk (*((volatile Word *) io_p2v (_Ser2HSCR0))) 786*3b58acd4Swdenk #define Ser2HSCR1 /* Ser. port 2 HSSP Control Reg. 1 */ \ 787*3b58acd4Swdenk (*((volatile Word *) io_p2v (_Ser2HSCR1))) 788*3b58acd4Swdenk #define Ser2HSDR /* Ser. port 2 HSSP Data Reg. */ \ 789*3b58acd4Swdenk (*((volatile Word *) io_p2v (_Ser2HSDR))) 790*3b58acd4Swdenk #define Ser2HSSR0 /* Ser. port 2 HSSP Status Reg. 0 */ \ 791*3b58acd4Swdenk (*((volatile Word *) io_p2v (_Ser2HSSR0))) 792*3b58acd4Swdenk #define Ser2HSSR1 /* Ser. port 2 HSSP Status Reg. 1 */ \ 793*3b58acd4Swdenk (*((volatile Word *) io_p2v (_Ser2HSSR1))) 794*3b58acd4Swdenk #define Ser2HSCR2 /* Ser. port 2 HSSP Control Reg. 2 */ \ 795*3b58acd4Swdenk (*((volatile Word *) io_p2v (_Ser2HSCR2))) 796*3b58acd4Swdenk #endif /* LANGUAGE == C */ 797*3b58acd4Swdenk 798*3b58acd4Swdenk #define HSCR0_ITR 0x00000001 /* IrDA Transmission Rate */ 799*3b58acd4Swdenk #define HSCR0_UART (HSCR0_ITR*0) /* UART mode (115.2 kb/s if IrDA) */ 800*3b58acd4Swdenk #define HSCR0_HSSP (HSCR0_ITR*1) /* HSSP mode (4 Mb/s) */ 801*3b58acd4Swdenk #define HSCR0_LBM 0x00000002 /* Look-Back Mode */ 802*3b58acd4Swdenk #define HSCR0_TUS 0x00000004 /* Transmit FIFO Under-run Select */ 803*3b58acd4Swdenk #define HSCR0_EFrmURn (HSCR0_TUS*0) /* End Frame on Under-Run */ 804*3b58acd4Swdenk #define HSCR0_AbortURn (HSCR0_TUS*1) /* Abort on Under-Run */ 805*3b58acd4Swdenk #define HSCR0_TXE 0x00000008 /* Transmit Enable */ 806*3b58acd4Swdenk #define HSCR0_RXE 0x00000010 /* Receive Enable */ 807*3b58acd4Swdenk #define HSCR0_RIE 0x00000020 /* Receive FIFO 2/5-to-3/5-full or */ 808*3b58acd4Swdenk /* more Interrupt Enable */ 809*3b58acd4Swdenk #define HSCR0_TIE 0x00000040 /* Transmit FIFO 1/2-full or less */ 810*3b58acd4Swdenk /* Interrupt Enable */ 811*3b58acd4Swdenk #define HSCR0_AME 0x00000080 /* Address Match Enable */ 812*3b58acd4Swdenk 813*3b58acd4Swdenk #define HSCR1_AMV Fld (8, 0) /* Address Match Value */ 814*3b58acd4Swdenk 815*3b58acd4Swdenk #define HSDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ 816*3b58acd4Swdenk #if 0 /* Hidden receive FIFO bits */ 817*3b58acd4Swdenk #define HSDR_EOF 0x00000100 /* receive End-Of-Frame (read) */ 818*3b58acd4Swdenk #define HSDR_CRE 0x00000200 /* receive CRC Error (read) */ 819*3b58acd4Swdenk #define HSDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */ 820*3b58acd4Swdenk #endif /* 0 */ 821*3b58acd4Swdenk 822*3b58acd4Swdenk #define HSSR0_EIF 0x00000001 /* Error In FIFO (read) */ 823*3b58acd4Swdenk #define HSSR0_TUR 0x00000002 /* Transmit FIFO Under-Run */ 824*3b58acd4Swdenk #define HSSR0_RAB 0x00000004 /* Receive ABort */ 825*3b58acd4Swdenk #define HSSR0_TFS 0x00000008 /* Transmit FIFO 1/2-full or less */ 826*3b58acd4Swdenk /* Service request (read) */ 827*3b58acd4Swdenk #define HSSR0_RFS 0x00000010 /* Receive FIFO 2/5-to-3/5-full or */ 828*3b58acd4Swdenk /* more Service request (read) */ 829*3b58acd4Swdenk #define HSSR0_FRE 0x00000020 /* receive FRaming Error */ 830*3b58acd4Swdenk 831*3b58acd4Swdenk #define HSSR1_RSY 0x00000001 /* Receiver SYnchronized (read) */ 832*3b58acd4Swdenk #define HSSR1_TBY 0x00000002 /* Transmitter BusY (read) */ 833*3b58acd4Swdenk #define HSSR1_RNE 0x00000004 /* Receive FIFO Not Empty (read) */ 834*3b58acd4Swdenk #define HSSR1_TNF 0x00000008 /* Transmit FIFO Not Full (read) */ 835*3b58acd4Swdenk #define HSSR1_EOF 0x00000010 /* receive End-Of-Frame (read) */ 836*3b58acd4Swdenk #define HSSR1_CRE 0x00000020 /* receive CRC Error (read) */ 837*3b58acd4Swdenk #define HSSR1_ROR 0x00000040 /* Receive FIFO Over-Run (read) */ 838*3b58acd4Swdenk 839*3b58acd4Swdenk #define HSCR2_TXP 0x00040000 /* Transmit data Polarity (TXD_2) */ 840*3b58acd4Swdenk #define HSCR2_TrDataL (HSCR2_TXP*0) /* Transmit Data active Low */ 841*3b58acd4Swdenk /* (inverted) */ 842*3b58acd4Swdenk #define HSCR2_TrDataH (HSCR2_TXP*1) /* Transmit Data active High */ 843*3b58acd4Swdenk /* (non-inverted) */ 844*3b58acd4Swdenk #define HSCR2_RXP 0x00080000 /* Receive data Polarity (RXD_2) */ 845*3b58acd4Swdenk #define HSCR2_RcDataL (HSCR2_RXP*0) /* Receive Data active Low */ 846*3b58acd4Swdenk /* (inverted) */ 847*3b58acd4Swdenk #define HSCR2_RcDataH (HSCR2_RXP*1) /* Receive Data active High */ 848*3b58acd4Swdenk /* (non-inverted) */ 849*3b58acd4Swdenk 850*3b58acd4Swdenk 851*3b58acd4Swdenk /* 852*3b58acd4Swdenk * Multi-media Communications Port (MCP) control registers 853*3b58acd4Swdenk * 854*3b58acd4Swdenk * Registers 855*3b58acd4Swdenk * Ser4MCCR0 Serial port 4 Multi-media Communications Port (MCP) 856*3b58acd4Swdenk * Control Register 0 (read/write). 857*3b58acd4Swdenk * Ser4MCDR0 Serial port 4 Multi-media Communications Port (MCP) 858*3b58acd4Swdenk * Data Register 0 (audio, read/write). 859*3b58acd4Swdenk * Ser4MCDR1 Serial port 4 Multi-media Communications Port (MCP) 860*3b58acd4Swdenk * Data Register 1 (telecom, read/write). 861*3b58acd4Swdenk * Ser4MCDR2 Serial port 4 Multi-media Communications Port (MCP) 862*3b58acd4Swdenk * Data Register 2 (CODEC registers, read/write). 863*3b58acd4Swdenk * Ser4MCSR Serial port 4 Multi-media Communications Port (MCP) 864*3b58acd4Swdenk * Status Register (read/write). 865*3b58acd4Swdenk * Ser4MCCR1 Serial port 4 Multi-media Communications Port (MCP) 866*3b58acd4Swdenk * Control Register 1 (read/write). 867*3b58acd4Swdenk * [The MCCR1 register is only implemented in 868*3b58acd4Swdenk * versions 2.0 (rev. = 8) and higher of the StrongARM 869*3b58acd4Swdenk * SA-1100.] 870*3b58acd4Swdenk * 871*3b58acd4Swdenk * Clocks 872*3b58acd4Swdenk * fmc, Tmc Frequency, period of the MCP communication (10 MHz, 873*3b58acd4Swdenk * 12 MHz, or GPIO [21]). 874*3b58acd4Swdenk * faud, Taud Frequency, period of the audio sampling. 875*3b58acd4Swdenk * ftcm, Ttcm Frequency, period of the telecom sampling. 876*3b58acd4Swdenk */ 877*3b58acd4Swdenk 878*3b58acd4Swdenk #define _Ser4MCCR0 0x80060000 /* Ser. port 4 MCP Control Reg. 0 */ 879*3b58acd4Swdenk #define _Ser4MCDR0 0x80060008 /* Ser. port 4 MCP Data Reg. 0 */ 880*3b58acd4Swdenk /* (audio) */ 881*3b58acd4Swdenk #define _Ser4MCDR1 0x8006000C /* Ser. port 4 MCP Data Reg. 1 */ 882*3b58acd4Swdenk /* (telecom) */ 883*3b58acd4Swdenk #define _Ser4MCDR2 0x80060010 /* Ser. port 4 MCP Data Reg. 2 */ 884*3b58acd4Swdenk /* (CODEC reg.) */ 885*3b58acd4Swdenk #define _Ser4MCSR 0x80060018 /* Ser. port 4 MCP Status Reg. */ 886*3b58acd4Swdenk #define _Ser4MCCR1 0x90060030 /* Ser. port 4 MCP Control Reg. 1 */ 887*3b58acd4Swdenk 888*3b58acd4Swdenk #if LANGUAGE == C 889*3b58acd4Swdenk #define Ser4MCCR0 /* Ser. port 4 MCP Control Reg. 0 */ \ 890*3b58acd4Swdenk (*((volatile Word *) io_p2v (_Ser4MCCR0))) 891*3b58acd4Swdenk #define Ser4MCDR0 /* Ser. port 4 MCP Data Reg. 0 */ \ 892*3b58acd4Swdenk /* (audio) */ \ 893*3b58acd4Swdenk (*((volatile Word *) io_p2v (_Ser4MCDR0))) 894*3b58acd4Swdenk #define Ser4MCDR1 /* Ser. port 4 MCP Data Reg. 1 */ \ 895*3b58acd4Swdenk /* (telecom) */ \ 896*3b58acd4Swdenk (*((volatile Word *) io_p2v (_Ser4MCDR1))) 897*3b58acd4Swdenk #define Ser4MCDR2 /* Ser. port 4 MCP Data Reg. 2 */ \ 898*3b58acd4Swdenk /* (CODEC reg.) */ \ 899*3b58acd4Swdenk (*((volatile Word *) io_p2v (_Ser4MCDR2))) 900*3b58acd4Swdenk #define Ser4MCSR /* Ser. port 4 MCP Status Reg. */ \ 901*3b58acd4Swdenk (*((volatile Word *) io_p2v (_Ser4MCSR))) 902*3b58acd4Swdenk #define Ser4MCCR1 /* Ser. port 4 MCP Control Reg. 1 */ \ 903*3b58acd4Swdenk (*((volatile Word *) io_p2v (_Ser4MCCR1))) 904*3b58acd4Swdenk #endif /* LANGUAGE == C */ 905*3b58acd4Swdenk 906*3b58acd4Swdenk #define MCCR0_ASD Fld (7, 0) /* Audio Sampling rate Divisor/32 */ 907*3b58acd4Swdenk /* [6..127] */ 908*3b58acd4Swdenk /* faud = fmc/(32*ASD) */ 909*3b58acd4Swdenk /* Taud = 32*ASD*Tmc */ 910*3b58acd4Swdenk #define MCCR0_AudSmpDiv(Div) /* Audio Sampling rate Divisor */ \ 911*3b58acd4Swdenk /* [192..4064] */ \ 912*3b58acd4Swdenk ((Div)/32 << FShft (MCCR0_ASD)) 913*3b58acd4Swdenk /* faud = fmc/(32*Floor (Div/32)) */ 914*3b58acd4Swdenk /* Taud = 32*Floor (Div/32)*Tmc */ 915*3b58acd4Swdenk #define MCCR0_CeilAudSmpDiv(Div) /* Ceil. of AudSmpDiv [192..4064] */ \ 916*3b58acd4Swdenk (((Div) + 31)/32 << FShft (MCCR0_ASD)) 917*3b58acd4Swdenk /* faud = fmc/(32*Ceil (Div/32)) */ 918*3b58acd4Swdenk /* Taud = 32*Ceil (Div/32)*Tmc */ 919*3b58acd4Swdenk #define MCCR0_TSD Fld (7, 8) /* Telecom Sampling rate */ 920*3b58acd4Swdenk /* Divisor/32 [16..127] */ 921*3b58acd4Swdenk /* ftcm = fmc/(32*TSD) */ 922*3b58acd4Swdenk /* Ttcm = 32*TSD*Tmc */ 923*3b58acd4Swdenk #define MCCR0_TcmSmpDiv(Div) /* Telecom Sampling rate Divisor */ \ 924*3b58acd4Swdenk /* [512..4064] */ \ 925*3b58acd4Swdenk ((Div)/32 << FShft (MCCR0_TSD)) 926*3b58acd4Swdenk /* ftcm = fmc/(32*Floor (Div/32)) */ 927*3b58acd4Swdenk /* Ttcm = 32*Floor (Div/32)*Tmc */ 928*3b58acd4Swdenk #define MCCR0_CeilTcmSmpDiv(Div) /* Ceil. of TcmSmpDiv [512..4064] */ \ 929*3b58acd4Swdenk (((Div) + 31)/32 << FShft (MCCR0_TSD)) 930*3b58acd4Swdenk /* ftcm = fmc/(32*Ceil (Div/32)) */ 931*3b58acd4Swdenk /* Ttcm = 32*Ceil (Div/32)*Tmc */ 932*3b58acd4Swdenk #define MCCR0_MCE 0x00010000 /* MCP Enable */ 933*3b58acd4Swdenk #define MCCR0_ECS 0x00020000 /* External Clock Select */ 934*3b58acd4Swdenk #define MCCR0_IntClk (MCCR0_ECS*0) /* Internal Clock (10 or 12 MHz) */ 935*3b58acd4Swdenk #define MCCR0_ExtClk (MCCR0_ECS*1) /* External Clock (GPIO [21]) */ 936*3b58acd4Swdenk #define MCCR0_ADM 0x00040000 /* A/D (audio/telecom) data */ 937*3b58acd4Swdenk /* sampling/storing Mode */ 938*3b58acd4Swdenk #define MCCR0_VldBit (MCCR0_ADM*0) /* Valid Bit storing mode */ 939*3b58acd4Swdenk #define MCCR0_SmpCnt (MCCR0_ADM*1) /* Sampling Counter storing mode */ 940*3b58acd4Swdenk #define MCCR0_TTE 0x00080000 /* Telecom Transmit FIFO 1/2-full */ 941*3b58acd4Swdenk /* or less interrupt Enable */ 942*3b58acd4Swdenk #define MCCR0_TRE 0x00100000 /* Telecom Receive FIFO 1/2-full */ 943*3b58acd4Swdenk /* or more interrupt Enable */ 944*3b58acd4Swdenk #define MCCR0_ATE 0x00200000 /* Audio Transmit FIFO 1/2-full */ 945*3b58acd4Swdenk /* or less interrupt Enable */ 946*3b58acd4Swdenk #define MCCR0_ARE 0x00400000 /* Audio Receive FIFO 1/2-full or */ 947*3b58acd4Swdenk /* more interrupt Enable */ 948*3b58acd4Swdenk #define MCCR0_LBM 0x00800000 /* Look-Back Mode */ 949*3b58acd4Swdenk #define MCCR0_ECP Fld (2, 24) /* External Clock Prescaler - 1 */ 950*3b58acd4Swdenk #define MCCR0_ExtClkDiv(Div) /* External Clock Divisor [1..4] */ \ 951*3b58acd4Swdenk (((Div) - 1) << FShft (MCCR0_ECP)) 952*3b58acd4Swdenk 953*3b58acd4Swdenk #define MCDR0_DATA Fld (12, 4) /* receive/transmit audio DATA */ 954*3b58acd4Swdenk /* FIFOs */ 955*3b58acd4Swdenk 956*3b58acd4Swdenk #define MCDR1_DATA Fld (14, 2) /* receive/transmit telecom DATA */ 957*3b58acd4Swdenk /* FIFOs */ 958*3b58acd4Swdenk 959*3b58acd4Swdenk /* receive/transmit CODEC reg. */ 960*3b58acd4Swdenk /* FIFOs: */ 961*3b58acd4Swdenk #define MCDR2_DATA Fld (16, 0) /* reg. DATA */ 962*3b58acd4Swdenk #define MCDR2_RW 0x00010000 /* reg. Read/Write (transmit) */ 963*3b58acd4Swdenk #define MCDR2_Rd (MCDR2_RW*0) /* reg. Read */ 964*3b58acd4Swdenk #define MCDR2_Wr (MCDR2_RW*1) /* reg. Write */ 965*3b58acd4Swdenk #define MCDR2_ADD Fld (4, 17) /* reg. ADDress */ 966*3b58acd4Swdenk 967*3b58acd4Swdenk #define MCSR_ATS 0x00000001 /* Audio Transmit FIFO 1/2-full */ 968*3b58acd4Swdenk /* or less Service request (read) */ 969*3b58acd4Swdenk #define MCSR_ARS 0x00000002 /* Audio Receive FIFO 1/2-full or */ 970*3b58acd4Swdenk /* more Service request (read) */ 971*3b58acd4Swdenk #define MCSR_TTS 0x00000004 /* Telecom Transmit FIFO 1/2-full */ 972*3b58acd4Swdenk /* or less Service request (read) */ 973*3b58acd4Swdenk #define MCSR_TRS 0x00000008 /* Telecom Receive FIFO 1/2-full */ 974*3b58acd4Swdenk /* or more Service request (read) */ 975*3b58acd4Swdenk #define MCSR_ATU 0x00000010 /* Audio Transmit FIFO Under-run */ 976*3b58acd4Swdenk #define MCSR_ARO 0x00000020 /* Audio Receive FIFO Over-run */ 977*3b58acd4Swdenk #define MCSR_TTU 0x00000040 /* Telecom Transmit FIFO Under-run */ 978*3b58acd4Swdenk #define MCSR_TRO 0x00000080 /* Telecom Receive FIFO Over-run */ 979*3b58acd4Swdenk #define MCSR_ANF 0x00000100 /* Audio transmit FIFO Not Full */ 980*3b58acd4Swdenk /* (read) */ 981*3b58acd4Swdenk #define MCSR_ANE 0x00000200 /* Audio receive FIFO Not Empty */ 982*3b58acd4Swdenk /* (read) */ 983*3b58acd4Swdenk #define MCSR_TNF 0x00000400 /* Telecom transmit FIFO Not Full */ 984*3b58acd4Swdenk /* (read) */ 985*3b58acd4Swdenk #define MCSR_TNE 0x00000800 /* Telecom receive FIFO Not Empty */ 986*3b58acd4Swdenk /* (read) */ 987*3b58acd4Swdenk #define MCSR_CWC 0x00001000 /* CODEC register Write Completed */ 988*3b58acd4Swdenk /* (read) */ 989*3b58acd4Swdenk #define MCSR_CRC 0x00002000 /* CODEC register Read Completed */ 990*3b58acd4Swdenk /* (read) */ 991*3b58acd4Swdenk #define MCSR_ACE 0x00004000 /* Audio CODEC Enabled (read) */ 992*3b58acd4Swdenk #define MCSR_TCE 0x00008000 /* Telecom CODEC Enabled (read) */ 993*3b58acd4Swdenk 994*3b58acd4Swdenk #define MCCR1_CFS 0x00100000 /* Clock Freq. Select */ 995*3b58acd4Swdenk #define MCCR1_F12MHz (MCCR1_CFS*0) /* Freq. (fmc) = ~ 12 MHz */ 996*3b58acd4Swdenk /* (11.981 MHz) */ 997*3b58acd4Swdenk #define MCCR1_F10MHz (MCCR1_CFS*1) /* Freq. (fmc) = ~ 10 MHz */ 998*3b58acd4Swdenk /* (9.585 MHz) */ 999*3b58acd4Swdenk 1000*3b58acd4Swdenk 1001*3b58acd4Swdenk /* 1002*3b58acd4Swdenk * Synchronous Serial Port (SSP) control registers 1003*3b58acd4Swdenk * 1004*3b58acd4Swdenk * Registers 1005*3b58acd4Swdenk * Ser4SSCR0 Serial port 4 Synchronous Serial Port (SSP) Control 1006*3b58acd4Swdenk * Register 0 (read/write). 1007*3b58acd4Swdenk * Ser4SSCR1 Serial port 4 Synchronous Serial Port (SSP) Control 1008*3b58acd4Swdenk * Register 1 (read/write). 1009*3b58acd4Swdenk * [Bits SPO and SP are only implemented in versions 2.0 1010*3b58acd4Swdenk * (rev. = 8) and higher of the StrongARM SA-1100.] 1011*3b58acd4Swdenk * Ser4SSDR Serial port 4 Synchronous Serial Port (SSP) Data 1012*3b58acd4Swdenk * Register (read/write). 1013*3b58acd4Swdenk * Ser4SSSR Serial port 4 Synchronous Serial Port (SSP) Status 1014*3b58acd4Swdenk * Register (read/write). 1015*3b58acd4Swdenk * 1016*3b58acd4Swdenk * Clocks 1017*3b58acd4Swdenk * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz 1018*3b58acd4Swdenk * or 3.5795 MHz). 1019*3b58acd4Swdenk * fss, Tss Frequency, period of the SSP communication. 1020*3b58acd4Swdenk */ 1021*3b58acd4Swdenk 1022*3b58acd4Swdenk #define _Ser4SSCR0 0x80070060 /* Ser. port 4 SSP Control Reg. 0 */ 1023*3b58acd4Swdenk #define _Ser4SSCR1 0x80070064 /* Ser. port 4 SSP Control Reg. 1 */ 1024*3b58acd4Swdenk #define _Ser4SSDR 0x8007006C /* Ser. port 4 SSP Data Reg. */ 1025*3b58acd4Swdenk #define _Ser4SSSR 0x80070074 /* Ser. port 4 SSP Status Reg. */ 1026*3b58acd4Swdenk 1027*3b58acd4Swdenk #if LANGUAGE == C 1028*3b58acd4Swdenk #define Ser4SSCR0 /* Ser. port 4 SSP Control Reg. 0 */ \ 1029*3b58acd4Swdenk (*((volatile Word *) io_p2v (_Ser4SSCR0))) 1030*3b58acd4Swdenk #define Ser4SSCR1 /* Ser. port 4 SSP Control Reg. 1 */ \ 1031*3b58acd4Swdenk (*((volatile Word *) io_p2v (_Ser4SSCR1))) 1032*3b58acd4Swdenk #define Ser4SSDR /* Ser. port 4 SSP Data Reg. */ \ 1033*3b58acd4Swdenk (*((volatile Word *) io_p2v (_Ser4SSDR))) 1034*3b58acd4Swdenk #define Ser4SSSR /* Ser. port 4 SSP Status Reg. */ \ 1035*3b58acd4Swdenk (*((volatile Word *) io_p2v (_Ser4SSSR))) 1036*3b58acd4Swdenk #endif /* LANGUAGE == C */ 1037*3b58acd4Swdenk 1038*3b58acd4Swdenk #define SSCR0_DSS Fld (4, 0) /* Data Size - 1 Select [3..15] */ 1039*3b58acd4Swdenk #define SSCR0_DataSize(Size) /* Data Size Select [4..16] */ \ 1040*3b58acd4Swdenk (((Size) - 1) << FShft (SSCR0_DSS)) 1041*3b58acd4Swdenk #define SSCR0_FRF Fld (2, 4) /* FRame Format */ 1042*3b58acd4Swdenk #define SSCR0_Motorola /* Motorola Serial Peripheral */ \ 1043*3b58acd4Swdenk /* Interface (SPI) format */ \ 1044*3b58acd4Swdenk (0 << FShft (SSCR0_FRF)) 1045*3b58acd4Swdenk #define SSCR0_TI /* Texas Instruments Synchronous */ \ 1046*3b58acd4Swdenk /* Serial format */ \ 1047*3b58acd4Swdenk (1 << FShft (SSCR0_FRF)) 1048*3b58acd4Swdenk #define SSCR0_National /* National Microwire format */ \ 1049*3b58acd4Swdenk (2 << FShft (SSCR0_FRF)) 1050*3b58acd4Swdenk #define SSCR0_SSE 0x00000080 /* SSP Enable */ 1051*3b58acd4Swdenk #define SSCR0_SCR Fld (8, 8) /* Serial Clock Rate divisor/2 - 1 */ 1052*3b58acd4Swdenk /* fss = fxtl/(2*(SCR + 1)) */ 1053*3b58acd4Swdenk /* Tss = 2*(SCR + 1)*Txtl */ 1054*3b58acd4Swdenk #define SSCR0_SerClkDiv(Div) /* Serial Clock Divisor [2..512] */ \ 1055*3b58acd4Swdenk (((Div) - 2)/2 << FShft (SSCR0_SCR)) 1056*3b58acd4Swdenk /* fss = fxtl/(2*Floor (Div/2)) */ 1057*3b58acd4Swdenk /* Tss = 2*Floor (Div/2)*Txtl */ 1058*3b58acd4Swdenk #define SSCR0_CeilSerClkDiv(Div) /* Ceil. of SerClkDiv [2..512] */ \ 1059*3b58acd4Swdenk (((Div) - 1)/2 << FShft (SSCR0_SCR)) 1060*3b58acd4Swdenk /* fss = fxtl/(2*Ceil (Div/2)) */ 1061*3b58acd4Swdenk /* Tss = 2*Ceil (Div/2)*Txtl */ 1062*3b58acd4Swdenk 1063*3b58acd4Swdenk #define SSCR1_RIE 0x00000001 /* Receive FIFO 1/2-full or more */ 1064*3b58acd4Swdenk /* Interrupt Enable */ 1065*3b58acd4Swdenk #define SSCR1_TIE 0x00000002 /* Transmit FIFO 1/2-full or less */ 1066*3b58acd4Swdenk /* Interrupt Enable */ 1067*3b58acd4Swdenk #define SSCR1_LBM 0x00000004 /* Look-Back Mode */ 1068*3b58acd4Swdenk #define SSCR1_SPO 0x00000008 /* Sample clock (SCLK) POlarity */ 1069*3b58acd4Swdenk #define SSCR1_SClkIactL (SSCR1_SPO*0) /* Sample Clock Inactive Low */ 1070*3b58acd4Swdenk #define SSCR1_SClkIactH (SSCR1_SPO*1) /* Sample Clock Inactive High */ 1071*3b58acd4Swdenk #define SSCR1_SP 0x00000010 /* Sample clock (SCLK) Phase */ 1072*3b58acd4Swdenk #define SSCR1_SClk1P (SSCR1_SP*0) /* Sample Clock active 1 Period */ 1073*3b58acd4Swdenk /* after frame (SFRM, 1st edge) */ 1074*3b58acd4Swdenk #define SSCR1_SClk1_2P (SSCR1_SP*1) /* Sample Clock active 1/2 Period */ 1075*3b58acd4Swdenk /* after frame (SFRM, 1st edge) */ 1076*3b58acd4Swdenk #define SSCR1_ECS 0x00000020 /* External Clock Select */ 1077*3b58acd4Swdenk #define SSCR1_IntClk (SSCR1_ECS*0) /* Internal Clock */ 1078*3b58acd4Swdenk #define SSCR1_ExtClk (SSCR1_ECS*1) /* External Clock (GPIO [19]) */ 1079*3b58acd4Swdenk 1080*3b58acd4Swdenk #define SSDR_DATA Fld (16, 0) /* receive/transmit DATA FIFOs */ 1081*3b58acd4Swdenk 1082*3b58acd4Swdenk #define SSSR_TNF 0x00000002 /* Transmit FIFO Not Full (read) */ 1083*3b58acd4Swdenk #define SSSR_RNE 0x00000004 /* Receive FIFO Not Empty (read) */ 1084*3b58acd4Swdenk #define SSSR_BSY 0x00000008 /* SSP BuSY (read) */ 1085*3b58acd4Swdenk #define SSSR_TFS 0x00000010 /* Transmit FIFO 1/2-full or less */ 1086*3b58acd4Swdenk /* Service request (read) */ 1087*3b58acd4Swdenk #define SSSR_RFS 0x00000020 /* Receive FIFO 1/2-full or more */ 1088*3b58acd4Swdenk /* Service request (read) */ 1089*3b58acd4Swdenk #define SSSR_ROR 0x00000040 /* Receive FIFO Over-Run */ 1090*3b58acd4Swdenk 1091*3b58acd4Swdenk 1092*3b58acd4Swdenk /* 1093*3b58acd4Swdenk * Operating System (OS) timer control registers 1094*3b58acd4Swdenk * 1095*3b58acd4Swdenk * Registers 1096*3b58acd4Swdenk * OSMR0 Operating System (OS) timer Match Register 0 1097*3b58acd4Swdenk * (read/write). 1098*3b58acd4Swdenk * OSMR1 Operating System (OS) timer Match Register 1 1099*3b58acd4Swdenk * (read/write). 1100*3b58acd4Swdenk * OSMR2 Operating System (OS) timer Match Register 2 1101*3b58acd4Swdenk * (read/write). 1102*3b58acd4Swdenk * OSMR3 Operating System (OS) timer Match Register 3 1103*3b58acd4Swdenk * (read/write). 1104*3b58acd4Swdenk * OSCR Operating System (OS) timer Counter Register 1105*3b58acd4Swdenk * (read/write). 1106*3b58acd4Swdenk * OSSR Operating System (OS) timer Status Register 1107*3b58acd4Swdenk * (read/write). 1108*3b58acd4Swdenk * OWER Operating System (OS) timer Watch-dog Enable Register 1109*3b58acd4Swdenk * (read/write). 1110*3b58acd4Swdenk * OIER Operating System (OS) timer Interrupt Enable Register 1111*3b58acd4Swdenk * (read/write). 1112*3b58acd4Swdenk */ 1113*3b58acd4Swdenk 1114*3b58acd4Swdenk #define _OSMR(Nb) /* OS timer Match Reg. [0..3] */ \ 1115*3b58acd4Swdenk (0x90000000 + (Nb)*4) 1116*3b58acd4Swdenk #define _OSMR0 _OSMR (0) /* OS timer Match Reg. 0 */ 1117*3b58acd4Swdenk #define _OSMR1 _OSMR (1) /* OS timer Match Reg. 1 */ 1118*3b58acd4Swdenk #define _OSMR2 _OSMR (2) /* OS timer Match Reg. 2 */ 1119*3b58acd4Swdenk #define _OSMR3 _OSMR (3) /* OS timer Match Reg. 3 */ 1120*3b58acd4Swdenk #define _OSCR 0x90000010 /* OS timer Counter Reg. */ 1121*3b58acd4Swdenk #define _OSSR 0x90000014 /* OS timer Status Reg. */ 1122*3b58acd4Swdenk #define _OWER 0x90000018 /* OS timer Watch-dog Enable Reg. */ 1123*3b58acd4Swdenk #define _OIER 0x9000001C /* OS timer Interrupt Enable Reg. */ 1124*3b58acd4Swdenk 1125*3b58acd4Swdenk #if LANGUAGE == C 1126*3b58acd4Swdenk #define OSMR /* OS timer Match Reg. [0..3] */ \ 1127*3b58acd4Swdenk ((volatile Word *) io_p2v (_OSMR (0))) 1128*3b58acd4Swdenk #define OSMR0 (OSMR [0]) /* OS timer Match Reg. 0 */ 1129*3b58acd4Swdenk #define OSMR1 (OSMR [1]) /* OS timer Match Reg. 1 */ 1130*3b58acd4Swdenk #define OSMR2 (OSMR [2]) /* OS timer Match Reg. 2 */ 1131*3b58acd4Swdenk #define OSMR3 (OSMR [3]) /* OS timer Match Reg. 3 */ 1132*3b58acd4Swdenk #define OSCR /* OS timer Counter Reg. */ \ 1133*3b58acd4Swdenk (*((volatile Word *) io_p2v (_OSCR))) 1134*3b58acd4Swdenk #define OSSR /* OS timer Status Reg. */ \ 1135*3b58acd4Swdenk (*((volatile Word *) io_p2v (_OSSR))) 1136*3b58acd4Swdenk #define OWER /* OS timer Watch-dog Enable Reg. */ \ 1137*3b58acd4Swdenk (*((volatile Word *) io_p2v (_OWER))) 1138*3b58acd4Swdenk #define OIER /* OS timer Interrupt Enable Reg. */ \ 1139*3b58acd4Swdenk (*((volatile Word *) io_p2v (_OIER))) 1140*3b58acd4Swdenk #endif /* LANGUAGE == C */ 1141*3b58acd4Swdenk 1142*3b58acd4Swdenk #define OSSR_M(Nb) /* Match detected [0..3] */ \ 1143*3b58acd4Swdenk (0x00000001 << (Nb)) 1144*3b58acd4Swdenk #define OSSR_M0 OSSR_M (0) /* Match detected 0 */ 1145*3b58acd4Swdenk #define OSSR_M1 OSSR_M (1) /* Match detected 1 */ 1146*3b58acd4Swdenk #define OSSR_M2 OSSR_M (2) /* Match detected 2 */ 1147*3b58acd4Swdenk #define OSSR_M3 OSSR_M (3) /* Match detected 3 */ 1148*3b58acd4Swdenk 1149*3b58acd4Swdenk #define OWER_WME 0x00000001 /* Watch-dog Match Enable */ 1150*3b58acd4Swdenk /* (set only) */ 1151*3b58acd4Swdenk 1152*3b58acd4Swdenk #define OIER_E(Nb) /* match interrupt Enable [0..3] */ \ 1153*3b58acd4Swdenk (0x00000001 << (Nb)) 1154*3b58acd4Swdenk #define OIER_E0 OIER_E (0) /* match interrupt Enable 0 */ 1155*3b58acd4Swdenk #define OIER_E1 OIER_E (1) /* match interrupt Enable 1 */ 1156*3b58acd4Swdenk #define OIER_E2 OIER_E (2) /* match interrupt Enable 2 */ 1157*3b58acd4Swdenk #define OIER_E3 OIER_E (3) /* match interrupt Enable 3 */ 1158*3b58acd4Swdenk 1159*3b58acd4Swdenk 1160*3b58acd4Swdenk /* 1161*3b58acd4Swdenk * Real-Time Clock (RTC) control registers 1162*3b58acd4Swdenk * 1163*3b58acd4Swdenk * Registers 1164*3b58acd4Swdenk * RTAR Real-Time Clock (RTC) Alarm Register (read/write). 1165*3b58acd4Swdenk * RCNR Real-Time Clock (RTC) CouNt Register (read/write). 1166*3b58acd4Swdenk * RTTR Real-Time Clock (RTC) Trim Register (read/write). 1167*3b58acd4Swdenk * RTSR Real-Time Clock (RTC) Status Register (read/write). 1168*3b58acd4Swdenk * 1169*3b58acd4Swdenk * Clocks 1170*3b58acd4Swdenk * frtx, Trtx Frequency, period of the real-time clock crystal 1171*3b58acd4Swdenk * (32.768 kHz nominal). 1172*3b58acd4Swdenk * frtc, Trtc Frequency, period of the real-time clock counter 1173*3b58acd4Swdenk * (1 Hz nominal). 1174*3b58acd4Swdenk */ 1175*3b58acd4Swdenk 1176*3b58acd4Swdenk #define _RTAR 0x90010000 /* RTC Alarm Reg. */ 1177*3b58acd4Swdenk #define _RCNR 0x90010004 /* RTC CouNt Reg. */ 1178*3b58acd4Swdenk #define _RTTR 0x90010008 /* RTC Trim Reg. */ 1179*3b58acd4Swdenk #define _RTSR 0x90010010 /* RTC Status Reg. */ 1180*3b58acd4Swdenk 1181*3b58acd4Swdenk #if LANGUAGE == C 1182*3b58acd4Swdenk #define RTAR /* RTC Alarm Reg. */ \ 1183*3b58acd4Swdenk (*((volatile Word *) io_p2v (_RTAR))) 1184*3b58acd4Swdenk #define RCNR /* RTC CouNt Reg. */ \ 1185*3b58acd4Swdenk (*((volatile Word *) io_p2v (_RCNR))) 1186*3b58acd4Swdenk #define RTTR /* RTC Trim Reg. */ \ 1187*3b58acd4Swdenk (*((volatile Word *) io_p2v (_RTTR))) 1188*3b58acd4Swdenk #define RTSR /* RTC Status Reg. */ \ 1189*3b58acd4Swdenk (*((volatile Word *) io_p2v (_RTSR))) 1190*3b58acd4Swdenk #endif /* LANGUAGE == C */ 1191*3b58acd4Swdenk 1192*3b58acd4Swdenk #define RTTR_C Fld (16, 0) /* clock divider Count - 1 */ 1193*3b58acd4Swdenk #define RTTR_D Fld (10, 16) /* trim Delete count */ 1194*3b58acd4Swdenk /* frtc = (1023*(C + 1) - D)*frtx/ */ 1195*3b58acd4Swdenk /* (1023*(C + 1)^2) */ 1196*3b58acd4Swdenk /* Trtc = (1023*(C + 1)^2)*Trtx/ */ 1197*3b58acd4Swdenk /* (1023*(C + 1) - D) */ 1198*3b58acd4Swdenk 1199*3b58acd4Swdenk #define RTSR_AL 0x00000001 /* ALarm detected */ 1200*3b58acd4Swdenk #define RTSR_HZ 0x00000002 /* 1 Hz clock detected */ 1201*3b58acd4Swdenk #define RTSR_ALE 0x00000004 /* ALarm interrupt Enable */ 1202*3b58acd4Swdenk #define RTSR_HZE 0x00000008 /* 1 Hz clock interrupt Enable */ 1203*3b58acd4Swdenk 1204*3b58acd4Swdenk 1205*3b58acd4Swdenk /* 1206*3b58acd4Swdenk * Power Manager (PM) control registers 1207*3b58acd4Swdenk * 1208*3b58acd4Swdenk * Registers 1209*3b58acd4Swdenk * PMCR Power Manager (PM) Control Register (read/write). 1210*3b58acd4Swdenk * PSSR Power Manager (PM) Sleep Status Register (read/write). 1211*3b58acd4Swdenk * PSPR Power Manager (PM) Scratch-Pad Register (read/write). 1212*3b58acd4Swdenk * PWER Power Manager (PM) Wake-up Enable Register 1213*3b58acd4Swdenk * (read/write). 1214*3b58acd4Swdenk * PCFR Power Manager (PM) general ConFiguration Register 1215*3b58acd4Swdenk * (read/write). 1216*3b58acd4Swdenk * PPCR Power Manager (PM) Phase-Locked Loop (PLL) 1217*3b58acd4Swdenk * Configuration Register (read/write). 1218*3b58acd4Swdenk * PGSR Power Manager (PM) General-Purpose Input/Output (GPIO) 1219*3b58acd4Swdenk * Sleep state Register (read/write, see GPIO pins). 1220*3b58acd4Swdenk * POSR Power Manager (PM) Oscillator Status Register (read). 1221*3b58acd4Swdenk * 1222*3b58acd4Swdenk * Clocks 1223*3b58acd4Swdenk * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz 1224*3b58acd4Swdenk * or 3.5795 MHz). 1225*3b58acd4Swdenk * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). 1226*3b58acd4Swdenk */ 1227*3b58acd4Swdenk 1228*3b58acd4Swdenk #define _PMCR 0x90020000 /* PM Control Reg. */ 1229*3b58acd4Swdenk #define _PSSR 0x90020004 /* PM Sleep Status Reg. */ 1230*3b58acd4Swdenk #define _PSPR 0x90020008 /* PM Scratch-Pad Reg. */ 1231*3b58acd4Swdenk #define _PWER 0x9002000C /* PM Wake-up Enable Reg. */ 1232*3b58acd4Swdenk #define _PCFR 0x90020010 /* PM general ConFiguration Reg. */ 1233*3b58acd4Swdenk #define _PPCR 0x90020014 /* PM PLL Configuration Reg. */ 1234*3b58acd4Swdenk #define _PGSR 0x90020018 /* PM GPIO Sleep state Reg. */ 1235*3b58acd4Swdenk #define _POSR 0x9002001C /* PM Oscillator Status Reg. */ 1236*3b58acd4Swdenk 1237*3b58acd4Swdenk #if LANGUAGE == C 1238*3b58acd4Swdenk #define PMCR /* PM Control Reg. */ \ 1239*3b58acd4Swdenk (*((volatile Word *) io_p2v (_PMCR))) 1240*3b58acd4Swdenk #define PSSR /* PM Sleep Status Reg. */ \ 1241*3b58acd4Swdenk (*((volatile Word *) io_p2v (_PSSR))) 1242*3b58acd4Swdenk #define PSPR /* PM Scratch-Pad Reg. */ \ 1243*3b58acd4Swdenk (*((volatile Word *) io_p2v (_PSPR))) 1244*3b58acd4Swdenk #define PWER /* PM Wake-up Enable Reg. */ \ 1245*3b58acd4Swdenk (*((volatile Word *) io_p2v (_PWER))) 1246*3b58acd4Swdenk #define PCFR /* PM general ConFiguration Reg. */ \ 1247*3b58acd4Swdenk (*((volatile Word *) io_p2v (_PCFR))) 1248*3b58acd4Swdenk #define PPCR /* PM PLL Configuration Reg. */ \ 1249*3b58acd4Swdenk (*((volatile Word *) io_p2v (_PPCR))) 1250*3b58acd4Swdenk #define PGSR /* PM GPIO Sleep state Reg. */ \ 1251*3b58acd4Swdenk (*((volatile Word *) io_p2v (_PGSR))) 1252*3b58acd4Swdenk #define POSR /* PM Oscillator Status Reg. */ \ 1253*3b58acd4Swdenk (*((volatile Word *) io_p2v (_POSR))) 1254*3b58acd4Swdenk 1255*3b58acd4Swdenk #elif LANGUAGE == Assembly 1256*3b58acd4Swdenk #define PMCR (io_p2v (_PMCR)) 1257*3b58acd4Swdenk #define PSSR (io_p2v (_PSSR)) 1258*3b58acd4Swdenk #define PSPR (io_p2v (_PSPR)) 1259*3b58acd4Swdenk #define PWER (io_p2v (_PWER)) 1260*3b58acd4Swdenk #define PCFR (io_p2v (_PCFR)) 1261*3b58acd4Swdenk #define PPCR (io_p2v (_PPCR)) 1262*3b58acd4Swdenk #define PGSR (io_p2v (_PGSR)) 1263*3b58acd4Swdenk #define POSR (io_p2v (_POSR)) 1264*3b58acd4Swdenk 1265*3b58acd4Swdenk #endif /* LANGUAGE == C */ 1266*3b58acd4Swdenk 1267*3b58acd4Swdenk #define PMCR_SF 0x00000001 /* Sleep Force (set only) */ 1268*3b58acd4Swdenk 1269*3b58acd4Swdenk #define PSSR_SS 0x00000001 /* Software Sleep */ 1270*3b58acd4Swdenk #define PSSR_BFS 0x00000002 /* Battery Fault Status */ 1271*3b58acd4Swdenk /* (BATT_FAULT) */ 1272*3b58acd4Swdenk #define PSSR_VFS 0x00000004 /* Vdd Fault Status (VDD_FAULT) */ 1273*3b58acd4Swdenk #define PSSR_DH 0x00000008 /* DRAM control Hold */ 1274*3b58acd4Swdenk #define PSSR_PH 0x00000010 /* Peripheral control Hold */ 1275*3b58acd4Swdenk 1276*3b58acd4Swdenk #define PWER_GPIO(Nb) GPIO_GPIO (Nb) /* GPIO [0..27] wake-up enable */ 1277*3b58acd4Swdenk #define PWER_GPIO0 PWER_GPIO (0) /* GPIO [0] wake-up enable */ 1278*3b58acd4Swdenk #define PWER_GPIO1 PWER_GPIO (1) /* GPIO [1] wake-up enable */ 1279*3b58acd4Swdenk #define PWER_GPIO2 PWER_GPIO (2) /* GPIO [2] wake-up enable */ 1280*3b58acd4Swdenk #define PWER_GPIO3 PWER_GPIO (3) /* GPIO [3] wake-up enable */ 1281*3b58acd4Swdenk #define PWER_GPIO4 PWER_GPIO (4) /* GPIO [4] wake-up enable */ 1282*3b58acd4Swdenk #define PWER_GPIO5 PWER_GPIO (5) /* GPIO [5] wake-up enable */ 1283*3b58acd4Swdenk #define PWER_GPIO6 PWER_GPIO (6) /* GPIO [6] wake-up enable */ 1284*3b58acd4Swdenk #define PWER_GPIO7 PWER_GPIO (7) /* GPIO [7] wake-up enable */ 1285*3b58acd4Swdenk #define PWER_GPIO8 PWER_GPIO (8) /* GPIO [8] wake-up enable */ 1286*3b58acd4Swdenk #define PWER_GPIO9 PWER_GPIO (9) /* GPIO [9] wake-up enable */ 1287*3b58acd4Swdenk #define PWER_GPIO10 PWER_GPIO (10) /* GPIO [10] wake-up enable */ 1288*3b58acd4Swdenk #define PWER_GPIO11 PWER_GPIO (11) /* GPIO [11] wake-up enable */ 1289*3b58acd4Swdenk #define PWER_GPIO12 PWER_GPIO (12) /* GPIO [12] wake-up enable */ 1290*3b58acd4Swdenk #define PWER_GPIO13 PWER_GPIO (13) /* GPIO [13] wake-up enable */ 1291*3b58acd4Swdenk #define PWER_GPIO14 PWER_GPIO (14) /* GPIO [14] wake-up enable */ 1292*3b58acd4Swdenk #define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */ 1293*3b58acd4Swdenk #define PWER_GPIO16 PWER_GPIO (16) /* GPIO [16] wake-up enable */ 1294*3b58acd4Swdenk #define PWER_GPIO17 PWER_GPIO (17) /* GPIO [17] wake-up enable */ 1295*3b58acd4Swdenk #define PWER_GPIO18 PWER_GPIO (18) /* GPIO [18] wake-up enable */ 1296*3b58acd4Swdenk #define PWER_GPIO19 PWER_GPIO (19) /* GPIO [19] wake-up enable */ 1297*3b58acd4Swdenk #define PWER_GPIO20 PWER_GPIO (20) /* GPIO [20] wake-up enable */ 1298*3b58acd4Swdenk #define PWER_GPIO21 PWER_GPIO (21) /* GPIO [21] wake-up enable */ 1299*3b58acd4Swdenk #define PWER_GPIO22 PWER_GPIO (22) /* GPIO [22] wake-up enable */ 1300*3b58acd4Swdenk #define PWER_GPIO23 PWER_GPIO (23) /* GPIO [23] wake-up enable */ 1301*3b58acd4Swdenk #define PWER_GPIO24 PWER_GPIO (24) /* GPIO [24] wake-up enable */ 1302*3b58acd4Swdenk #define PWER_GPIO25 PWER_GPIO (25) /* GPIO [25] wake-up enable */ 1303*3b58acd4Swdenk #define PWER_GPIO26 PWER_GPIO (26) /* GPIO [26] wake-up enable */ 1304*3b58acd4Swdenk #define PWER_GPIO27 PWER_GPIO (27) /* GPIO [27] wake-up enable */ 1305*3b58acd4Swdenk #define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */ 1306*3b58acd4Swdenk 1307*3b58acd4Swdenk #define PCFR_OPDE 0x00000001 /* Oscillator Power-Down Enable */ 1308*3b58acd4Swdenk #define PCFR_ClkRun (PCFR_OPDE*0) /* Clock Running in sleep mode */ 1309*3b58acd4Swdenk #define PCFR_ClkStp (PCFR_OPDE*1) /* Clock Stopped in sleep mode */ 1310*3b58acd4Swdenk #define PCFR_FP 0x00000002 /* Float PCMCIA pins */ 1311*3b58acd4Swdenk #define PCFR_PCMCIANeg (PCFR_FP*0) /* PCMCIA pins Negated (1) */ 1312*3b58acd4Swdenk #define PCFR_PCMCIAFlt (PCFR_FP*1) /* PCMCIA pins Floating */ 1313*3b58acd4Swdenk #define PCFR_FS 0x00000004 /* Float Static memory pins */ 1314*3b58acd4Swdenk #define PCFR_StMemNeg (PCFR_FS*0) /* Static Memory pins Negated (1) */ 1315*3b58acd4Swdenk #define PCFR_StMemFlt (PCFR_FS*1) /* Static Memory pins Floating */ 1316*3b58acd4Swdenk #define PCFR_FO 0x00000008 /* Force RTC oscillator */ 1317*3b58acd4Swdenk /* (32.768 kHz) enable On */ 1318*3b58acd4Swdenk 1319*3b58acd4Swdenk #define PPCR_CCF Fld (5, 0) /* CPU core Clock (CCLK) Freq. */ 1320*3b58acd4Swdenk #define PPCR_Fx16 /* Freq. x 16 (fcpu = 16*fxtl) */ \ 1321*3b58acd4Swdenk (0x00 << FShft (PPCR_CCF)) 1322*3b58acd4Swdenk #define PPCR_Fx20 /* Freq. x 20 (fcpu = 20*fxtl) */ \ 1323*3b58acd4Swdenk (0x01 << FShft (PPCR_CCF)) 1324*3b58acd4Swdenk #define PPCR_Fx24 /* Freq. x 24 (fcpu = 24*fxtl) */ \ 1325*3b58acd4Swdenk (0x02 << FShft (PPCR_CCF)) 1326*3b58acd4Swdenk #define PPCR_Fx28 /* Freq. x 28 (fcpu = 28*fxtl) */ \ 1327*3b58acd4Swdenk (0x03 << FShft (PPCR_CCF)) 1328*3b58acd4Swdenk #define PPCR_Fx32 /* Freq. x 32 (fcpu = 32*fxtl) */ \ 1329*3b58acd4Swdenk (0x04 << FShft (PPCR_CCF)) 1330*3b58acd4Swdenk #define PPCR_Fx36 /* Freq. x 36 (fcpu = 36*fxtl) */ \ 1331*3b58acd4Swdenk (0x05 << FShft (PPCR_CCF)) 1332*3b58acd4Swdenk #define PPCR_Fx40 /* Freq. x 40 (fcpu = 40*fxtl) */ \ 1333*3b58acd4Swdenk (0x06 << FShft (PPCR_CCF)) 1334*3b58acd4Swdenk #define PPCR_Fx44 /* Freq. x 44 (fcpu = 44*fxtl) */ \ 1335*3b58acd4Swdenk (0x07 << FShft (PPCR_CCF)) 1336*3b58acd4Swdenk #define PPCR_Fx48 /* Freq. x 48 (fcpu = 48*fxtl) */ \ 1337*3b58acd4Swdenk (0x08 << FShft (PPCR_CCF)) 1338*3b58acd4Swdenk #define PPCR_Fx52 /* Freq. x 52 (fcpu = 52*fxtl) */ \ 1339*3b58acd4Swdenk (0x09 << FShft (PPCR_CCF)) 1340*3b58acd4Swdenk #define PPCR_Fx56 /* Freq. x 56 (fcpu = 56*fxtl) */ \ 1341*3b58acd4Swdenk (0x0A << FShft (PPCR_CCF)) 1342*3b58acd4Swdenk #define PPCR_Fx60 /* Freq. x 60 (fcpu = 60*fxtl) */ \ 1343*3b58acd4Swdenk (0x0B << FShft (PPCR_CCF)) 1344*3b58acd4Swdenk #define PPCR_Fx64 /* Freq. x 64 (fcpu = 64*fxtl) */ \ 1345*3b58acd4Swdenk (0x0C << FShft (PPCR_CCF)) 1346*3b58acd4Swdenk #define PPCR_Fx68 /* Freq. x 68 (fcpu = 68*fxtl) */ \ 1347*3b58acd4Swdenk (0x0D << FShft (PPCR_CCF)) 1348*3b58acd4Swdenk #define PPCR_Fx72 /* Freq. x 72 (fcpu = 72*fxtl) */ \ 1349*3b58acd4Swdenk (0x0E << FShft (PPCR_CCF)) 1350*3b58acd4Swdenk #define PPCR_Fx76 /* Freq. x 76 (fcpu = 76*fxtl) */ \ 1351*3b58acd4Swdenk (0x0F << FShft (PPCR_CCF)) 1352*3b58acd4Swdenk /* 3.6864 MHz crystal (fxtl): */ 1353*3b58acd4Swdenk #define PPCR_F59_0MHz PPCR_Fx16 /* Freq. (fcpu) = 59.0 MHz */ 1354*3b58acd4Swdenk #define PPCR_F73_7MHz PPCR_Fx20 /* Freq. (fcpu) = 73.7 MHz */ 1355*3b58acd4Swdenk #define PPCR_F88_5MHz PPCR_Fx24 /* Freq. (fcpu) = 88.5 MHz */ 1356*3b58acd4Swdenk #define PPCR_F103_2MHz PPCR_Fx28 /* Freq. (fcpu) = 103.2 MHz */ 1357*3b58acd4Swdenk #define PPCR_F118_0MHz PPCR_Fx32 /* Freq. (fcpu) = 118.0 MHz */ 1358*3b58acd4Swdenk #define PPCR_F132_7MHz PPCR_Fx36 /* Freq. (fcpu) = 132.7 MHz */ 1359*3b58acd4Swdenk #define PPCR_F147_5MHz PPCR_Fx40 /* Freq. (fcpu) = 147.5 MHz */ 1360*3b58acd4Swdenk #define PPCR_F162_2MHz PPCR_Fx44 /* Freq. (fcpu) = 162.2 MHz */ 1361*3b58acd4Swdenk #define PPCR_F176_9MHz PPCR_Fx48 /* Freq. (fcpu) = 176.9 MHz */ 1362*3b58acd4Swdenk #define PPCR_F191_7MHz PPCR_Fx52 /* Freq. (fcpu) = 191.7 MHz */ 1363*3b58acd4Swdenk #define PPCR_F206_4MHz PPCR_Fx56 /* Freq. (fcpu) = 206.4 MHz */ 1364*3b58acd4Swdenk #define PPCR_F221_2MHz PPCR_Fx60 /* Freq. (fcpu) = 221.2 MHz */ 1365*3b58acd4Swdenk #define PPCR_F239_6MHz PPCR_Fx64 /* Freq. (fcpu) = 239.6 MHz */ 1366*3b58acd4Swdenk #define PPCR_F250_7MHz PPCR_Fx68 /* Freq. (fcpu) = 250.7 MHz */ 1367*3b58acd4Swdenk #define PPCR_F265_4MHz PPCR_Fx72 /* Freq. (fcpu) = 265.4 MHz */ 1368*3b58acd4Swdenk #define PPCR_F280_2MHz PPCR_Fx76 /* Freq. (fcpu) = 280.2 MHz */ 1369*3b58acd4Swdenk /* 3.5795 MHz crystal (fxtl): */ 1370*3b58acd4Swdenk #define PPCR_F57_3MHz PPCR_Fx16 /* Freq. (fcpu) = 57.3 MHz */ 1371*3b58acd4Swdenk #define PPCR_F71_6MHz PPCR_Fx20 /* Freq. (fcpu) = 71.6 MHz */ 1372*3b58acd4Swdenk #define PPCR_F85_9MHz PPCR_Fx24 /* Freq. (fcpu) = 85.9 MHz */ 1373*3b58acd4Swdenk #define PPCR_F100_2MHz PPCR_Fx28 /* Freq. (fcpu) = 100.2 MHz */ 1374*3b58acd4Swdenk #define PPCR_F114_5MHz PPCR_Fx32 /* Freq. (fcpu) = 114.5 MHz */ 1375*3b58acd4Swdenk #define PPCR_F128_9MHz PPCR_Fx36 /* Freq. (fcpu) = 128.9 MHz */ 1376*3b58acd4Swdenk #define PPCR_F143_2MHz PPCR_Fx40 /* Freq. (fcpu) = 143.2 MHz */ 1377*3b58acd4Swdenk #define PPCR_F157_5MHz PPCR_Fx44 /* Freq. (fcpu) = 157.5 MHz */ 1378*3b58acd4Swdenk #define PPCR_F171_8MHz PPCR_Fx48 /* Freq. (fcpu) = 171.8 MHz */ 1379*3b58acd4Swdenk #define PPCR_F186_1MHz PPCR_Fx52 /* Freq. (fcpu) = 186.1 MHz */ 1380*3b58acd4Swdenk #define PPCR_F200_5MHz PPCR_Fx56 /* Freq. (fcpu) = 200.5 MHz */ 1381*3b58acd4Swdenk #define PPCR_F214_8MHz PPCR_Fx60 /* Freq. (fcpu) = 214.8 MHz */ 1382*3b58acd4Swdenk #define PPCR_F229_1MHz PPCR_Fx64 /* Freq. (fcpu) = 229.1 MHz */ 1383*3b58acd4Swdenk #define PPCR_F243_4MHz PPCR_Fx68 /* Freq. (fcpu) = 243.4 MHz */ 1384*3b58acd4Swdenk #define PPCR_F257_7MHz PPCR_Fx72 /* Freq. (fcpu) = 257.7 MHz */ 1385*3b58acd4Swdenk #define PPCR_F272_0MHz PPCR_Fx76 /* Freq. (fcpu) = 272.0 MHz */ 1386*3b58acd4Swdenk 1387*3b58acd4Swdenk #define POSR_OOK 0x00000001 /* RTC Oscillator (32.768 kHz) OK */ 1388*3b58acd4Swdenk 1389*3b58acd4Swdenk 1390*3b58acd4Swdenk /* 1391*3b58acd4Swdenk * Reset Controller (RC) control registers 1392*3b58acd4Swdenk * 1393*3b58acd4Swdenk * Registers 1394*3b58acd4Swdenk * RSRR Reset Controller (RC) Software Reset Register 1395*3b58acd4Swdenk * (read/write). 1396*3b58acd4Swdenk * RCSR Reset Controller (RC) Status Register (read/write). 1397*3b58acd4Swdenk */ 1398*3b58acd4Swdenk 1399*3b58acd4Swdenk #define _RSRR 0x90030000 /* RC Software Reset Reg. */ 1400*3b58acd4Swdenk #define _RCSR 0x90030004 /* RC Status Reg. */ 1401*3b58acd4Swdenk 1402*3b58acd4Swdenk #if LANGUAGE == C 1403*3b58acd4Swdenk #define RSRR /* RC Software Reset Reg. */ \ 1404*3b58acd4Swdenk (*((volatile Word *) io_p2v (_RSRR))) 1405*3b58acd4Swdenk #define RCSR /* RC Status Reg. */ \ 1406*3b58acd4Swdenk (*((volatile Word *) io_p2v (_RCSR))) 1407*3b58acd4Swdenk #endif /* LANGUAGE == C */ 1408*3b58acd4Swdenk 1409*3b58acd4Swdenk #define RSRR_SWR 0x00000001 /* SoftWare Reset (set only) */ 1410*3b58acd4Swdenk 1411*3b58acd4Swdenk #define RCSR_HWR 0x00000001 /* HardWare Reset */ 1412*3b58acd4Swdenk #define RCSR_SWR 0x00000002 /* SoftWare Reset */ 1413*3b58acd4Swdenk #define RCSR_WDR 0x00000004 /* Watch-Dog Reset */ 1414*3b58acd4Swdenk #define RCSR_SMR 0x00000008 /* Sleep-Mode Reset */ 1415*3b58acd4Swdenk 1416*3b58acd4Swdenk 1417*3b58acd4Swdenk /* 1418*3b58acd4Swdenk * Test unit control registers 1419*3b58acd4Swdenk * 1420*3b58acd4Swdenk * Registers 1421*3b58acd4Swdenk * TUCR Test Unit Control Register (read/write). 1422*3b58acd4Swdenk */ 1423*3b58acd4Swdenk 1424*3b58acd4Swdenk #define _TUCR 0x90030008 /* Test Unit Control Reg. */ 1425*3b58acd4Swdenk 1426*3b58acd4Swdenk #if LANGUAGE == C 1427*3b58acd4Swdenk #define TUCR /* Test Unit Control Reg. */ \ 1428*3b58acd4Swdenk (*((volatile Word *) io_p2v (_TUCR))) 1429*3b58acd4Swdenk #endif /* LANGUAGE == C */ 1430*3b58acd4Swdenk 1431*3b58acd4Swdenk #define TUCR_TIC 0x00000040 /* TIC mode */ 1432*3b58acd4Swdenk #define TUCR_TTST 0x00000080 /* Trim TeST mode */ 1433*3b58acd4Swdenk #define TUCR_RCRC 0x00000100 /* Richard's Cyclic Redundancy */ 1434*3b58acd4Swdenk /* Check */ 1435*3b58acd4Swdenk #define TUCR_PMD 0x00000200 /* Power Management Disable */ 1436*3b58acd4Swdenk #define TUCR_MR 0x00000400 /* Memory Request mode */ 1437*3b58acd4Swdenk #define TUCR_NoMB (TUCR_MR*0) /* No Memory Bus request & grant */ 1438*3b58acd4Swdenk #define TUCR_MBGPIO (TUCR_MR*1) /* Memory Bus request (MBREQ) & */ 1439*3b58acd4Swdenk /* grant (MBGNT) on GPIO [22:21] */ 1440*3b58acd4Swdenk #define TUCR_CTB Fld (3, 20) /* Clock Test Bits */ 1441*3b58acd4Swdenk #define TUCR_FDC 0x00800000 /* RTC Force Delete Count */ 1442*3b58acd4Swdenk #define TUCR_FMC 0x01000000 /* Force Michelle's Control mode */ 1443*3b58acd4Swdenk #define TUCR_TMC 0x02000000 /* RTC Trimmer Multiplexer Control */ 1444*3b58acd4Swdenk #define TUCR_DPS 0x04000000 /* Disallow Pad Sleep */ 1445*3b58acd4Swdenk #define TUCR_TSEL Fld (3, 29) /* clock Test SELect on GPIO [27] */ 1446*3b58acd4Swdenk #define TUCR_32_768kHz /* 32.768 kHz osc. on GPIO [27] */ \ 1447*3b58acd4Swdenk (0 << FShft (TUCR_TSEL)) 1448*3b58acd4Swdenk #define TUCR_3_6864MHz /* 3.6864 MHz osc. on GPIO [27] */ \ 1449*3b58acd4Swdenk (1 << FShft (TUCR_TSEL)) 1450*3b58acd4Swdenk #define TUCR_VDD /* VDD ring osc./16 on GPIO [27] */ \ 1451*3b58acd4Swdenk (2 << FShft (TUCR_TSEL)) 1452*3b58acd4Swdenk #define TUCR_96MHzPLL /* 96 MHz PLL/4 on GPIO [27] */ \ 1453*3b58acd4Swdenk (3 << FShft (TUCR_TSEL)) 1454*3b58acd4Swdenk #define TUCR_Clock /* internal (fcpu/2) & 32.768 kHz */ \ 1455*3b58acd4Swdenk /* Clocks on GPIO [26:27] */ \ 1456*3b58acd4Swdenk (4 << FShft (TUCR_TSEL)) 1457*3b58acd4Swdenk #define TUCR_3_6864MHzA /* 3.6864 MHz osc. on GPIO [27] */ \ 1458*3b58acd4Swdenk /* (Alternative) */ \ 1459*3b58acd4Swdenk (5 << FShft (TUCR_TSEL)) 1460*3b58acd4Swdenk #define TUCR_MainPLL /* Main PLL/16 on GPIO [27] */ \ 1461*3b58acd4Swdenk (6 << FShft (TUCR_TSEL)) 1462*3b58acd4Swdenk #define TUCR_VDDL /* VDDL ring osc./4 on GPIO [27] */ \ 1463*3b58acd4Swdenk (7 << FShft (TUCR_TSEL)) 1464*3b58acd4Swdenk 1465*3b58acd4Swdenk 1466*3b58acd4Swdenk /* 1467*3b58acd4Swdenk * General-Purpose Input/Output (GPIO) control registers 1468*3b58acd4Swdenk * 1469*3b58acd4Swdenk * Registers 1470*3b58acd4Swdenk * GPLR General-Purpose Input/Output (GPIO) Pin Level 1471*3b58acd4Swdenk * Register (read). 1472*3b58acd4Swdenk * GPDR General-Purpose Input/Output (GPIO) Pin Direction 1473*3b58acd4Swdenk * Register (read/write). 1474*3b58acd4Swdenk * GPSR General-Purpose Input/Output (GPIO) Pin output Set 1475*3b58acd4Swdenk * Register (write). 1476*3b58acd4Swdenk * GPCR General-Purpose Input/Output (GPIO) Pin output Clear 1477*3b58acd4Swdenk * Register (write). 1478*3b58acd4Swdenk * GRER General-Purpose Input/Output (GPIO) Rising-Edge 1479*3b58acd4Swdenk * detect Register (read/write). 1480*3b58acd4Swdenk * GFER General-Purpose Input/Output (GPIO) Falling-Edge 1481*3b58acd4Swdenk * detect Register (read/write). 1482*3b58acd4Swdenk * GEDR General-Purpose Input/Output (GPIO) Edge Detect 1483*3b58acd4Swdenk * status Register (read/write). 1484*3b58acd4Swdenk * GAFR General-Purpose Input/Output (GPIO) Alternate 1485*3b58acd4Swdenk * Function Register (read/write). 1486*3b58acd4Swdenk * 1487*3b58acd4Swdenk * Clock 1488*3b58acd4Swdenk * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). 1489*3b58acd4Swdenk */ 1490*3b58acd4Swdenk 1491*3b58acd4Swdenk #define _GPLR 0x90040000 /* GPIO Pin Level Reg. */ 1492*3b58acd4Swdenk #define _GPDR 0x90040004 /* GPIO Pin Direction Reg. */ 1493*3b58acd4Swdenk #define _GPSR 0x90040008 /* GPIO Pin output Set Reg. */ 1494*3b58acd4Swdenk #define _GPCR 0x9004000C /* GPIO Pin output Clear Reg. */ 1495*3b58acd4Swdenk #define _GRER 0x90040010 /* GPIO Rising-Edge detect Reg. */ 1496*3b58acd4Swdenk #define _GFER 0x90040014 /* GPIO Falling-Edge detect Reg. */ 1497*3b58acd4Swdenk #define _GEDR 0x90040018 /* GPIO Edge Detect status Reg. */ 1498*3b58acd4Swdenk #define _GAFR 0x9004001C /* GPIO Alternate Function Reg. */ 1499*3b58acd4Swdenk 1500*3b58acd4Swdenk #if LANGUAGE == C 1501*3b58acd4Swdenk #define GPLR /* GPIO Pin Level Reg. */ \ 1502*3b58acd4Swdenk (*((volatile Word *) io_p2v (_GPLR))) 1503*3b58acd4Swdenk #define GPDR /* GPIO Pin Direction Reg. */ \ 1504*3b58acd4Swdenk (*((volatile Word *) io_p2v (_GPDR))) 1505*3b58acd4Swdenk #define GPSR /* GPIO Pin output Set Reg. */ \ 1506*3b58acd4Swdenk (*((volatile Word *) io_p2v (_GPSR))) 1507*3b58acd4Swdenk #define GPCR /* GPIO Pin output Clear Reg. */ \ 1508*3b58acd4Swdenk (*((volatile Word *) io_p2v (_GPCR))) 1509*3b58acd4Swdenk #define GRER /* GPIO Rising-Edge detect Reg. */ \ 1510*3b58acd4Swdenk (*((volatile Word *) io_p2v (_GRER))) 1511*3b58acd4Swdenk #define GFER /* GPIO Falling-Edge detect Reg. */ \ 1512*3b58acd4Swdenk (*((volatile Word *) io_p2v (_GFER))) 1513*3b58acd4Swdenk #define GEDR /* GPIO Edge Detect status Reg. */ \ 1514*3b58acd4Swdenk (*((volatile Word *) io_p2v (_GEDR))) 1515*3b58acd4Swdenk #define GAFR /* GPIO Alternate Function Reg. */ \ 1516*3b58acd4Swdenk (*((volatile Word *) io_p2v (_GAFR))) 1517*3b58acd4Swdenk #elif LANGUAGE == Assembly 1518*3b58acd4Swdenk 1519*3b58acd4Swdenk #define GPLR (io_p2v (_GPLR)) 1520*3b58acd4Swdenk #define GPDR (io_p2v (_GPDR)) 1521*3b58acd4Swdenk #define GPSR (io_p2v (_GPSR)) 1522*3b58acd4Swdenk #define GPCR (io_p2v (_GPCR)) 1523*3b58acd4Swdenk #define GRER (io_p2v (_GRER)) 1524*3b58acd4Swdenk #define GFER (io_p2v (_GFER)) 1525*3b58acd4Swdenk #define GEDR (io_p2v (_GEDR)) 1526*3b58acd4Swdenk #define GAFR (io_p2v (_GAFR)) 1527*3b58acd4Swdenk 1528*3b58acd4Swdenk #endif /* LANGUAGE == C */ 1529*3b58acd4Swdenk 1530*3b58acd4Swdenk #define GPIO_MIN (0) 1531*3b58acd4Swdenk #define GPIO_MAX (27) 1532*3b58acd4Swdenk 1533*3b58acd4Swdenk #define GPIO_GPIO(Nb) /* GPIO [0..27] */ \ 1534*3b58acd4Swdenk (0x00000001 << (Nb)) 1535*3b58acd4Swdenk #define GPIO_GPIO0 GPIO_GPIO (0) /* GPIO [0] */ 1536*3b58acd4Swdenk #define GPIO_GPIO1 GPIO_GPIO (1) /* GPIO [1] */ 1537*3b58acd4Swdenk #define GPIO_GPIO2 GPIO_GPIO (2) /* GPIO [2] */ 1538*3b58acd4Swdenk #define GPIO_GPIO3 GPIO_GPIO (3) /* GPIO [3] */ 1539*3b58acd4Swdenk #define GPIO_GPIO4 GPIO_GPIO (4) /* GPIO [4] */ 1540*3b58acd4Swdenk #define GPIO_GPIO5 GPIO_GPIO (5) /* GPIO [5] */ 1541*3b58acd4Swdenk #define GPIO_GPIO6 GPIO_GPIO (6) /* GPIO [6] */ 1542*3b58acd4Swdenk #define GPIO_GPIO7 GPIO_GPIO (7) /* GPIO [7] */ 1543*3b58acd4Swdenk #define GPIO_GPIO8 GPIO_GPIO (8) /* GPIO [8] */ 1544*3b58acd4Swdenk #define GPIO_GPIO9 GPIO_GPIO (9) /* GPIO [9] */ 1545*3b58acd4Swdenk #define GPIO_GPIO10 GPIO_GPIO (10) /* GPIO [10] */ 1546*3b58acd4Swdenk #define GPIO_GPIO11 GPIO_GPIO (11) /* GPIO [11] */ 1547*3b58acd4Swdenk #define GPIO_GPIO12 GPIO_GPIO (12) /* GPIO [12] */ 1548*3b58acd4Swdenk #define GPIO_GPIO13 GPIO_GPIO (13) /* GPIO [13] */ 1549*3b58acd4Swdenk #define GPIO_GPIO14 GPIO_GPIO (14) /* GPIO [14] */ 1550*3b58acd4Swdenk #define GPIO_GPIO15 GPIO_GPIO (15) /* GPIO [15] */ 1551*3b58acd4Swdenk #define GPIO_GPIO16 GPIO_GPIO (16) /* GPIO [16] */ 1552*3b58acd4Swdenk #define GPIO_GPIO17 GPIO_GPIO (17) /* GPIO [17] */ 1553*3b58acd4Swdenk #define GPIO_GPIO18 GPIO_GPIO (18) /* GPIO [18] */ 1554*3b58acd4Swdenk #define GPIO_GPIO19 GPIO_GPIO (19) /* GPIO [19] */ 1555*3b58acd4Swdenk #define GPIO_GPIO20 GPIO_GPIO (20) /* GPIO [20] */ 1556*3b58acd4Swdenk #define GPIO_GPIO21 GPIO_GPIO (21) /* GPIO [21] */ 1557*3b58acd4Swdenk #define GPIO_GPIO22 GPIO_GPIO (22) /* GPIO [22] */ 1558*3b58acd4Swdenk #define GPIO_GPIO23 GPIO_GPIO (23) /* GPIO [23] */ 1559*3b58acd4Swdenk #define GPIO_GPIO24 GPIO_GPIO (24) /* GPIO [24] */ 1560*3b58acd4Swdenk #define GPIO_GPIO25 GPIO_GPIO (25) /* GPIO [25] */ 1561*3b58acd4Swdenk #define GPIO_GPIO26 GPIO_GPIO (26) /* GPIO [26] */ 1562*3b58acd4Swdenk #define GPIO_GPIO27 GPIO_GPIO (27) /* GPIO [27] */ 1563*3b58acd4Swdenk 1564*3b58acd4Swdenk #define GPIO_LDD(Nb) /* LCD Data [8..15] (O) */ \ 1565*3b58acd4Swdenk GPIO_GPIO ((Nb) - 6) 1566*3b58acd4Swdenk #define GPIO_LDD8 GPIO_LDD (8) /* LCD Data [8] (O) */ 1567*3b58acd4Swdenk #define GPIO_LDD9 GPIO_LDD (9) /* LCD Data [9] (O) */ 1568*3b58acd4Swdenk #define GPIO_LDD10 GPIO_LDD (10) /* LCD Data [10] (O) */ 1569*3b58acd4Swdenk #define GPIO_LDD11 GPIO_LDD (11) /* LCD Data [11] (O) */ 1570*3b58acd4Swdenk #define GPIO_LDD12 GPIO_LDD (12) /* LCD Data [12] (O) */ 1571*3b58acd4Swdenk #define GPIO_LDD13 GPIO_LDD (13) /* LCD Data [13] (O) */ 1572*3b58acd4Swdenk #define GPIO_LDD14 GPIO_LDD (14) /* LCD Data [14] (O) */ 1573*3b58acd4Swdenk #define GPIO_LDD15 GPIO_LDD (15) /* LCD Data [15] (O) */ 1574*3b58acd4Swdenk /* ser. port 4: */ 1575*3b58acd4Swdenk #define GPIO_SSP_TXD GPIO_GPIO (10) /* SSP Transmit Data (O) */ 1576*3b58acd4Swdenk #define GPIO_SSP_RXD GPIO_GPIO (11) /* SSP Receive Data (I) */ 1577*3b58acd4Swdenk #define GPIO_SSP_SCLK GPIO_GPIO (12) /* SSP Sample CLocK (O) */ 1578*3b58acd4Swdenk #define GPIO_SSP_SFRM GPIO_GPIO (13) /* SSP Sample FRaMe (O) */ 1579*3b58acd4Swdenk /* ser. port 1: */ 1580*3b58acd4Swdenk #define GPIO_UART_TXD GPIO_GPIO (14) /* UART Transmit Data (O) */ 1581*3b58acd4Swdenk #define GPIO_UART_RXD GPIO_GPIO (15) /* UART Receive Data (I) */ 1582*3b58acd4Swdenk #define GPIO_SDLC_SCLK GPIO_GPIO (16) /* SDLC Sample CLocK (I/O) */ 1583*3b58acd4Swdenk #define GPIO_SDLC_AAF GPIO_GPIO (17) /* SDLC Abort After Frame (O) */ 1584*3b58acd4Swdenk #define GPIO_UART_SCLK1 GPIO_GPIO (18) /* UART Sample CLocK 1 (I) */ 1585*3b58acd4Swdenk /* ser. port 4: */ 1586*3b58acd4Swdenk #define GPIO_SSP_CLK GPIO_GPIO (19) /* SSP external CLocK (I) */ 1587*3b58acd4Swdenk /* ser. port 3: */ 1588*3b58acd4Swdenk #define GPIO_UART_SCLK3 GPIO_GPIO (20) /* UART Sample CLocK 3 (I) */ 1589*3b58acd4Swdenk /* ser. port 4: */ 1590*3b58acd4Swdenk #define GPIO_MCP_CLK GPIO_GPIO (21) /* MCP CLocK (I) */ 1591*3b58acd4Swdenk /* test controller: */ 1592*3b58acd4Swdenk #define GPIO_TIC_ACK GPIO_GPIO (21) /* TIC ACKnowledge (O) */ 1593*3b58acd4Swdenk #define GPIO_MBGNT GPIO_GPIO (21) /* Memory Bus GraNT (O) */ 1594*3b58acd4Swdenk #define GPIO_TREQA GPIO_GPIO (22) /* TIC REQuest A (I) */ 1595*3b58acd4Swdenk #define GPIO_MBREQ GPIO_GPIO (22) /* Memory Bus REQuest (I) */ 1596*3b58acd4Swdenk #define GPIO_TREQB GPIO_GPIO (23) /* TIC REQuest B (I) */ 1597*3b58acd4Swdenk #define GPIO_1Hz GPIO_GPIO (25) /* 1 Hz clock (O) */ 1598*3b58acd4Swdenk #define GPIO_RCLK GPIO_GPIO (26) /* internal (R) CLocK (O, fcpu/2) */ 1599*3b58acd4Swdenk #define GPIO_32_768kHz GPIO_GPIO (27) /* 32.768 kHz clock (O, RTC) */ 1600*3b58acd4Swdenk 1601*3b58acd4Swdenk #define GPDR_In 0 /* Input */ 1602*3b58acd4Swdenk #define GPDR_Out 1 /* Output */ 1603*3b58acd4Swdenk 1604*3b58acd4Swdenk 1605*3b58acd4Swdenk /* 1606*3b58acd4Swdenk * Interrupt Controller (IC) control registers 1607*3b58acd4Swdenk * 1608*3b58acd4Swdenk * Registers 1609*3b58acd4Swdenk * ICIP Interrupt Controller (IC) Interrupt ReQuest (IRQ) 1610*3b58acd4Swdenk * Pending register (read). 1611*3b58acd4Swdenk * ICMR Interrupt Controller (IC) Mask Register (read/write). 1612*3b58acd4Swdenk * ICLR Interrupt Controller (IC) Level Register (read/write). 1613*3b58acd4Swdenk * ICCR Interrupt Controller (IC) Control Register 1614*3b58acd4Swdenk * (read/write). 1615*3b58acd4Swdenk * [The ICCR register is only implemented in versions 2.0 1616*3b58acd4Swdenk * (rev. = 8) and higher of the StrongARM SA-1100.] 1617*3b58acd4Swdenk * ICFP Interrupt Controller (IC) Fast Interrupt reQuest 1618*3b58acd4Swdenk * (FIQ) Pending register (read). 1619*3b58acd4Swdenk * ICPR Interrupt Controller (IC) Pending Register (read). 1620*3b58acd4Swdenk * [The ICPR register is active low (inverted) in 1621*3b58acd4Swdenk * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the 1622*3b58acd4Swdenk * StrongARM SA-1100, it is active high (non-inverted) in 1623*3b58acd4Swdenk * versions 2.0 (rev. = 8) and higher.] 1624*3b58acd4Swdenk */ 1625*3b58acd4Swdenk 1626*3b58acd4Swdenk #define _ICIP 0x90050000 /* IC IRQ Pending reg. */ 1627*3b58acd4Swdenk #define _ICMR 0x90050004 /* IC Mask Reg. */ 1628*3b58acd4Swdenk #define _ICLR 0x90050008 /* IC Level Reg. */ 1629*3b58acd4Swdenk #define _ICCR 0x9005000C /* IC Control Reg. */ 1630*3b58acd4Swdenk #define _ICFP 0x90050010 /* IC FIQ Pending reg. */ 1631*3b58acd4Swdenk #define _ICPR 0x90050020 /* IC Pending Reg. */ 1632*3b58acd4Swdenk 1633*3b58acd4Swdenk #if LANGUAGE == C 1634*3b58acd4Swdenk #define ICIP /* IC IRQ Pending reg. */ \ 1635*3b58acd4Swdenk (*((volatile Word *) io_p2v (_ICIP))) 1636*3b58acd4Swdenk #define ICMR /* IC Mask Reg. */ \ 1637*3b58acd4Swdenk (*((volatile Word *) io_p2v (_ICMR))) 1638*3b58acd4Swdenk #define ICLR /* IC Level Reg. */ \ 1639*3b58acd4Swdenk (*((volatile Word *) io_p2v (_ICLR))) 1640*3b58acd4Swdenk #define ICCR /* IC Control Reg. */ \ 1641*3b58acd4Swdenk (*((volatile Word *) io_p2v (_ICCR))) 1642*3b58acd4Swdenk #define ICFP /* IC FIQ Pending reg. */ \ 1643*3b58acd4Swdenk (*((volatile Word *) io_p2v (_ICFP))) 1644*3b58acd4Swdenk #define ICPR /* IC Pending Reg. */ \ 1645*3b58acd4Swdenk (*((volatile Word *) io_p2v (_ICPR))) 1646*3b58acd4Swdenk #endif /* LANGUAGE == C */ 1647*3b58acd4Swdenk 1648*3b58acd4Swdenk #define IC_GPIO(Nb) /* GPIO [0..10] */ \ 1649*3b58acd4Swdenk (0x00000001 << (Nb)) 1650*3b58acd4Swdenk #define IC_GPIO0 IC_GPIO (0) /* GPIO [0] */ 1651*3b58acd4Swdenk #define IC_GPIO1 IC_GPIO (1) /* GPIO [1] */ 1652*3b58acd4Swdenk #define IC_GPIO2 IC_GPIO (2) /* GPIO [2] */ 1653*3b58acd4Swdenk #define IC_GPIO3 IC_GPIO (3) /* GPIO [3] */ 1654*3b58acd4Swdenk #define IC_GPIO4 IC_GPIO (4) /* GPIO [4] */ 1655*3b58acd4Swdenk #define IC_GPIO5 IC_GPIO (5) /* GPIO [5] */ 1656*3b58acd4Swdenk #define IC_GPIO6 IC_GPIO (6) /* GPIO [6] */ 1657*3b58acd4Swdenk #define IC_GPIO7 IC_GPIO (7) /* GPIO [7] */ 1658*3b58acd4Swdenk #define IC_GPIO8 IC_GPIO (8) /* GPIO [8] */ 1659*3b58acd4Swdenk #define IC_GPIO9 IC_GPIO (9) /* GPIO [9] */ 1660*3b58acd4Swdenk #define IC_GPIO10 IC_GPIO (10) /* GPIO [10] */ 1661*3b58acd4Swdenk #define IC_GPIO11_27 0x00000800 /* GPIO [11:27] (ORed) */ 1662*3b58acd4Swdenk #define IC_LCD 0x00001000 /* LCD controller */ 1663*3b58acd4Swdenk #define IC_Ser0UDC 0x00002000 /* Ser. port 0 UDC */ 1664*3b58acd4Swdenk #define IC_Ser1SDLC 0x00004000 /* Ser. port 1 SDLC */ 1665*3b58acd4Swdenk #define IC_Ser1UART 0x00008000 /* Ser. port 1 UART */ 1666*3b58acd4Swdenk #define IC_Ser2ICP 0x00010000 /* Ser. port 2 ICP */ 1667*3b58acd4Swdenk #define IC_Ser3UART 0x00020000 /* Ser. port 3 UART */ 1668*3b58acd4Swdenk #define IC_Ser4MCP 0x00040000 /* Ser. port 4 MCP */ 1669*3b58acd4Swdenk #define IC_Ser4SSP 0x00080000 /* Ser. port 4 SSP */ 1670*3b58acd4Swdenk #define IC_DMA(Nb) /* DMA controller channel [0..5] */ \ 1671*3b58acd4Swdenk (0x00100000 << (Nb)) 1672*3b58acd4Swdenk #define IC_DMA0 IC_DMA (0) /* DMA controller channel 0 */ 1673*3b58acd4Swdenk #define IC_DMA1 IC_DMA (1) /* DMA controller channel 1 */ 1674*3b58acd4Swdenk #define IC_DMA2 IC_DMA (2) /* DMA controller channel 2 */ 1675*3b58acd4Swdenk #define IC_DMA3 IC_DMA (3) /* DMA controller channel 3 */ 1676*3b58acd4Swdenk #define IC_DMA4 IC_DMA (4) /* DMA controller channel 4 */ 1677*3b58acd4Swdenk #define IC_DMA5 IC_DMA (5) /* DMA controller channel 5 */ 1678*3b58acd4Swdenk #define IC_OST(Nb) /* OS Timer match [0..3] */ \ 1679*3b58acd4Swdenk (0x04000000 << (Nb)) 1680*3b58acd4Swdenk #define IC_OST0 IC_OST (0) /* OS Timer match 0 */ 1681*3b58acd4Swdenk #define IC_OST1 IC_OST (1) /* OS Timer match 1 */ 1682*3b58acd4Swdenk #define IC_OST2 IC_OST (2) /* OS Timer match 2 */ 1683*3b58acd4Swdenk #define IC_OST3 IC_OST (3) /* OS Timer match 3 */ 1684*3b58acd4Swdenk #define IC_RTC1Hz 0x40000000 /* RTC 1 Hz clock */ 1685*3b58acd4Swdenk #define IC_RTCAlrm 0x80000000 /* RTC Alarm */ 1686*3b58acd4Swdenk 1687*3b58acd4Swdenk #define ICLR_IRQ 0 /* Interrupt ReQuest */ 1688*3b58acd4Swdenk #define ICLR_FIQ 1 /* Fast Interrupt reQuest */ 1689*3b58acd4Swdenk 1690*3b58acd4Swdenk #define ICCR_DIM 0x00000001 /* Disable Idle-mode interrupt */ 1691*3b58acd4Swdenk /* Mask */ 1692*3b58acd4Swdenk #define ICCR_IdleAllInt (ICCR_DIM*0) /* Idle-mode All Interrupt enable */ 1693*3b58acd4Swdenk /* (ICMR ignored) */ 1694*3b58acd4Swdenk #define ICCR_IdleMskInt (ICCR_DIM*1) /* Idle-mode non-Masked Interrupt */ 1695*3b58acd4Swdenk /* enable (ICMR used) */ 1696*3b58acd4Swdenk 1697*3b58acd4Swdenk 1698*3b58acd4Swdenk /* 1699*3b58acd4Swdenk * Peripheral Pin Controller (PPC) control registers 1700*3b58acd4Swdenk * 1701*3b58acd4Swdenk * Registers 1702*3b58acd4Swdenk * PPDR Peripheral Pin Controller (PPC) Pin Direction 1703*3b58acd4Swdenk * Register (read/write). 1704*3b58acd4Swdenk * PPSR Peripheral Pin Controller (PPC) Pin State Register 1705*3b58acd4Swdenk * (read/write). 1706*3b58acd4Swdenk * PPAR Peripheral Pin Controller (PPC) Pin Assignment 1707*3b58acd4Swdenk * Register (read/write). 1708*3b58acd4Swdenk * PSDR Peripheral Pin Controller (PPC) Sleep-mode pin 1709*3b58acd4Swdenk * Direction Register (read/write). 1710*3b58acd4Swdenk * PPFR Peripheral Pin Controller (PPC) Pin Flag Register 1711*3b58acd4Swdenk * (read). 1712*3b58acd4Swdenk */ 1713*3b58acd4Swdenk 1714*3b58acd4Swdenk #define _PPDR 0x90060000 /* PPC Pin Direction Reg. */ 1715*3b58acd4Swdenk #define _PPSR 0x90060004 /* PPC Pin State Reg. */ 1716*3b58acd4Swdenk #define _PPAR 0x90060008 /* PPC Pin Assignment Reg. */ 1717*3b58acd4Swdenk #define _PSDR 0x9006000C /* PPC Sleep-mode pin Direction */ 1718*3b58acd4Swdenk /* Reg. */ 1719*3b58acd4Swdenk #define _PPFR 0x90060010 /* PPC Pin Flag Reg. */ 1720*3b58acd4Swdenk 1721*3b58acd4Swdenk #if LANGUAGE == C 1722*3b58acd4Swdenk #define PPDR /* PPC Pin Direction Reg. */ \ 1723*3b58acd4Swdenk (*((volatile Word *) io_p2v (_PPDR))) 1724*3b58acd4Swdenk #define PPSR /* PPC Pin State Reg. */ \ 1725*3b58acd4Swdenk (*((volatile Word *) io_p2v (_PPSR))) 1726*3b58acd4Swdenk #define PPAR /* PPC Pin Assignment Reg. */ \ 1727*3b58acd4Swdenk (*((volatile Word *) io_p2v (_PPAR))) 1728*3b58acd4Swdenk #define PSDR /* PPC Sleep-mode pin Direction */ \ 1729*3b58acd4Swdenk /* Reg. */ \ 1730*3b58acd4Swdenk (*((volatile Word *) io_p2v (_PSDR))) 1731*3b58acd4Swdenk #define PPFR /* PPC Pin Flag Reg. */ \ 1732*3b58acd4Swdenk (*((volatile Word *) io_p2v (_PPFR))) 1733*3b58acd4Swdenk #endif /* LANGUAGE == C */ 1734*3b58acd4Swdenk 1735*3b58acd4Swdenk #define PPC_LDD(Nb) /* LCD Data [0..7] */ \ 1736*3b58acd4Swdenk (0x00000001 << (Nb)) 1737*3b58acd4Swdenk #define PPC_LDD0 PPC_LDD (0) /* LCD Data [0] */ 1738*3b58acd4Swdenk #define PPC_LDD1 PPC_LDD (1) /* LCD Data [1] */ 1739*3b58acd4Swdenk #define PPC_LDD2 PPC_LDD (2) /* LCD Data [2] */ 1740*3b58acd4Swdenk #define PPC_LDD3 PPC_LDD (3) /* LCD Data [3] */ 1741*3b58acd4Swdenk #define PPC_LDD4 PPC_LDD (4) /* LCD Data [4] */ 1742*3b58acd4Swdenk #define PPC_LDD5 PPC_LDD (5) /* LCD Data [5] */ 1743*3b58acd4Swdenk #define PPC_LDD6 PPC_LDD (6) /* LCD Data [6] */ 1744*3b58acd4Swdenk #define PPC_LDD7 PPC_LDD (7) /* LCD Data [7] */ 1745*3b58acd4Swdenk #define PPC_L_PCLK 0x00000100 /* LCD Pixel CLocK */ 1746*3b58acd4Swdenk #define PPC_L_LCLK 0x00000200 /* LCD Line CLocK */ 1747*3b58acd4Swdenk #define PPC_L_FCLK 0x00000400 /* LCD Frame CLocK */ 1748*3b58acd4Swdenk #define PPC_L_BIAS 0x00000800 /* LCD AC BIAS */ 1749*3b58acd4Swdenk /* ser. port 1: */ 1750*3b58acd4Swdenk #define PPC_TXD1 0x00001000 /* SDLC/UART Transmit Data 1 */ 1751*3b58acd4Swdenk #define PPC_RXD1 0x00002000 /* SDLC/UART Receive Data 1 */ 1752*3b58acd4Swdenk /* ser. port 2: */ 1753*3b58acd4Swdenk #define PPC_TXD2 0x00004000 /* IPC Transmit Data 2 */ 1754*3b58acd4Swdenk #define PPC_RXD2 0x00008000 /* IPC Receive Data 2 */ 1755*3b58acd4Swdenk /* ser. port 3: */ 1756*3b58acd4Swdenk #define PPC_TXD3 0x00010000 /* UART Transmit Data 3 */ 1757*3b58acd4Swdenk #define PPC_RXD3 0x00020000 /* UART Receive Data 3 */ 1758*3b58acd4Swdenk /* ser. port 4: */ 1759*3b58acd4Swdenk #define PPC_TXD4 0x00040000 /* MCP/SSP Transmit Data 4 */ 1760*3b58acd4Swdenk #define PPC_RXD4 0x00080000 /* MCP/SSP Receive Data 4 */ 1761*3b58acd4Swdenk #define PPC_SCLK 0x00100000 /* MCP/SSP Sample CLocK */ 1762*3b58acd4Swdenk #define PPC_SFRM 0x00200000 /* MCP/SSP Sample FRaMe */ 1763*3b58acd4Swdenk 1764*3b58acd4Swdenk #define PPDR_In 0 /* Input */ 1765*3b58acd4Swdenk #define PPDR_Out 1 /* Output */ 1766*3b58acd4Swdenk 1767*3b58acd4Swdenk /* ser. port 1: */ 1768*3b58acd4Swdenk #define PPAR_UPR 0x00001000 /* UART Pin Reassignment */ 1769*3b58acd4Swdenk #define PPAR_UARTTR (PPAR_UPR*0) /* UART on TXD_1 & RXD_1 */ 1770*3b58acd4Swdenk #define PPAR_UARTGPIO (PPAR_UPR*1) /* UART on GPIO [14:15] */ 1771*3b58acd4Swdenk /* ser. port 4: */ 1772*3b58acd4Swdenk #define PPAR_SPR 0x00040000 /* SSP Pin Reassignment */ 1773*3b58acd4Swdenk #define PPAR_SSPTRSS (PPAR_SPR*0) /* SSP on TXD_C, RXD_C, SCLK_C, */ 1774*3b58acd4Swdenk /* & SFRM_C */ 1775*3b58acd4Swdenk #define PPAR_SSPGPIO (PPAR_SPR*1) /* SSP on GPIO [10:13] */ 1776*3b58acd4Swdenk 1777*3b58acd4Swdenk #define PSDR_OutL 0 /* Output Low in sleep mode */ 1778*3b58acd4Swdenk #define PSDR_Flt 1 /* Floating (input) in sleep mode */ 1779*3b58acd4Swdenk 1780*3b58acd4Swdenk #define PPFR_LCD 0x00000001 /* LCD controller */ 1781*3b58acd4Swdenk #define PPFR_SP1TX 0x00001000 /* Ser. Port 1 SDLC/UART Transmit */ 1782*3b58acd4Swdenk #define PPFR_SP1RX 0x00002000 /* Ser. Port 1 SDLC/UART Receive */ 1783*3b58acd4Swdenk #define PPFR_SP2TX 0x00004000 /* Ser. Port 2 ICP Transmit */ 1784*3b58acd4Swdenk #define PPFR_SP2RX 0x00008000 /* Ser. Port 2 ICP Receive */ 1785*3b58acd4Swdenk #define PPFR_SP3TX 0x00010000 /* Ser. Port 3 UART Transmit */ 1786*3b58acd4Swdenk #define PPFR_SP3RX 0x00020000 /* Ser. Port 3 UART Receive */ 1787*3b58acd4Swdenk #define PPFR_SP4 0x00040000 /* Ser. Port 4 MCP/SSP */ 1788*3b58acd4Swdenk #define PPFR_PerEn 0 /* Peripheral Enabled */ 1789*3b58acd4Swdenk #define PPFR_PPCEn 1 /* PPC Enabled */ 1790*3b58acd4Swdenk 1791*3b58acd4Swdenk 1792*3b58acd4Swdenk /* 1793*3b58acd4Swdenk * Dynamic Random-Access Memory (DRAM) control registers 1794*3b58acd4Swdenk * 1795*3b58acd4Swdenk * Registers 1796*3b58acd4Swdenk * MDCNFG Memory system: Dynamic Random-Access Memory (DRAM) 1797*3b58acd4Swdenk * CoNFiGuration register (read/write). 1798*3b58acd4Swdenk * MDCAS0 Memory system: Dynamic Random-Access Memory (DRAM) 1799*3b58acd4Swdenk * Column Address Strobe (CAS) shift register 0 1800*3b58acd4Swdenk * (read/write). 1801*3b58acd4Swdenk * MDCAS1 Memory system: Dynamic Random-Access Memory (DRAM) 1802*3b58acd4Swdenk * Column Address Strobe (CAS) shift register 1 1803*3b58acd4Swdenk * (read/write). 1804*3b58acd4Swdenk * MDCAS2 Memory system: Dynamic Random-Access Memory (DRAM) 1805*3b58acd4Swdenk * Column Address Strobe (CAS) shift register 2 1806*3b58acd4Swdenk * (read/write). 1807*3b58acd4Swdenk * 1808*3b58acd4Swdenk * Clocks 1809*3b58acd4Swdenk * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). 1810*3b58acd4Swdenk * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2). 1811*3b58acd4Swdenk * fcas, Tcas Frequency, period of the DRAM CAS shift registers. 1812*3b58acd4Swdenk */ 1813*3b58acd4Swdenk 1814*3b58acd4Swdenk /* Memory system: */ 1815*3b58acd4Swdenk #define _MDCNFG 0xA0000000 /* DRAM CoNFiGuration reg. */ 1816*3b58acd4Swdenk #define _MDCAS(Nb) /* DRAM CAS shift reg. [0..3] */ \ 1817*3b58acd4Swdenk (0xA0000004 + (Nb)*4) 1818*3b58acd4Swdenk #define _MDCAS0 _MDCAS (0) /* DRAM CAS shift reg. 0 */ 1819*3b58acd4Swdenk #define _MDCAS1 _MDCAS (1) /* DRAM CAS shift reg. 1 */ 1820*3b58acd4Swdenk #define _MDCAS2 _MDCAS (2) /* DRAM CAS shift reg. 2 */ 1821*3b58acd4Swdenk 1822*3b58acd4Swdenk #if LANGUAGE == C 1823*3b58acd4Swdenk /* Memory system: */ 1824*3b58acd4Swdenk #define MDCNFG /* DRAM CoNFiGuration reg. */ \ 1825*3b58acd4Swdenk (*((volatile Word *) io_p2v (_MDCNFG))) 1826*3b58acd4Swdenk #define MDCAS /* DRAM CAS shift reg. [0..3] */ \ 1827*3b58acd4Swdenk ((volatile Word *) io_p2v (_MDCAS (0))) 1828*3b58acd4Swdenk #define MDCAS0 (MDCAS [0]) /* DRAM CAS shift reg. 0 */ 1829*3b58acd4Swdenk #define MDCAS1 (MDCAS [1]) /* DRAM CAS shift reg. 1 */ 1830*3b58acd4Swdenk #define MDCAS2 (MDCAS [2]) /* DRAM CAS shift reg. 2 */ 1831*3b58acd4Swdenk 1832*3b58acd4Swdenk #elif LANGUAGE == Assembly 1833*3b58acd4Swdenk 1834*3b58acd4Swdenk #define MDCNFG (io_p2v(_MDCNFG)) 1835*3b58acd4Swdenk 1836*3b58acd4Swdenk #endif /* LANGUAGE == C */ 1837*3b58acd4Swdenk 1838*3b58acd4Swdenk /* SA1100 MDCNFG values */ 1839*3b58acd4Swdenk #define MDCNFG_DE(Nb) /* DRAM Enable bank [0..3] */ \ 1840*3b58acd4Swdenk (0x00000001 << (Nb)) 1841*3b58acd4Swdenk #define MDCNFG_DE0 MDCNFG_DE (0) /* DRAM Enable bank 0 */ 1842*3b58acd4Swdenk #define MDCNFG_DE1 MDCNFG_DE (1) /* DRAM Enable bank 1 */ 1843*3b58acd4Swdenk #define MDCNFG_DE2 MDCNFG_DE (2) /* DRAM Enable bank 2 */ 1844*3b58acd4Swdenk #define MDCNFG_DE3 MDCNFG_DE (3) /* DRAM Enable bank 3 */ 1845*3b58acd4Swdenk #define MDCNFG_DRAC Fld (2, 4) /* DRAM Row Address Count - 9 */ 1846*3b58acd4Swdenk #define MDCNFG_RowAdd(Add) /* Row Address count [9..12] */ \ 1847*3b58acd4Swdenk (((Add) - 9) << FShft (MDCNFG_DRAC)) 1848*3b58acd4Swdenk #define MDCNFG_CDB2 0x00000040 /* shift reg. Clock Divide By 2 */ 1849*3b58acd4Swdenk /* (fcas = fcpu/2) */ 1850*3b58acd4Swdenk #define MDCNFG_TRP Fld (4, 7) /* Time RAS Pre-charge - 1 [Tmem] */ 1851*3b58acd4Swdenk #define MDCNFG_PrChrg(Tcpu) /* Pre-Charge time [2..32 Tcpu] */ \ 1852*3b58acd4Swdenk (((Tcpu) - 2)/2 << FShft (MDCNFG_TRP)) 1853*3b58acd4Swdenk #define MDCNFG_CeilPrChrg(Tcpu) /* Ceil. of PrChrg [2..32 Tcpu] */ \ 1854*3b58acd4Swdenk (((Tcpu) - 1)/2 << FShft (MDCNFG_TRP)) 1855*3b58acd4Swdenk #define MDCNFG_TRASR Fld (4, 11) /* Time RAS Refresh - 1 [Tmem] */ 1856*3b58acd4Swdenk #define MDCNFG_Ref(Tcpu) /* Refresh time [2..32 Tcpu] */ \ 1857*3b58acd4Swdenk (((Tcpu) - 2)/2 << FShft (MDCNFG_TRASR)) 1858*3b58acd4Swdenk #define MDCNFG_CeilRef(Tcpu) /* Ceil. of Ref [2..32 Tcpu] */ \ 1859*3b58acd4Swdenk (((Tcpu) - 1)/2 << FShft (MDCNFG_TRASR)) 1860*3b58acd4Swdenk #define MDCNFG_TDL Fld (2, 15) /* Time Data Latch [Tcpu] */ 1861*3b58acd4Swdenk #define MDCNFG_DataLtch(Tcpu) /* Data Latch delay [0..3 Tcpu] */ \ 1862*3b58acd4Swdenk ((Tcpu) << FShft (MDCNFG_TDL)) 1863*3b58acd4Swdenk #define MDCNFG_DRI Fld (15, 17) /* min. DRAM Refresh Interval/4 */ 1864*3b58acd4Swdenk /* [Tmem] */ 1865*3b58acd4Swdenk #define MDCNFG_RefInt(Tcpu) /* min. Refresh Interval */ \ 1866*3b58acd4Swdenk /* [0..262136 Tcpu] */ \ 1867*3b58acd4Swdenk ((Tcpu)/8 << FShft (MDCNFG_DRI)) 1868*3b58acd4Swdenk 1869*3b58acd4Swdenk /* SA1110 MDCNFG values */ 1870*3b58acd4Swdenk #define MDCNFG_SA1110_DE0 0x00000001 /* DRAM Enable bank 0 */ 1871*3b58acd4Swdenk #define MDCNFG_SA1110_DE1 0x00000002 /* DRAM Enable bank 1 */ 1872*3b58acd4Swdenk #define MDCNFG_SA1110_DTIM0 0x00000004 /* DRAM timing type 0/1 */ 1873*3b58acd4Swdenk #define MDCNFG_SA1110_DWID0 0x00000008 /* DRAM bus width 0/1 */ 1874*3b58acd4Swdenk #define MDCNFG_SA1110_DRAC0 Fld(3, 4) /* DRAM row addr bit count */ 1875*3b58acd4Swdenk /* bank 0/1 */ 1876*3b58acd4Swdenk #define MDCNFG_SA1110_CDB20 0x00000080 /* Mem Clock divide by 2 0/1 */ 1877*3b58acd4Swdenk #define MDCNFG_SA1110_TRP0 Fld(3, 8) /* RAS precharge 0/1 */ 1878*3b58acd4Swdenk #define MDCNFG_SA1110_TDL0 Fld(2, 12) /* Data input latch after CAS*/ 1879*3b58acd4Swdenk /* deassertion 0/1 */ 1880*3b58acd4Swdenk #define MDCNFG_SA1110_TWR0 Fld(2, 14) /* SDRAM write recovery 0/1 */ 1881*3b58acd4Swdenk #define MDCNFG_SA1110_DE2 0x00010000 /* DRAM Enable bank 0 */ 1882*3b58acd4Swdenk #define MDCNFG_SA1110_DE3 0x00020000 /* DRAM Enable bank 1 */ 1883*3b58acd4Swdenk #define MDCNFG_SA1110_DTIM2 0x00040000 /* DRAM timing type 0/1 */ 1884*3b58acd4Swdenk #define MDCNFG_SA1110_DWID2 0x00080000 /* DRAM bus width 0/1 */ 1885*3b58acd4Swdenk #define MDCNFG_SA1110_DRAC2 Fld(3, 20) /* DRAM row addr bit count */ 1886*3b58acd4Swdenk /* bank 0/1 */ 1887*3b58acd4Swdenk #define MDCNFG_SA1110_CDB22 0x00800000 /* Mem Clock divide by 2 0/1 */ 1888*3b58acd4Swdenk #define MDCNFG_SA1110_TRP2 Fld(3, 24) /* RAS precharge 0/1 */ 1889*3b58acd4Swdenk #define MDCNFG_SA1110_TDL2 Fld(2, 28) /* Data input latch after CAS*/ 1890*3b58acd4Swdenk /* deassertion 0/1 */ 1891*3b58acd4Swdenk #define MDCNFG_SA1110_TWR2 Fld(2, 30) /* SDRAM write recovery 0/1 */ 1892*3b58acd4Swdenk 1893*3b58acd4Swdenk 1894*3b58acd4Swdenk /* 1895*3b58acd4Swdenk * Static memory control registers 1896*3b58acd4Swdenk * 1897*3b58acd4Swdenk * Registers 1898*3b58acd4Swdenk * MSC0 Memory system: Static memory Control register 0 1899*3b58acd4Swdenk * (read/write). 1900*3b58acd4Swdenk * MSC1 Memory system: Static memory Control register 1 1901*3b58acd4Swdenk * (read/write). 1902*3b58acd4Swdenk * 1903*3b58acd4Swdenk * Clocks 1904*3b58acd4Swdenk * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). 1905*3b58acd4Swdenk * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2). 1906*3b58acd4Swdenk */ 1907*3b58acd4Swdenk 1908*3b58acd4Swdenk /* Memory system: */ 1909*3b58acd4Swdenk #define _MSC(Nb) /* Static memory Control reg. */ \ 1910*3b58acd4Swdenk /* [0..1] */ \ 1911*3b58acd4Swdenk (0xA0000010 + (Nb)*4) 1912*3b58acd4Swdenk #define _MSC0 _MSC (0) /* Static memory Control reg. 0 */ 1913*3b58acd4Swdenk #define _MSC1 _MSC (1) /* Static memory Control reg. 1 */ 1914*3b58acd4Swdenk #define _MSC2 0xA000002C /* Static memory Control reg. 2, not contiguous */ 1915*3b58acd4Swdenk 1916*3b58acd4Swdenk #if LANGUAGE == C 1917*3b58acd4Swdenk /* Memory system: */ 1918*3b58acd4Swdenk #define MSC /* Static memory Control reg. */ \ 1919*3b58acd4Swdenk /* [0..1] */ \ 1920*3b58acd4Swdenk ((volatile Word *) io_p2v (_MSC (0))) 1921*3b58acd4Swdenk #define MSC0 (MSC [0]) /* Static memory Control reg. 0 */ 1922*3b58acd4Swdenk #define MSC1 (MSC [1]) /* Static memory Control reg. 1 */ 1923*3b58acd4Swdenk #define MSC2 (*(volatile Word *) io_p2v (_MSC2)) /* Static memory Control reg. 2 */ 1924*3b58acd4Swdenk 1925*3b58acd4Swdenk #elif LANGUAGE == Assembly 1926*3b58acd4Swdenk 1927*3b58acd4Swdenk #define MSC0 io_p2v(0xa0000010) 1928*3b58acd4Swdenk #define MSC1 io_p2v(0xa0000014) 1929*3b58acd4Swdenk #define MSC2 io_p2v(0xa000002c) 1930*3b58acd4Swdenk 1931*3b58acd4Swdenk #endif /* LANGUAGE == C */ 1932*3b58acd4Swdenk 1933*3b58acd4Swdenk #define MSC_Bnk(Nb) /* static memory Bank [0..3] */ \ 1934*3b58acd4Swdenk Fld (16, ((Nb) Modulo 2)*16) 1935*3b58acd4Swdenk #define MSC0_Bnk0 MSC_Bnk (0) /* static memory Bank 0 */ 1936*3b58acd4Swdenk #define MSC0_Bnk1 MSC_Bnk (1) /* static memory Bank 1 */ 1937*3b58acd4Swdenk #define MSC1_Bnk2 MSC_Bnk (2) /* static memory Bank 2 */ 1938*3b58acd4Swdenk #define MSC1_Bnk3 MSC_Bnk (3) /* static memory Bank 3 */ 1939*3b58acd4Swdenk 1940*3b58acd4Swdenk #define MSC_RT Fld (2, 0) /* ROM/static memory Type */ 1941*3b58acd4Swdenk #define MSC_NonBrst /* Non-Burst static memory */ \ 1942*3b58acd4Swdenk (0 << FShft (MSC_RT)) 1943*3b58acd4Swdenk #define MSC_SRAM /* 32-bit byte-writable SRAM */ \ 1944*3b58acd4Swdenk (1 << FShft (MSC_RT)) 1945*3b58acd4Swdenk #define MSC_Brst4 /* Burst-of-4 static memory */ \ 1946*3b58acd4Swdenk (2 << FShft (MSC_RT)) 1947*3b58acd4Swdenk #define MSC_Brst8 /* Burst-of-8 static memory */ \ 1948*3b58acd4Swdenk (3 << FShft (MSC_RT)) 1949*3b58acd4Swdenk #define MSC_RBW 0x0004 /* ROM/static memory Bus Width */ 1950*3b58acd4Swdenk #define MSC_32BitStMem (MSC_RBW*0) /* 32-Bit Static Memory */ 1951*3b58acd4Swdenk #define MSC_16BitStMem (MSC_RBW*1) /* 16-Bit Static Memory */ 1952*3b58acd4Swdenk #define MSC_RDF Fld (5, 3) /* ROM/static memory read Delay */ 1953*3b58acd4Swdenk /* First access - 1(.5) [Tmem] */ 1954*3b58acd4Swdenk #define MSC_1stRdAcc(Tcpu) /* 1st Read Access time (burst */ \ 1955*3b58acd4Swdenk /* static memory) [3..65 Tcpu] */ \ 1956*3b58acd4Swdenk ((((Tcpu) - 3)/2) << FShft (MSC_RDF)) 1957*3b58acd4Swdenk #define MSC_Ceil1stRdAcc(Tcpu) /* Ceil. of 1stRdAcc [3..65 Tcpu] */ \ 1958*3b58acd4Swdenk ((((Tcpu) - 2)/2) << FShft (MSC_RDF)) 1959*3b58acd4Swdenk #define MSC_RdAcc(Tcpu) /* Read Access time (non-burst */ \ 1960*3b58acd4Swdenk /* static memory) [2..64 Tcpu] */ \ 1961*3b58acd4Swdenk ((((Tcpu) - 2)/2) << FShft (MSC_RDF)) 1962*3b58acd4Swdenk #define MSC_CeilRdAcc(Tcpu) /* Ceil. of RdAcc [2..64 Tcpu] */ \ 1963*3b58acd4Swdenk ((((Tcpu) - 1)/2) << FShft (MSC_RDF)) 1964*3b58acd4Swdenk #define MSC_RDN Fld (5, 8) /* ROM/static memory read Delay */ 1965*3b58acd4Swdenk /* Next access - 1 [Tmem] */ 1966*3b58acd4Swdenk #define MSC_NxtRdAcc(Tcpu) /* Next Read Access time (burst */ \ 1967*3b58acd4Swdenk /* static memory) [2..64 Tcpu] */ \ 1968*3b58acd4Swdenk ((((Tcpu) - 2)/2) << FShft (MSC_RDN)) 1969*3b58acd4Swdenk #define MSC_CeilNxtRdAcc(Tcpu) /* Ceil. of NxtRdAcc [2..64 Tcpu] */ \ 1970*3b58acd4Swdenk ((((Tcpu) - 1)/2) << FShft (MSC_RDN)) 1971*3b58acd4Swdenk #define MSC_WrAcc(Tcpu) /* Write Access time (non-burst */ \ 1972*3b58acd4Swdenk /* static memory) [2..64 Tcpu] */ \ 1973*3b58acd4Swdenk ((((Tcpu) - 2)/2) << FShft (MSC_RDN)) 1974*3b58acd4Swdenk #define MSC_CeilWrAcc(Tcpu) /* Ceil. of WrAcc [2..64 Tcpu] */ \ 1975*3b58acd4Swdenk ((((Tcpu) - 1)/2) << FShft (MSC_RDN)) 1976*3b58acd4Swdenk #define MSC_RRR Fld (3, 13) /* ROM/static memory RecoveRy */ 1977*3b58acd4Swdenk /* time/2 [Tmem] */ 1978*3b58acd4Swdenk #define MSC_Rec(Tcpu) /* Recovery time [0..28 Tcpu] */ \ 1979*3b58acd4Swdenk (((Tcpu)/4) << FShft (MSC_RRR)) 1980*3b58acd4Swdenk #define MSC_CeilRec(Tcpu) /* Ceil. of Rec [0..28 Tcpu] */ \ 1981*3b58acd4Swdenk ((((Tcpu) + 3)/4) << FShft (MSC_RRR)) 1982*3b58acd4Swdenk 1983*3b58acd4Swdenk 1984*3b58acd4Swdenk /* 1985*3b58acd4Swdenk * Personal Computer Memory Card International Association (PCMCIA) control 1986*3b58acd4Swdenk * register 1987*3b58acd4Swdenk * 1988*3b58acd4Swdenk * Register 1989*3b58acd4Swdenk * MECR Memory system: Expansion memory bus (PCMCIA) 1990*3b58acd4Swdenk * Configuration Register (read/write). 1991*3b58acd4Swdenk * 1992*3b58acd4Swdenk * Clocks 1993*3b58acd4Swdenk * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). 1994*3b58acd4Swdenk * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2). 1995*3b58acd4Swdenk * fbclk, Tbclk Frequency, period of the PCMCIA clock (BCLK). 1996*3b58acd4Swdenk */ 1997*3b58acd4Swdenk 1998*3b58acd4Swdenk /* Memory system: */ 1999*3b58acd4Swdenk #define _MECR 0xA0000018 /* Expansion memory bus (PCMCIA) */ 2000*3b58acd4Swdenk /* Configuration Reg. */ 2001*3b58acd4Swdenk 2002*3b58acd4Swdenk #if LANGUAGE == C 2003*3b58acd4Swdenk /* Memory system: */ 2004*3b58acd4Swdenk #define MECR /* Expansion memory bus (PCMCIA) */ \ 2005*3b58acd4Swdenk /* Configuration Reg. */ \ 2006*3b58acd4Swdenk (*((volatile Word *) io_p2v (_MECR))) 2007*3b58acd4Swdenk #endif /* LANGUAGE == C */ 2008*3b58acd4Swdenk 2009*3b58acd4Swdenk #define MECR_PCMCIA(Nb) /* PCMCIA [0..1] */ \ 2010*3b58acd4Swdenk Fld (15, (Nb)*16) 2011*3b58acd4Swdenk #define MECR_PCMCIA0 MECR_PCMCIA (0) /* PCMCIA 0 */ 2012*3b58acd4Swdenk #define MECR_PCMCIA1 MECR_PCMCIA (1) /* PCMCIA 1 */ 2013*3b58acd4Swdenk 2014*3b58acd4Swdenk #define MECR_BSIO Fld (5, 0) /* BCLK Select I/O - 1 [Tmem] */ 2015*3b58acd4Swdenk #define MECR_IOClk(Tcpu) /* I/O Clock [2..64 Tcpu] */ \ 2016*3b58acd4Swdenk ((((Tcpu) - 2)/2) << FShft (MECR_BSIO)) 2017*3b58acd4Swdenk #define MECR_CeilIOClk(Tcpu) /* Ceil. of IOClk [2..64 Tcpu] */ \ 2018*3b58acd4Swdenk ((((Tcpu) - 1)/2) << FShft (MECR_BSIO)) 2019*3b58acd4Swdenk #define MECR_BSA Fld (5, 5) /* BCLK Select Attribute - 1 */ 2020*3b58acd4Swdenk /* [Tmem] */ 2021*3b58acd4Swdenk #define MECR_AttrClk(Tcpu) /* Attribute Clock [2..64 Tcpu] */ \ 2022*3b58acd4Swdenk ((((Tcpu) - 2)/2) << FShft (MECR_BSA)) 2023*3b58acd4Swdenk #define MECR_CeilAttrClk(Tcpu) /* Ceil. of AttrClk [2..64 Tcpu] */ \ 2024*3b58acd4Swdenk ((((Tcpu) - 1)/2) << FShft (MECR_BSA)) 2025*3b58acd4Swdenk #define MECR_BSM Fld (5, 10) /* BCLK Select Memory - 1 [Tmem] */ 2026*3b58acd4Swdenk #define MECR_MemClk(Tcpu) /* Memory Clock [2..64 Tcpu] */ \ 2027*3b58acd4Swdenk ((((Tcpu) - 2)/2) << FShft (MECR_BSM)) 2028*3b58acd4Swdenk #define MECR_CeilMemClk(Tcpu) /* Ceil. of MemClk [2..64 Tcpu] */ \ 2029*3b58acd4Swdenk ((((Tcpu) - 1)/2) << FShft (MECR_BSM)) 2030*3b58acd4Swdenk 2031*3b58acd4Swdenk /* 2032*3b58acd4Swdenk * On SA1110 only 2033*3b58acd4Swdenk */ 2034*3b58acd4Swdenk 2035*3b58acd4Swdenk #define _MDREFR 0xA000001C 2036*3b58acd4Swdenk 2037*3b58acd4Swdenk #if LANGUAGE == C 2038*3b58acd4Swdenk /* Memory system: */ 2039*3b58acd4Swdenk #define MDREFR \ 2040*3b58acd4Swdenk (*((volatile Word *) io_p2v (_MDREFR))) 2041*3b58acd4Swdenk 2042*3b58acd4Swdenk #elif LANGUAGE == Assembly 2043*3b58acd4Swdenk 2044*3b58acd4Swdenk #define MDREFR (io_p2v(_MDREFR)) 2045*3b58acd4Swdenk 2046*3b58acd4Swdenk #endif /* LANGUAGE == C */ 2047*3b58acd4Swdenk 2048*3b58acd4Swdenk #define MDREFR_TRASR Fld (4, 0) 2049*3b58acd4Swdenk #define MDREFR_DRI Fld (12, 4) 2050*3b58acd4Swdenk #define MDREFR_E0PIN (1 << 16) 2051*3b58acd4Swdenk #define MDREFR_K0RUN (1 << 17) 2052*3b58acd4Swdenk #define MDREFR_K0DB2 (1 << 18) 2053*3b58acd4Swdenk #define MDREFR_E1PIN (1 << 20) 2054*3b58acd4Swdenk #define MDREFR_K1RUN (1 << 21) 2055*3b58acd4Swdenk #define MDREFR_K1DB2 (1 << 22) 2056*3b58acd4Swdenk #define MDREFR_K2RUN (1 << 25) 2057*3b58acd4Swdenk #define MDREFR_K2DB2 (1 << 26) 2058*3b58acd4Swdenk #define MDREFR_EAPD (1 << 28) 2059*3b58acd4Swdenk #define MDREFR_KAPD (1 << 29) 2060*3b58acd4Swdenk #define MDREFR_SLFRSH (1 << 31) 2061*3b58acd4Swdenk 2062*3b58acd4Swdenk 2063*3b58acd4Swdenk /* 2064*3b58acd4Swdenk * Direct Memory Access (DMA) control registers 2065*3b58acd4Swdenk * 2066*3b58acd4Swdenk * Registers 2067*3b58acd4Swdenk * DDAR0 Direct Memory Access (DMA) Device Address Register 2068*3b58acd4Swdenk * channel 0 (read/write). 2069*3b58acd4Swdenk * DCSR0 Direct Memory Access (DMA) Control and Status 2070*3b58acd4Swdenk * Register channel 0 (read/write). 2071*3b58acd4Swdenk * DBSA0 Direct Memory Access (DMA) Buffer Start address 2072*3b58acd4Swdenk * register A channel 0 (read/write). 2073*3b58acd4Swdenk * DBTA0 Direct Memory Access (DMA) Buffer Transfer count 2074*3b58acd4Swdenk * register A channel 0 (read/write). 2075*3b58acd4Swdenk * DBSB0 Direct Memory Access (DMA) Buffer Start address 2076*3b58acd4Swdenk * register B channel 0 (read/write). 2077*3b58acd4Swdenk * DBTB0 Direct Memory Access (DMA) Buffer Transfer count 2078*3b58acd4Swdenk * register B channel 0 (read/write). 2079*3b58acd4Swdenk * 2080*3b58acd4Swdenk * DDAR1 Direct Memory Access (DMA) Device Address Register 2081*3b58acd4Swdenk * channel 1 (read/write). 2082*3b58acd4Swdenk * DCSR1 Direct Memory Access (DMA) Control and Status 2083*3b58acd4Swdenk * Register channel 1 (read/write). 2084*3b58acd4Swdenk * DBSA1 Direct Memory Access (DMA) Buffer Start address 2085*3b58acd4Swdenk * register A channel 1 (read/write). 2086*3b58acd4Swdenk * DBTA1 Direct Memory Access (DMA) Buffer Transfer count 2087*3b58acd4Swdenk * register A channel 1 (read/write). 2088*3b58acd4Swdenk * DBSB1 Direct Memory Access (DMA) Buffer Start address 2089*3b58acd4Swdenk * register B channel 1 (read/write). 2090*3b58acd4Swdenk * DBTB1 Direct Memory Access (DMA) Buffer Transfer count 2091*3b58acd4Swdenk * register B channel 1 (read/write). 2092*3b58acd4Swdenk * 2093*3b58acd4Swdenk * DDAR2 Direct Memory Access (DMA) Device Address Register 2094*3b58acd4Swdenk * channel 2 (read/write). 2095*3b58acd4Swdenk * DCSR2 Direct Memory Access (DMA) Control and Status 2096*3b58acd4Swdenk * Register channel 2 (read/write). 2097*3b58acd4Swdenk * DBSA2 Direct Memory Access (DMA) Buffer Start address 2098*3b58acd4Swdenk * register A channel 2 (read/write). 2099*3b58acd4Swdenk * DBTA2 Direct Memory Access (DMA) Buffer Transfer count 2100*3b58acd4Swdenk * register A channel 2 (read/write). 2101*3b58acd4Swdenk * DBSB2 Direct Memory Access (DMA) Buffer Start address 2102*3b58acd4Swdenk * register B channel 2 (read/write). 2103*3b58acd4Swdenk * DBTB2 Direct Memory Access (DMA) Buffer Transfer count 2104*3b58acd4Swdenk * register B channel 2 (read/write). 2105*3b58acd4Swdenk * 2106*3b58acd4Swdenk * DDAR3 Direct Memory Access (DMA) Device Address Register 2107*3b58acd4Swdenk * channel 3 (read/write). 2108*3b58acd4Swdenk * DCSR3 Direct Memory Access (DMA) Control and Status 2109*3b58acd4Swdenk * Register channel 3 (read/write). 2110*3b58acd4Swdenk * DBSA3 Direct Memory Access (DMA) Buffer Start address 2111*3b58acd4Swdenk * register A channel 3 (read/write). 2112*3b58acd4Swdenk * DBTA3 Direct Memory Access (DMA) Buffer Transfer count 2113*3b58acd4Swdenk * register A channel 3 (read/write). 2114*3b58acd4Swdenk * DBSB3 Direct Memory Access (DMA) Buffer Start address 2115*3b58acd4Swdenk * register B channel 3 (read/write). 2116*3b58acd4Swdenk * DBTB3 Direct Memory Access (DMA) Buffer Transfer count 2117*3b58acd4Swdenk * register B channel 3 (read/write). 2118*3b58acd4Swdenk * 2119*3b58acd4Swdenk * DDAR4 Direct Memory Access (DMA) Device Address Register 2120*3b58acd4Swdenk * channel 4 (read/write). 2121*3b58acd4Swdenk * DCSR4 Direct Memory Access (DMA) Control and Status 2122*3b58acd4Swdenk * Register channel 4 (read/write). 2123*3b58acd4Swdenk * DBSA4 Direct Memory Access (DMA) Buffer Start address 2124*3b58acd4Swdenk * register A channel 4 (read/write). 2125*3b58acd4Swdenk * DBTA4 Direct Memory Access (DMA) Buffer Transfer count 2126*3b58acd4Swdenk * register A channel 4 (read/write). 2127*3b58acd4Swdenk * DBSB4 Direct Memory Access (DMA) Buffer Start address 2128*3b58acd4Swdenk * register B channel 4 (read/write). 2129*3b58acd4Swdenk * DBTB4 Direct Memory Access (DMA) Buffer Transfer count 2130*3b58acd4Swdenk * register B channel 4 (read/write). 2131*3b58acd4Swdenk * 2132*3b58acd4Swdenk * DDAR5 Direct Memory Access (DMA) Device Address Register 2133*3b58acd4Swdenk * channel 5 (read/write). 2134*3b58acd4Swdenk * DCSR5 Direct Memory Access (DMA) Control and Status 2135*3b58acd4Swdenk * Register channel 5 (read/write). 2136*3b58acd4Swdenk * DBSA5 Direct Memory Access (DMA) Buffer Start address 2137*3b58acd4Swdenk * register A channel 5 (read/write). 2138*3b58acd4Swdenk * DBTA5 Direct Memory Access (DMA) Buffer Transfer count 2139*3b58acd4Swdenk * register A channel 5 (read/write). 2140*3b58acd4Swdenk * DBSB5 Direct Memory Access (DMA) Buffer Start address 2141*3b58acd4Swdenk * register B channel 5 (read/write). 2142*3b58acd4Swdenk * DBTB5 Direct Memory Access (DMA) Buffer Transfer count 2143*3b58acd4Swdenk * register B channel 5 (read/write). 2144*3b58acd4Swdenk */ 2145*3b58acd4Swdenk 2146*3b58acd4Swdenk #define DMASp 0x00000020 /* DMA control reg. Space [byte] */ 2147*3b58acd4Swdenk 2148*3b58acd4Swdenk #define _DDAR(Nb) /* DMA Device Address Reg. */ \ 2149*3b58acd4Swdenk /* channel [0..5] */ \ 2150*3b58acd4Swdenk (0xB0000000 + (Nb)*DMASp) 2151*3b58acd4Swdenk #define _SetDCSR(Nb) /* Set DMA Control & Status Reg. */ \ 2152*3b58acd4Swdenk /* channel [0..5] (write) */ \ 2153*3b58acd4Swdenk (0xB0000004 + (Nb)*DMASp) 2154*3b58acd4Swdenk #define _ClrDCSR(Nb) /* Clear DMA Control & Status Reg. */ \ 2155*3b58acd4Swdenk /* channel [0..5] (write) */ \ 2156*3b58acd4Swdenk (0xB0000008 + (Nb)*DMASp) 2157*3b58acd4Swdenk #define _RdDCSR(Nb) /* Read DMA Control & Status Reg. */ \ 2158*3b58acd4Swdenk /* channel [0..5] (read) */ \ 2159*3b58acd4Swdenk (0xB000000C + (Nb)*DMASp) 2160*3b58acd4Swdenk #define _DBSA(Nb) /* DMA Buffer Start address reg. A */ \ 2161*3b58acd4Swdenk /* channel [0..5] */ \ 2162*3b58acd4Swdenk (0xB0000010 + (Nb)*DMASp) 2163*3b58acd4Swdenk #define _DBTA(Nb) /* DMA Buffer Transfer count */ \ 2164*3b58acd4Swdenk /* reg. A channel [0..5] */ \ 2165*3b58acd4Swdenk (0xB0000014 + (Nb)*DMASp) 2166*3b58acd4Swdenk #define _DBSB(Nb) /* DMA Buffer Start address reg. B */ \ 2167*3b58acd4Swdenk /* channel [0..5] */ \ 2168*3b58acd4Swdenk (0xB0000018 + (Nb)*DMASp) 2169*3b58acd4Swdenk #define _DBTB(Nb) /* DMA Buffer Transfer count */ \ 2170*3b58acd4Swdenk /* reg. B channel [0..5] */ \ 2171*3b58acd4Swdenk (0xB000001C + (Nb)*DMASp) 2172*3b58acd4Swdenk 2173*3b58acd4Swdenk #define _DDAR0 _DDAR (0) /* DMA Device Address Reg. */ 2174*3b58acd4Swdenk /* channel 0 */ 2175*3b58acd4Swdenk #define _SetDCSR0 _SetDCSR (0) /* Set DMA Control & Status Reg. */ 2176*3b58acd4Swdenk /* channel 0 (write) */ 2177*3b58acd4Swdenk #define _ClrDCSR0 _ClrDCSR (0) /* Clear DMA Control & Status Reg. */ 2178*3b58acd4Swdenk /* channel 0 (write) */ 2179*3b58acd4Swdenk #define _RdDCSR0 _RdDCSR (0) /* Read DMA Control & Status Reg. */ 2180*3b58acd4Swdenk /* channel 0 (read) */ 2181*3b58acd4Swdenk #define _DBSA0 _DBSA (0) /* DMA Buffer Start address reg. A */ 2182*3b58acd4Swdenk /* channel 0 */ 2183*3b58acd4Swdenk #define _DBTA0 _DBTA (0) /* DMA Buffer Transfer count */ 2184*3b58acd4Swdenk /* reg. A channel 0 */ 2185*3b58acd4Swdenk #define _DBSB0 _DBSB (0) /* DMA Buffer Start address reg. B */ 2186*3b58acd4Swdenk /* channel 0 */ 2187*3b58acd4Swdenk #define _DBTB0 _DBTB (0) /* DMA Buffer Transfer count */ 2188*3b58acd4Swdenk /* reg. B channel 0 */ 2189*3b58acd4Swdenk 2190*3b58acd4Swdenk #define _DDAR1 _DDAR (1) /* DMA Device Address Reg. */ 2191*3b58acd4Swdenk /* channel 1 */ 2192*3b58acd4Swdenk #define _SetDCSR1 _SetDCSR (1) /* Set DMA Control & Status Reg. */ 2193*3b58acd4Swdenk /* channel 1 (write) */ 2194*3b58acd4Swdenk #define _ClrDCSR1 _ClrDCSR (1) /* Clear DMA Control & Status Reg. */ 2195*3b58acd4Swdenk /* channel 1 (write) */ 2196*3b58acd4Swdenk #define _RdDCSR1 _RdDCSR (1) /* Read DMA Control & Status Reg. */ 2197*3b58acd4Swdenk /* channel 1 (read) */ 2198*3b58acd4Swdenk #define _DBSA1 _DBSA (1) /* DMA Buffer Start address reg. A */ 2199*3b58acd4Swdenk /* channel 1 */ 2200*3b58acd4Swdenk #define _DBTA1 _DBTA (1) /* DMA Buffer Transfer count */ 2201*3b58acd4Swdenk /* reg. A channel 1 */ 2202*3b58acd4Swdenk #define _DBSB1 _DBSB (1) /* DMA Buffer Start address reg. B */ 2203*3b58acd4Swdenk /* channel 1 */ 2204*3b58acd4Swdenk #define _DBTB1 _DBTB (1) /* DMA Buffer Transfer count */ 2205*3b58acd4Swdenk /* reg. B channel 1 */ 2206*3b58acd4Swdenk 2207*3b58acd4Swdenk #define _DDAR2 _DDAR (2) /* DMA Device Address Reg. */ 2208*3b58acd4Swdenk /* channel 2 */ 2209*3b58acd4Swdenk #define _SetDCSR2 _SetDCSR (2) /* Set DMA Control & Status Reg. */ 2210*3b58acd4Swdenk /* channel 2 (write) */ 2211*3b58acd4Swdenk #define _ClrDCSR2 _ClrDCSR (2) /* Clear DMA Control & Status Reg. */ 2212*3b58acd4Swdenk /* channel 2 (write) */ 2213*3b58acd4Swdenk #define _RdDCSR2 _RdDCSR (2) /* Read DMA Control & Status Reg. */ 2214*3b58acd4Swdenk /* channel 2 (read) */ 2215*3b58acd4Swdenk #define _DBSA2 _DBSA (2) /* DMA Buffer Start address reg. A */ 2216*3b58acd4Swdenk /* channel 2 */ 2217*3b58acd4Swdenk #define _DBTA2 _DBTA (2) /* DMA Buffer Transfer count */ 2218*3b58acd4Swdenk /* reg. A channel 2 */ 2219*3b58acd4Swdenk #define _DBSB2 _DBSB (2) /* DMA Buffer Start address reg. B */ 2220*3b58acd4Swdenk /* channel 2 */ 2221*3b58acd4Swdenk #define _DBTB2 _DBTB (2) /* DMA Buffer Transfer count */ 2222*3b58acd4Swdenk /* reg. B channel 2 */ 2223*3b58acd4Swdenk 2224*3b58acd4Swdenk #define _DDAR3 _DDAR (3) /* DMA Device Address Reg. */ 2225*3b58acd4Swdenk /* channel 3 */ 2226*3b58acd4Swdenk #define _SetDCSR3 _SetDCSR (3) /* Set DMA Control & Status Reg. */ 2227*3b58acd4Swdenk /* channel 3 (write) */ 2228*3b58acd4Swdenk #define _ClrDCSR3 _ClrDCSR (3) /* Clear DMA Control & Status Reg. */ 2229*3b58acd4Swdenk /* channel 3 (write) */ 2230*3b58acd4Swdenk #define _RdDCSR3 _RdDCSR (3) /* Read DMA Control & Status Reg. */ 2231*3b58acd4Swdenk /* channel 3 (read) */ 2232*3b58acd4Swdenk #define _DBSA3 _DBSA (3) /* DMA Buffer Start address reg. A */ 2233*3b58acd4Swdenk /* channel 3 */ 2234*3b58acd4Swdenk #define _DBTA3 _DBTA (3) /* DMA Buffer Transfer count */ 2235*3b58acd4Swdenk /* reg. A channel 3 */ 2236*3b58acd4Swdenk #define _DBSB3 _DBSB (3) /* DMA Buffer Start address reg. B */ 2237*3b58acd4Swdenk /* channel 3 */ 2238*3b58acd4Swdenk #define _DBTB3 _DBTB (3) /* DMA Buffer Transfer count */ 2239*3b58acd4Swdenk /* reg. B channel 3 */ 2240*3b58acd4Swdenk 2241*3b58acd4Swdenk #define _DDAR4 _DDAR (4) /* DMA Device Address Reg. */ 2242*3b58acd4Swdenk /* channel 4 */ 2243*3b58acd4Swdenk #define _SetDCSR4 _SetDCSR (4) /* Set DMA Control & Status Reg. */ 2244*3b58acd4Swdenk /* channel 4 (write) */ 2245*3b58acd4Swdenk #define _ClrDCSR4 _ClrDCSR (4) /* Clear DMA Control & Status Reg. */ 2246*3b58acd4Swdenk /* channel 4 (write) */ 2247*3b58acd4Swdenk #define _RdDCSR4 _RdDCSR (4) /* Read DMA Control & Status Reg. */ 2248*3b58acd4Swdenk /* channel 4 (read) */ 2249*3b58acd4Swdenk #define _DBSA4 _DBSA (4) /* DMA Buffer Start address reg. A */ 2250*3b58acd4Swdenk /* channel 4 */ 2251*3b58acd4Swdenk #define _DBTA4 _DBTA (4) /* DMA Buffer Transfer count */ 2252*3b58acd4Swdenk /* reg. A channel 4 */ 2253*3b58acd4Swdenk #define _DBSB4 _DBSB (4) /* DMA Buffer Start address reg. B */ 2254*3b58acd4Swdenk /* channel 4 */ 2255*3b58acd4Swdenk #define _DBTB4 _DBTB (4) /* DMA Buffer Transfer count */ 2256*3b58acd4Swdenk /* reg. B channel 4 */ 2257*3b58acd4Swdenk 2258*3b58acd4Swdenk #define _DDAR5 _DDAR (5) /* DMA Device Address Reg. */ 2259*3b58acd4Swdenk /* channel 5 */ 2260*3b58acd4Swdenk #define _SetDCSR5 _SetDCSR (5) /* Set DMA Control & Status Reg. */ 2261*3b58acd4Swdenk /* channel 5 (write) */ 2262*3b58acd4Swdenk #define _ClrDCSR5 _ClrDCSR (5) /* Clear DMA Control & Status Reg. */ 2263*3b58acd4Swdenk /* channel 5 (write) */ 2264*3b58acd4Swdenk #define _RdDCSR5 _RdDCSR (5) /* Read DMA Control & Status Reg. */ 2265*3b58acd4Swdenk /* channel 5 (read) */ 2266*3b58acd4Swdenk #define _DBSA5 _DBSA (5) /* DMA Buffer Start address reg. A */ 2267*3b58acd4Swdenk /* channel 5 */ 2268*3b58acd4Swdenk #define _DBTA5 _DBTA (5) /* DMA Buffer Transfer count */ 2269*3b58acd4Swdenk /* reg. A channel 5 */ 2270*3b58acd4Swdenk #define _DBSB5 _DBSB (5) /* DMA Buffer Start address reg. B */ 2271*3b58acd4Swdenk /* channel 5 */ 2272*3b58acd4Swdenk #define _DBTB5 _DBTB (5) /* DMA Buffer Transfer count */ 2273*3b58acd4Swdenk /* reg. B channel 5 */ 2274*3b58acd4Swdenk 2275*3b58acd4Swdenk #if LANGUAGE == C 2276*3b58acd4Swdenk 2277*3b58acd4Swdenk #define DDAR0 /* DMA Device Address Reg. */ \ 2278*3b58acd4Swdenk /* channel 0 */ \ 2279*3b58acd4Swdenk (*((volatile Word *) io_p2v (_DDAR0))) 2280*3b58acd4Swdenk #define SetDCSR0 /* Set DMA Control & Status Reg. */ \ 2281*3b58acd4Swdenk /* channel 0 (write) */ \ 2282*3b58acd4Swdenk (*((volatile Word *) io_p2v (_SetDCSR0))) 2283*3b58acd4Swdenk #define ClrDCSR0 /* Clear DMA Control & Status Reg. */ \ 2284*3b58acd4Swdenk /* channel 0 (write) */ \ 2285*3b58acd4Swdenk (*((volatile Word *) io_p2v (_ClrDCSR0))) 2286*3b58acd4Swdenk #define RdDCSR0 /* Read DMA Control & Status Reg. */ \ 2287*3b58acd4Swdenk /* channel 0 (read) */ \ 2288*3b58acd4Swdenk (*((volatile Word *) io_p2v (_RdDCSR0))) 2289*3b58acd4Swdenk #define DBSA0 /* DMA Buffer Start address reg. A */ \ 2290*3b58acd4Swdenk /* channel 0 */ \ 2291*3b58acd4Swdenk (*((volatile Address *) io_p2v (_DBSA0))) 2292*3b58acd4Swdenk #define DBTA0 /* DMA Buffer Transfer count */ \ 2293*3b58acd4Swdenk /* reg. A channel 0 */ \ 2294*3b58acd4Swdenk (*((volatile Word *) io_p2v (_DBTA0))) 2295*3b58acd4Swdenk #define DBSB0 /* DMA Buffer Start address reg. B */ \ 2296*3b58acd4Swdenk /* channel 0 */ \ 2297*3b58acd4Swdenk (*((volatile Address *) io_p2v (_DBSB0))) 2298*3b58acd4Swdenk #define DBTB0 /* DMA Buffer Transfer count */ \ 2299*3b58acd4Swdenk /* reg. B channel 0 */ \ 2300*3b58acd4Swdenk (*((volatile Word *) io_p2v (_DBTB0))) 2301*3b58acd4Swdenk 2302*3b58acd4Swdenk #define DDAR1 /* DMA Device Address Reg. */ \ 2303*3b58acd4Swdenk /* channel 1 */ \ 2304*3b58acd4Swdenk (*((volatile Word *) io_p2v (_DDAR1))) 2305*3b58acd4Swdenk #define SetDCSR1 /* Set DMA Control & Status Reg. */ \ 2306*3b58acd4Swdenk /* channel 1 (write) */ \ 2307*3b58acd4Swdenk (*((volatile Word *) io_p2v (_SetDCSR1))) 2308*3b58acd4Swdenk #define ClrDCSR1 /* Clear DMA Control & Status Reg. */ \ 2309*3b58acd4Swdenk /* channel 1 (write) */ \ 2310*3b58acd4Swdenk (*((volatile Word *) io_p2v (_ClrDCSR1))) 2311*3b58acd4Swdenk #define RdDCSR1 /* Read DMA Control & Status Reg. */ \ 2312*3b58acd4Swdenk /* channel 1 (read) */ \ 2313*3b58acd4Swdenk (*((volatile Word *) io_p2v (_RdDCSR1))) 2314*3b58acd4Swdenk #define DBSA1 /* DMA Buffer Start address reg. A */ \ 2315*3b58acd4Swdenk /* channel 1 */ \ 2316*3b58acd4Swdenk (*((volatile Address *) io_p2v (_DBSA1))) 2317*3b58acd4Swdenk #define DBTA1 /* DMA Buffer Transfer count */ \ 2318*3b58acd4Swdenk /* reg. A channel 1 */ \ 2319*3b58acd4Swdenk (*((volatile Word *) io_p2v (_DBTA1))) 2320*3b58acd4Swdenk #define DBSB1 /* DMA Buffer Start address reg. B */ \ 2321*3b58acd4Swdenk /* channel 1 */ \ 2322*3b58acd4Swdenk (*((volatile Address *) io_p2v (_DBSB1))) 2323*3b58acd4Swdenk #define DBTB1 /* DMA Buffer Transfer count */ \ 2324*3b58acd4Swdenk /* reg. B channel 1 */ \ 2325*3b58acd4Swdenk (*((volatile Word *) io_p2v (_DBTB1))) 2326*3b58acd4Swdenk 2327*3b58acd4Swdenk #define DDAR2 /* DMA Device Address Reg. */ \ 2328*3b58acd4Swdenk /* channel 2 */ \ 2329*3b58acd4Swdenk (*((volatile Word *) io_p2v (_DDAR2))) 2330*3b58acd4Swdenk #define SetDCSR2 /* Set DMA Control & Status Reg. */ \ 2331*3b58acd4Swdenk /* channel 2 (write) */ \ 2332*3b58acd4Swdenk (*((volatile Word *) io_p2v (_SetDCSR2))) 2333*3b58acd4Swdenk #define ClrDCSR2 /* Clear DMA Control & Status Reg. */ \ 2334*3b58acd4Swdenk /* channel 2 (write) */ \ 2335*3b58acd4Swdenk (*((volatile Word *) io_p2v (_ClrDCSR2))) 2336*3b58acd4Swdenk #define RdDCSR2 /* Read DMA Control & Status Reg. */ \ 2337*3b58acd4Swdenk /* channel 2 (read) */ \ 2338*3b58acd4Swdenk (*((volatile Word *) io_p2v (_RdDCSR2))) 2339*3b58acd4Swdenk #define DBSA2 /* DMA Buffer Start address reg. A */ \ 2340*3b58acd4Swdenk /* channel 2 */ \ 2341*3b58acd4Swdenk (*((volatile Address *) io_p2v (_DBSA2))) 2342*3b58acd4Swdenk #define DBTA2 /* DMA Buffer Transfer count */ \ 2343*3b58acd4Swdenk /* reg. A channel 2 */ \ 2344*3b58acd4Swdenk (*((volatile Word *) io_p2v (_DBTA2))) 2345*3b58acd4Swdenk #define DBSB2 /* DMA Buffer Start address reg. B */ \ 2346*3b58acd4Swdenk /* channel 2 */ \ 2347*3b58acd4Swdenk (*((volatile Address *) io_p2v (_DBSB2))) 2348*3b58acd4Swdenk #define DBTB2 /* DMA Buffer Transfer count */ \ 2349*3b58acd4Swdenk /* reg. B channel 2 */ \ 2350*3b58acd4Swdenk (*((volatile Word *) io_p2v (_DBTB2))) 2351*3b58acd4Swdenk 2352*3b58acd4Swdenk #define DDAR3 /* DMA Device Address Reg. */ \ 2353*3b58acd4Swdenk /* channel 3 */ \ 2354*3b58acd4Swdenk (*((volatile Word *) io_p2v (_DDAR3))) 2355*3b58acd4Swdenk #define SetDCSR3 /* Set DMA Control & Status Reg. */ \ 2356*3b58acd4Swdenk /* channel 3 (write) */ \ 2357*3b58acd4Swdenk (*((volatile Word *) io_p2v (_SetDCSR3))) 2358*3b58acd4Swdenk #define ClrDCSR3 /* Clear DMA Control & Status Reg. */ \ 2359*3b58acd4Swdenk /* channel 3 (write) */ \ 2360*3b58acd4Swdenk (*((volatile Word *) io_p2v (_ClrDCSR3))) 2361*3b58acd4Swdenk #define RdDCSR3 /* Read DMA Control & Status Reg. */ \ 2362*3b58acd4Swdenk /* channel 3 (read) */ \ 2363*3b58acd4Swdenk (*((volatile Word *) io_p2v (_RdDCSR3))) 2364*3b58acd4Swdenk #define DBSA3 /* DMA Buffer Start address reg. A */ \ 2365*3b58acd4Swdenk /* channel 3 */ \ 2366*3b58acd4Swdenk (*((volatile Address *) io_p2v (_DBSA3))) 2367*3b58acd4Swdenk #define DBTA3 /* DMA Buffer Transfer count */ \ 2368*3b58acd4Swdenk /* reg. A channel 3 */ \ 2369*3b58acd4Swdenk (*((volatile Word *) io_p2v (_DBTA3))) 2370*3b58acd4Swdenk #define DBSB3 /* DMA Buffer Start address reg. B */ \ 2371*3b58acd4Swdenk /* channel 3 */ \ 2372*3b58acd4Swdenk (*((volatile Address *) io_p2v (_DBSB3))) 2373*3b58acd4Swdenk #define DBTB3 /* DMA Buffer Transfer count */ \ 2374*3b58acd4Swdenk /* reg. B channel 3 */ \ 2375*3b58acd4Swdenk (*((volatile Word *) io_p2v (_DBTB3))) 2376*3b58acd4Swdenk 2377*3b58acd4Swdenk #define DDAR4 /* DMA Device Address Reg. */ \ 2378*3b58acd4Swdenk /* channel 4 */ \ 2379*3b58acd4Swdenk (*((volatile Word *) io_p2v (_DDAR4))) 2380*3b58acd4Swdenk #define SetDCSR4 /* Set DMA Control & Status Reg. */ \ 2381*3b58acd4Swdenk /* channel 4 (write) */ \ 2382*3b58acd4Swdenk (*((volatile Word *) io_p2v (_SetDCSR4))) 2383*3b58acd4Swdenk #define ClrDCSR4 /* Clear DMA Control & Status Reg. */ \ 2384*3b58acd4Swdenk /* channel 4 (write) */ \ 2385*3b58acd4Swdenk (*((volatile Word *) io_p2v (_ClrDCSR4))) 2386*3b58acd4Swdenk #define RdDCSR4 /* Read DMA Control & Status Reg. */ \ 2387*3b58acd4Swdenk /* channel 4 (read) */ \ 2388*3b58acd4Swdenk (*((volatile Word *) io_p2v (_RdDCSR4))) 2389*3b58acd4Swdenk #define DBSA4 /* DMA Buffer Start address reg. A */ \ 2390*3b58acd4Swdenk /* channel 4 */ \ 2391*3b58acd4Swdenk (*((volatile Address *) io_p2v (_DBSA4))) 2392*3b58acd4Swdenk #define DBTA4 /* DMA Buffer Transfer count */ \ 2393*3b58acd4Swdenk /* reg. A channel 4 */ \ 2394*3b58acd4Swdenk (*((volatile Word *) io_p2v (_DBTA4))) 2395*3b58acd4Swdenk #define DBSB4 /* DMA Buffer Start address reg. B */ \ 2396*3b58acd4Swdenk /* channel 4 */ \ 2397*3b58acd4Swdenk (*((volatile Address *) io_p2v (_DBSB4))) 2398*3b58acd4Swdenk #define DBTB4 /* DMA Buffer Transfer count */ \ 2399*3b58acd4Swdenk /* reg. B channel 4 */ \ 2400*3b58acd4Swdenk (*((volatile Word *) io_p2v (_DBTB4))) 2401*3b58acd4Swdenk 2402*3b58acd4Swdenk #define DDAR5 /* DMA Device Address Reg. */ \ 2403*3b58acd4Swdenk /* channel 5 */ \ 2404*3b58acd4Swdenk (*((volatile Word *) io_p2v (_DDAR5))) 2405*3b58acd4Swdenk #define SetDCSR5 /* Set DMA Control & Status Reg. */ \ 2406*3b58acd4Swdenk /* channel 5 (write) */ \ 2407*3b58acd4Swdenk (*((volatile Word *) io_p2v (_SetDCSR5))) 2408*3b58acd4Swdenk #define ClrDCSR5 /* Clear DMA Control & Status Reg. */ \ 2409*3b58acd4Swdenk /* channel 5 (write) */ \ 2410*3b58acd4Swdenk (*((volatile Word *) io_p2v (_ClrDCSR5))) 2411*3b58acd4Swdenk #define RdDCSR5 /* Read DMA Control & Status Reg. */ \ 2412*3b58acd4Swdenk /* channel 5 (read) */ \ 2413*3b58acd4Swdenk (*((volatile Word *) io_p2v (_RdDCSR5))) 2414*3b58acd4Swdenk #define DBSA5 /* DMA Buffer Start address reg. A */ \ 2415*3b58acd4Swdenk /* channel 5 */ \ 2416*3b58acd4Swdenk (*((volatile Address *) io_p2v (_DBSA5))) 2417*3b58acd4Swdenk #define DBTA5 /* DMA Buffer Transfer count */ \ 2418*3b58acd4Swdenk /* reg. A channel 5 */ \ 2419*3b58acd4Swdenk (*((volatile Word *) io_p2v (_DBTA5))) 2420*3b58acd4Swdenk #define DBSB5 /* DMA Buffer Start address reg. B */ \ 2421*3b58acd4Swdenk /* channel 5 */ \ 2422*3b58acd4Swdenk (*((volatile Address *) io_p2v (_DBSB5))) 2423*3b58acd4Swdenk #define DBTB5 /* DMA Buffer Transfer count */ \ 2424*3b58acd4Swdenk /* reg. B channel 5 */ \ 2425*3b58acd4Swdenk (*((volatile Word *) io_p2v (_DBTB5))) 2426*3b58acd4Swdenk 2427*3b58acd4Swdenk #endif /* LANGUAGE == C */ 2428*3b58acd4Swdenk 2429*3b58acd4Swdenk #define DDAR_RW 0x00000001 /* device data Read/Write */ 2430*3b58acd4Swdenk #define DDAR_DevWr (DDAR_RW*0) /* Device data Write */ 2431*3b58acd4Swdenk /* (memory -> device) */ 2432*3b58acd4Swdenk #define DDAR_DevRd (DDAR_RW*1) /* Device data Read */ 2433*3b58acd4Swdenk /* (device -> memory) */ 2434*3b58acd4Swdenk #define DDAR_E 0x00000002 /* big/little Endian device */ 2435*3b58acd4Swdenk #define DDAR_LtlEnd (DDAR_E*0) /* Little Endian device */ 2436*3b58acd4Swdenk #define DDAR_BigEnd (DDAR_E*1) /* Big Endian device */ 2437*3b58acd4Swdenk #define DDAR_BS 0x00000004 /* device Burst Size */ 2438*3b58acd4Swdenk #define DDAR_Brst4 (DDAR_BS*0) /* Burst-of-4 device */ 2439*3b58acd4Swdenk #define DDAR_Brst8 (DDAR_BS*1) /* Burst-of-8 device */ 2440*3b58acd4Swdenk #define DDAR_DW 0x00000008 /* device Data Width */ 2441*3b58acd4Swdenk #define DDAR_8BitDev (DDAR_DW*0) /* 8-Bit Device */ 2442*3b58acd4Swdenk #define DDAR_16BitDev (DDAR_DW*1) /* 16-Bit Device */ 2443*3b58acd4Swdenk #define DDAR_DS Fld (4, 4) /* Device Select */ 2444*3b58acd4Swdenk #define DDAR_Ser0UDCTr /* Ser. port 0 UDC Transmit */ \ 2445*3b58acd4Swdenk (0x0 << FShft (DDAR_DS)) 2446*3b58acd4Swdenk #define DDAR_Ser0UDCRc /* Ser. port 0 UDC Receive */ \ 2447*3b58acd4Swdenk (0x1 << FShft (DDAR_DS)) 2448*3b58acd4Swdenk #define DDAR_Ser1SDLCTr /* Ser. port 1 SDLC Transmit */ \ 2449*3b58acd4Swdenk (0x2 << FShft (DDAR_DS)) 2450*3b58acd4Swdenk #define DDAR_Ser1SDLCRc /* Ser. port 1 SDLC Receive */ \ 2451*3b58acd4Swdenk (0x3 << FShft (DDAR_DS)) 2452*3b58acd4Swdenk #define DDAR_Ser1UARTTr /* Ser. port 1 UART Transmit */ \ 2453*3b58acd4Swdenk (0x4 << FShft (DDAR_DS)) 2454*3b58acd4Swdenk #define DDAR_Ser1UARTRc /* Ser. port 1 UART Receive */ \ 2455*3b58acd4Swdenk (0x5 << FShft (DDAR_DS)) 2456*3b58acd4Swdenk #define DDAR_Ser2ICPTr /* Ser. port 2 ICP Transmit */ \ 2457*3b58acd4Swdenk (0x6 << FShft (DDAR_DS)) 2458*3b58acd4Swdenk #define DDAR_Ser2ICPRc /* Ser. port 2 ICP Receive */ \ 2459*3b58acd4Swdenk (0x7 << FShft (DDAR_DS)) 2460*3b58acd4Swdenk #define DDAR_Ser3UARTTr /* Ser. port 3 UART Transmit */ \ 2461*3b58acd4Swdenk (0x8 << FShft (DDAR_DS)) 2462*3b58acd4Swdenk #define DDAR_Ser3UARTRc /* Ser. port 3 UART Receive */ \ 2463*3b58acd4Swdenk (0x9 << FShft (DDAR_DS)) 2464*3b58acd4Swdenk #define DDAR_Ser4MCP0Tr /* Ser. port 4 MCP 0 Transmit */ \ 2465*3b58acd4Swdenk /* (audio) */ \ 2466*3b58acd4Swdenk (0xA << FShft (DDAR_DS)) 2467*3b58acd4Swdenk #define DDAR_Ser4MCP0Rc /* Ser. port 4 MCP 0 Receive */ \ 2468*3b58acd4Swdenk /* (audio) */ \ 2469*3b58acd4Swdenk (0xB << FShft (DDAR_DS)) 2470*3b58acd4Swdenk #define DDAR_Ser4MCP1Tr /* Ser. port 4 MCP 1 Transmit */ \ 2471*3b58acd4Swdenk /* (telecom) */ \ 2472*3b58acd4Swdenk (0xC << FShft (DDAR_DS)) 2473*3b58acd4Swdenk #define DDAR_Ser4MCP1Rc /* Ser. port 4 MCP 1 Receive */ \ 2474*3b58acd4Swdenk /* (telecom) */ \ 2475*3b58acd4Swdenk (0xD << FShft (DDAR_DS)) 2476*3b58acd4Swdenk #define DDAR_Ser4SSPTr /* Ser. port 4 SSP Transmit */ \ 2477*3b58acd4Swdenk (0xE << FShft (DDAR_DS)) 2478*3b58acd4Swdenk #define DDAR_Ser4SSPRc /* Ser. port 4 SSP Receive */ \ 2479*3b58acd4Swdenk (0xF << FShft (DDAR_DS)) 2480*3b58acd4Swdenk #define DDAR_DA Fld (24, 8) /* Device Address */ 2481*3b58acd4Swdenk #define DDAR_DevAdd(Add) /* Device Address */ \ 2482*3b58acd4Swdenk (((Add) & 0xF0000000) | \ 2483*3b58acd4Swdenk (((Add) & 0X003FFFFC) << (FShft (DDAR_DA) - 2))) 2484*3b58acd4Swdenk #define DDAR_Ser0UDCWr /* Ser. port 0 UDC Write */ \ 2485*3b58acd4Swdenk (DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \ 2486*3b58acd4Swdenk DDAR_Ser0UDCTr + DDAR_DevAdd (_Ser0UDCDR)) 2487*3b58acd4Swdenk #define DDAR_Ser0UDCRd /* Ser. port 0 UDC Read */ \ 2488*3b58acd4Swdenk (DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \ 2489*3b58acd4Swdenk DDAR_Ser0UDCRc + DDAR_DevAdd (_Ser0UDCDR)) 2490*3b58acd4Swdenk #define DDAR_Ser1UARTWr /* Ser. port 1 UART Write */ \ 2491*3b58acd4Swdenk (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \ 2492*3b58acd4Swdenk DDAR_Ser1UARTTr + DDAR_DevAdd (_Ser1UTDR)) 2493*3b58acd4Swdenk #define DDAR_Ser1UARTRd /* Ser. port 1 UART Read */ \ 2494*3b58acd4Swdenk (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \ 2495*3b58acd4Swdenk DDAR_Ser1UARTRc + DDAR_DevAdd (_Ser1UTDR)) 2496*3b58acd4Swdenk #define DDAR_Ser1SDLCWr /* Ser. port 1 SDLC Write */ \ 2497*3b58acd4Swdenk (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \ 2498*3b58acd4Swdenk DDAR_Ser1SDLCTr + DDAR_DevAdd (_Ser1SDDR)) 2499*3b58acd4Swdenk #define DDAR_Ser1SDLCRd /* Ser. port 1 SDLC Read */ \ 2500*3b58acd4Swdenk (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \ 2501*3b58acd4Swdenk DDAR_Ser1SDLCRc + DDAR_DevAdd (_Ser1SDDR)) 2502*3b58acd4Swdenk #define DDAR_Ser2UARTWr /* Ser. port 2 UART Write */ \ 2503*3b58acd4Swdenk (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \ 2504*3b58acd4Swdenk DDAR_Ser2ICPTr + DDAR_DevAdd (_Ser2UTDR)) 2505*3b58acd4Swdenk #define DDAR_Ser2UARTRd /* Ser. port 2 UART Read */ \ 2506*3b58acd4Swdenk (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \ 2507*3b58acd4Swdenk DDAR_Ser2ICPRc + DDAR_DevAdd (_Ser2UTDR)) 2508*3b58acd4Swdenk #define DDAR_Ser2HSSPWr /* Ser. port 2 HSSP Write */ \ 2509*3b58acd4Swdenk (DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \ 2510*3b58acd4Swdenk DDAR_Ser2ICPTr + DDAR_DevAdd (_Ser2HSDR)) 2511*3b58acd4Swdenk #define DDAR_Ser2HSSPRd /* Ser. port 2 HSSP Read */ \ 2512*3b58acd4Swdenk (DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \ 2513*3b58acd4Swdenk DDAR_Ser2ICPRc + DDAR_DevAdd (_Ser2HSDR)) 2514*3b58acd4Swdenk #define DDAR_Ser3UARTWr /* Ser. port 3 UART Write */ \ 2515*3b58acd4Swdenk (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \ 2516*3b58acd4Swdenk DDAR_Ser3UARTTr + DDAR_DevAdd (_Ser3UTDR)) 2517*3b58acd4Swdenk #define DDAR_Ser3UARTRd /* Ser. port 3 UART Read */ \ 2518*3b58acd4Swdenk (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \ 2519*3b58acd4Swdenk DDAR_Ser3UARTRc + DDAR_DevAdd (_Ser3UTDR)) 2520*3b58acd4Swdenk #define DDAR_Ser4MCP0Wr /* Ser. port 4 MCP 0 Write (audio) */ \ 2521*3b58acd4Swdenk (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \ 2522*3b58acd4Swdenk DDAR_Ser4MCP0Tr + DDAR_DevAdd (_Ser4MCDR0)) 2523*3b58acd4Swdenk #define DDAR_Ser4MCP0Rd /* Ser. port 4 MCP 0 Read (audio) */ \ 2524*3b58acd4Swdenk (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \ 2525*3b58acd4Swdenk DDAR_Ser4MCP0Rc + DDAR_DevAdd (_Ser4MCDR0)) 2526*3b58acd4Swdenk #define DDAR_Ser4MCP1Wr /* Ser. port 4 MCP 1 Write */ \ 2527*3b58acd4Swdenk /* (telecom) */ \ 2528*3b58acd4Swdenk (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \ 2529*3b58acd4Swdenk DDAR_Ser4MCP1Tr + DDAR_DevAdd (_Ser4MCDR1)) 2530*3b58acd4Swdenk #define DDAR_Ser4MCP1Rd /* Ser. port 4 MCP 1 Read */ \ 2531*3b58acd4Swdenk /* (telecom) */ \ 2532*3b58acd4Swdenk (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \ 2533*3b58acd4Swdenk DDAR_Ser4MCP1Rc + DDAR_DevAdd (_Ser4MCDR1)) 2534*3b58acd4Swdenk #define DDAR_Ser4SSPWr /* Ser. port 4 SSP Write (16 bits) */ \ 2535*3b58acd4Swdenk (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \ 2536*3b58acd4Swdenk DDAR_Ser4SSPTr + DDAR_DevAdd (_Ser4SSDR)) 2537*3b58acd4Swdenk #define DDAR_Ser4SSPRd /* Ser. port 4 SSP Read (16 bits) */ \ 2538*3b58acd4Swdenk (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \ 2539*3b58acd4Swdenk DDAR_Ser4SSPRc + DDAR_DevAdd (_Ser4SSDR)) 2540*3b58acd4Swdenk 2541*3b58acd4Swdenk #define DCSR_RUN 0x00000001 /* DMA RUNing */ 2542*3b58acd4Swdenk #define DCSR_IE 0x00000002 /* DMA Interrupt Enable */ 2543*3b58acd4Swdenk #define DCSR_ERROR 0x00000004 /* DMA ERROR */ 2544*3b58acd4Swdenk #define DCSR_DONEA 0x00000008 /* DONE DMA transfer buffer A */ 2545*3b58acd4Swdenk #define DCSR_STRTA 0x00000010 /* STaRTed DMA transfer buffer A */ 2546*3b58acd4Swdenk #define DCSR_DONEB 0x00000020 /* DONE DMA transfer buffer B */ 2547*3b58acd4Swdenk #define DCSR_STRTB 0x00000040 /* STaRTed DMA transfer buffer B */ 2548*3b58acd4Swdenk #define DCSR_BIU 0x00000080 /* DMA Buffer In Use */ 2549*3b58acd4Swdenk #define DCSR_BufA (DCSR_BIU*0) /* DMA Buffer A in use */ 2550*3b58acd4Swdenk #define DCSR_BufB (DCSR_BIU*1) /* DMA Buffer B in use */ 2551*3b58acd4Swdenk 2552*3b58acd4Swdenk #define DBT_TC Fld (13, 0) /* Transfer Count */ 2553*3b58acd4Swdenk #define DBTA_TCA DBT_TC /* Transfer Count buffer A */ 2554*3b58acd4Swdenk #define DBTB_TCB DBT_TC /* Transfer Count buffer B */ 2555*3b58acd4Swdenk 2556*3b58acd4Swdenk 2557*3b58acd4Swdenk /* 2558*3b58acd4Swdenk * Liquid Crystal Display (LCD) control registers 2559*3b58acd4Swdenk * 2560*3b58acd4Swdenk * Registers 2561*3b58acd4Swdenk * LCCR0 Liquid Crystal Display (LCD) Control Register 0 2562*3b58acd4Swdenk * (read/write). 2563*3b58acd4Swdenk * [Bits LDM, BAM, and ERM are only implemented in 2564*3b58acd4Swdenk * versions 2.0 (rev. = 8) and higher of the StrongARM 2565*3b58acd4Swdenk * SA-1100.] 2566*3b58acd4Swdenk * LCSR Liquid Crystal Display (LCD) Status Register 2567*3b58acd4Swdenk * (read/write). 2568*3b58acd4Swdenk * [Bit LDD can be only read in versions 1.0 (rev. = 1) 2569*3b58acd4Swdenk * and 1.1 (rev. = 2) of the StrongARM SA-1100, it can be 2570*3b58acd4Swdenk * read and written (cleared) in versions 2.0 (rev. = 8) 2571*3b58acd4Swdenk * and higher.] 2572*3b58acd4Swdenk * DBAR1 Liquid Crystal Display (LCD) Direct Memory Access 2573*3b58acd4Swdenk * (DMA) Base Address Register channel 1 (read/write). 2574*3b58acd4Swdenk * DCAR1 Liquid Crystal Display (LCD) Direct Memory Access 2575*3b58acd4Swdenk * (DMA) Current Address Register channel 1 (read). 2576*3b58acd4Swdenk * DBAR2 Liquid Crystal Display (LCD) Direct Memory Access 2577*3b58acd4Swdenk * (DMA) Base Address Register channel 2 (read/write). 2578*3b58acd4Swdenk * DCAR2 Liquid Crystal Display (LCD) Direct Memory Access 2579*3b58acd4Swdenk * (DMA) Current Address Register channel 2 (read). 2580*3b58acd4Swdenk * LCCR1 Liquid Crystal Display (LCD) Control Register 1 2581*3b58acd4Swdenk * (read/write). 2582*3b58acd4Swdenk * [The LCCR1 register can be only written in 2583*3b58acd4Swdenk * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the 2584*3b58acd4Swdenk * StrongARM SA-1100, it can be written and read in 2585*3b58acd4Swdenk * versions 2.0 (rev. = 8) and higher.] 2586*3b58acd4Swdenk * LCCR2 Liquid Crystal Display (LCD) Control Register 2 2587*3b58acd4Swdenk * (read/write). 2588*3b58acd4Swdenk * [The LCCR1 register can be only written in 2589*3b58acd4Swdenk * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the 2590*3b58acd4Swdenk * StrongARM SA-1100, it can be written and read in 2591*3b58acd4Swdenk * versions 2.0 (rev. = 8) and higher.] 2592*3b58acd4Swdenk * LCCR3 Liquid Crystal Display (LCD) Control Register 3 2593*3b58acd4Swdenk * (read/write). 2594*3b58acd4Swdenk * [The LCCR1 register can be only written in 2595*3b58acd4Swdenk * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the 2596*3b58acd4Swdenk * StrongARM SA-1100, it can be written and read in 2597*3b58acd4Swdenk * versions 2.0 (rev. = 8) and higher. Bit PCP is only 2598*3b58acd4Swdenk * implemented in versions 2.0 (rev. = 8) and higher of 2599*3b58acd4Swdenk * the StrongARM SA-1100.] 2600*3b58acd4Swdenk * 2601*3b58acd4Swdenk * Clocks 2602*3b58acd4Swdenk * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). 2603*3b58acd4Swdenk * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2). 2604*3b58acd4Swdenk * fpix, Tpix Frequency, period of the pixel clock. 2605*3b58acd4Swdenk * fln, Tln Frequency, period of the line clock. 2606*3b58acd4Swdenk * fac, Tac Frequency, period of the AC bias clock. 2607*3b58acd4Swdenk */ 2608*3b58acd4Swdenk 2609*3b58acd4Swdenk #define LCD_PEntrySp 2 /* LCD Palette Entry Space [byte] */ 2610*3b58acd4Swdenk #define LCD_4BitPSp /* LCD 4-Bit pixel Palette Space */ \ 2611*3b58acd4Swdenk /* [byte] */ \ 2612*3b58acd4Swdenk (16*LCD_PEntrySp) 2613*3b58acd4Swdenk #define LCD_8BitPSp /* LCD 8-Bit pixel Palette Space */ \ 2614*3b58acd4Swdenk /* [byte] */ \ 2615*3b58acd4Swdenk (256*LCD_PEntrySp) 2616*3b58acd4Swdenk #define LCD_12_16BitPSp /* LCD 12/16-Bit pixel */ \ 2617*3b58acd4Swdenk /* dummy-Palette Space [byte] */ \ 2618*3b58acd4Swdenk (16*LCD_PEntrySp) 2619*3b58acd4Swdenk 2620*3b58acd4Swdenk #define LCD_PGrey Fld (4, 0) /* LCD Palette entry Grey value */ 2621*3b58acd4Swdenk #define LCD_PBlue Fld (4, 0) /* LCD Palette entry Blue value */ 2622*3b58acd4Swdenk #define LCD_PGreen Fld (4, 4) /* LCD Palette entry Green value */ 2623*3b58acd4Swdenk #define LCD_PRed Fld (4, 8) /* LCD Palette entry Red value */ 2624*3b58acd4Swdenk #define LCD_PBS Fld (2, 12) /* LCD Pixel Bit Size */ 2625*3b58acd4Swdenk #define LCD_4Bit /* LCD 4-Bit pixel mode */ \ 2626*3b58acd4Swdenk (0 << FShft (LCD_PBS)) 2627*3b58acd4Swdenk #define LCD_8Bit /* LCD 8-Bit pixel mode */ \ 2628*3b58acd4Swdenk (1 << FShft (LCD_PBS)) 2629*3b58acd4Swdenk #define LCD_12_16Bit /* LCD 12/16-Bit pixel mode */ \ 2630*3b58acd4Swdenk (2 << FShft (LCD_PBS)) 2631*3b58acd4Swdenk 2632*3b58acd4Swdenk #define LCD_Int0_0 0x0 /* LCD Intensity = 0.0% = 0 */ 2633*3b58acd4Swdenk #define LCD_Int11_1 0x1 /* LCD Intensity = 11.1% = 1/9 */ 2634*3b58acd4Swdenk #define LCD_Int20_0 0x2 /* LCD Intensity = 20.0% = 1/5 */ 2635*3b58acd4Swdenk #define LCD_Int26_7 0x3 /* LCD Intensity = 26.7% = 4/15 */ 2636*3b58acd4Swdenk #define LCD_Int33_3 0x4 /* LCD Intensity = 33.3% = 3/9 */ 2637*3b58acd4Swdenk #define LCD_Int40_0 0x5 /* LCD Intensity = 40.0% = 2/5 */ 2638*3b58acd4Swdenk #define LCD_Int44_4 0x6 /* LCD Intensity = 44.4% = 4/9 */ 2639*3b58acd4Swdenk #define LCD_Int50_0 0x7 /* LCD Intensity = 50.0% = 1/2 */ 2640*3b58acd4Swdenk #define LCD_Int55_6 0x8 /* LCD Intensity = 55.6% = 5/9 */ 2641*3b58acd4Swdenk #define LCD_Int60_0 0x9 /* LCD Intensity = 60.0% = 3/5 */ 2642*3b58acd4Swdenk #define LCD_Int66_7 0xA /* LCD Intensity = 66.7% = 6/9 */ 2643*3b58acd4Swdenk #define LCD_Int73_3 0xB /* LCD Intensity = 73.3% = 11/15 */ 2644*3b58acd4Swdenk #define LCD_Int80_0 0xC /* LCD Intensity = 80.0% = 4/5 */ 2645*3b58acd4Swdenk #define LCD_Int88_9 0xD /* LCD Intensity = 88.9% = 8/9 */ 2646*3b58acd4Swdenk #define LCD_Int100_0 0xE /* LCD Intensity = 100.0% = 1 */ 2647*3b58acd4Swdenk #define LCD_Int100_0A 0xF /* LCD Intensity = 100.0% = 1 */ 2648*3b58acd4Swdenk /* (Alternative) */ 2649*3b58acd4Swdenk 2650*3b58acd4Swdenk #define _LCCR0 0xB0100000 /* LCD Control Reg. 0 */ 2651*3b58acd4Swdenk #define _LCSR 0xB0100004 /* LCD Status Reg. */ 2652*3b58acd4Swdenk #define _DBAR1 0xB0100010 /* LCD DMA Base Address Reg. */ 2653*3b58acd4Swdenk /* channel 1 */ 2654*3b58acd4Swdenk #define _DCAR1 0xB0100014 /* LCD DMA Current Address Reg. */ 2655*3b58acd4Swdenk /* channel 1 */ 2656*3b58acd4Swdenk #define _DBAR2 0xB0100018 /* LCD DMA Base Address Reg. */ 2657*3b58acd4Swdenk /* channel 2 */ 2658*3b58acd4Swdenk #define _DCAR2 0xB010001C /* LCD DMA Current Address Reg. */ 2659*3b58acd4Swdenk /* channel 2 */ 2660*3b58acd4Swdenk #define _LCCR1 0xB0100020 /* LCD Control Reg. 1 */ 2661*3b58acd4Swdenk #define _LCCR2 0xB0100024 /* LCD Control Reg. 2 */ 2662*3b58acd4Swdenk #define _LCCR3 0xB0100028 /* LCD Control Reg. 3 */ 2663*3b58acd4Swdenk 2664*3b58acd4Swdenk #if LANGUAGE == C 2665*3b58acd4Swdenk #define LCCR0 /* LCD Control Reg. 0 */ \ 2666*3b58acd4Swdenk (*((volatile Word *) io_p2v (_LCCR0))) 2667*3b58acd4Swdenk #define LCSR /* LCD Status Reg. */ \ 2668*3b58acd4Swdenk (*((volatile Word *) io_p2v (_LCSR))) 2669*3b58acd4Swdenk #define DBAR1 /* LCD DMA Base Address Reg. */ \ 2670*3b58acd4Swdenk /* channel 1 */ \ 2671*3b58acd4Swdenk (*((volatile Address *) io_p2v (_DBAR1))) 2672*3b58acd4Swdenk #define DCAR1 /* LCD DMA Current Address Reg. */ \ 2673*3b58acd4Swdenk /* channel 1 */ \ 2674*3b58acd4Swdenk (*((volatile Address *) io_p2v (_DCAR1))) 2675*3b58acd4Swdenk #define DBAR2 /* LCD DMA Base Address Reg. */ \ 2676*3b58acd4Swdenk /* channel 2 */ \ 2677*3b58acd4Swdenk (*((volatile Address *) io_p2v (_DBAR2))) 2678*3b58acd4Swdenk #define DCAR2 /* LCD DMA Current Address Reg. */ \ 2679*3b58acd4Swdenk /* channel 2 */ \ 2680*3b58acd4Swdenk (*((volatile Address *) io_p2v (_DCAR2))) 2681*3b58acd4Swdenk #define LCCR1 /* LCD Control Reg. 1 */ \ 2682*3b58acd4Swdenk (*((volatile Word *) io_p2v (_LCCR1))) 2683*3b58acd4Swdenk #define LCCR2 /* LCD Control Reg. 2 */ \ 2684*3b58acd4Swdenk (*((volatile Word *) io_p2v (_LCCR2))) 2685*3b58acd4Swdenk #define LCCR3 /* LCD Control Reg. 3 */ \ 2686*3b58acd4Swdenk (*((volatile Word *) io_p2v (_LCCR3))) 2687*3b58acd4Swdenk #endif /* LANGUAGE == C */ 2688*3b58acd4Swdenk 2689*3b58acd4Swdenk #define LCCR0_LEN 0x00000001 /* LCD ENable */ 2690*3b58acd4Swdenk #define LCCR0_CMS 0x00000002 /* Color/Monochrome display Select */ 2691*3b58acd4Swdenk #define LCCR0_Color (LCCR0_CMS*0) /* Color display */ 2692*3b58acd4Swdenk #define LCCR0_Mono (LCCR0_CMS*1) /* Monochrome display */ 2693*3b58acd4Swdenk #define LCCR0_SDS 0x00000004 /* Single/Dual panel display */ 2694*3b58acd4Swdenk /* Select */ 2695*3b58acd4Swdenk #define LCCR0_Sngl (LCCR0_SDS*0) /* Single panel display */ 2696*3b58acd4Swdenk #define LCCR0_Dual (LCCR0_SDS*1) /* Dual panel display */ 2697*3b58acd4Swdenk #define LCCR0_LDM 0x00000008 /* LCD Disable done (LDD) */ 2698*3b58acd4Swdenk /* interrupt Mask (disable) */ 2699*3b58acd4Swdenk #define LCCR0_BAM 0x00000010 /* Base Address update (BAU) */ 2700*3b58acd4Swdenk /* interrupt Mask (disable) */ 2701*3b58acd4Swdenk #define LCCR0_ERM 0x00000020 /* LCD ERror (BER, IOL, IUL, IOU, */ 2702*3b58acd4Swdenk /* IUU, OOL, OUL, OOU, and OUU) */ 2703*3b58acd4Swdenk /* interrupt Mask (disable) */ 2704*3b58acd4Swdenk #define LCCR0_PAS 0x00000080 /* Passive/Active display Select */ 2705*3b58acd4Swdenk #define LCCR0_Pas (LCCR0_PAS*0) /* Passive display (STN) */ 2706*3b58acd4Swdenk #define LCCR0_Act (LCCR0_PAS*1) /* Active display (TFT) */ 2707*3b58acd4Swdenk #define LCCR0_BLE 0x00000100 /* Big/Little Endian select */ 2708*3b58acd4Swdenk #define LCCR0_LtlEnd (LCCR0_BLE*0) /* Little Endian frame buffer */ 2709*3b58acd4Swdenk #define LCCR0_BigEnd (LCCR0_BLE*1) /* Big Endian frame buffer */ 2710*3b58acd4Swdenk #define LCCR0_DPD 0x00000200 /* Double Pixel Data (monochrome */ 2711*3b58acd4Swdenk /* display mode) */ 2712*3b58acd4Swdenk #define LCCR0_4PixMono (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome */ 2713*3b58acd4Swdenk /* display */ 2714*3b58acd4Swdenk #define LCCR0_8PixMono (LCCR0_DPD*1) /* 8-Pixel/clock Monochrome */ 2715*3b58acd4Swdenk /* display */ 2716*3b58acd4Swdenk #define LCCR0_PDD Fld (8, 12) /* Palette DMA request Delay */ 2717*3b58acd4Swdenk /* [Tmem] */ 2718*3b58acd4Swdenk #define LCCR0_DMADel(Tcpu) /* palette DMA request Delay */ \ 2719*3b58acd4Swdenk /* [0..510 Tcpu] */ \ 2720*3b58acd4Swdenk ((Tcpu)/2 << FShft (LCCR0_PDD)) 2721*3b58acd4Swdenk 2722*3b58acd4Swdenk #define LCSR_LDD 0x00000001 /* LCD Disable Done */ 2723*3b58acd4Swdenk #define LCSR_BAU 0x00000002 /* Base Address Update (read) */ 2724*3b58acd4Swdenk #define LCSR_BER 0x00000004 /* Bus ERror */ 2725*3b58acd4Swdenk #define LCSR_ABC 0x00000008 /* AC Bias clock Count */ 2726*3b58acd4Swdenk #define LCSR_IOL 0x00000010 /* Input FIFO Over-run Lower */ 2727*3b58acd4Swdenk /* panel */ 2728*3b58acd4Swdenk #define LCSR_IUL 0x00000020 /* Input FIFO Under-run Lower */ 2729*3b58acd4Swdenk /* panel */ 2730*3b58acd4Swdenk #define LCSR_IOU 0x00000040 /* Input FIFO Over-run Upper */ 2731*3b58acd4Swdenk /* panel */ 2732*3b58acd4Swdenk #define LCSR_IUU 0x00000080 /* Input FIFO Under-run Upper */ 2733*3b58acd4Swdenk /* panel */ 2734*3b58acd4Swdenk #define LCSR_OOL 0x00000100 /* Output FIFO Over-run Lower */ 2735*3b58acd4Swdenk /* panel */ 2736*3b58acd4Swdenk #define LCSR_OUL 0x00000200 /* Output FIFO Under-run Lower */ 2737*3b58acd4Swdenk /* panel */ 2738*3b58acd4Swdenk #define LCSR_OOU 0x00000400 /* Output FIFO Over-run Upper */ 2739*3b58acd4Swdenk /* panel */ 2740*3b58acd4Swdenk #define LCSR_OUU 0x00000800 /* Output FIFO Under-run Upper */ 2741*3b58acd4Swdenk /* panel */ 2742*3b58acd4Swdenk 2743*3b58acd4Swdenk #define LCCR1_PPL Fld (6, 4) /* Pixels Per Line/16 - 1 */ 2744*3b58acd4Swdenk #define LCCR1_DisWdth(Pixel) /* Display Width [16..1024 pix.] */ \ 2745*3b58acd4Swdenk (((Pixel) - 16)/16 << FShft (LCCR1_PPL)) 2746*3b58acd4Swdenk #define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */ 2747*3b58acd4Swdenk /* pulse Width - 2 [Tpix] (L_LCLK) */ 2748*3b58acd4Swdenk #define LCCR1_HorSnchWdth(Tpix) /* Horizontal Synchronization */ \ 2749*3b58acd4Swdenk /* pulse Width [2..65 Tpix] */ \ 2750*3b58acd4Swdenk (((Tpix) - 2) << FShft (LCCR1_HSW)) 2751*3b58acd4Swdenk #define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait */ 2752*3b58acd4Swdenk /* count - 1 [Tpix] */ 2753*3b58acd4Swdenk #define LCCR1_EndLnDel(Tpix) /* End-of-Line Delay */ \ 2754*3b58acd4Swdenk /* [1..256 Tpix] */ \ 2755*3b58acd4Swdenk (((Tpix) - 1) << FShft (LCCR1_ELW)) 2756*3b58acd4Swdenk #define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */ 2757*3b58acd4Swdenk /* Wait count - 1 [Tpix] */ 2758*3b58acd4Swdenk #define LCCR1_BegLnDel(Tpix) /* Beginning-of-Line Delay */ \ 2759*3b58acd4Swdenk /* [1..256 Tpix] */ \ 2760*3b58acd4Swdenk (((Tpix) - 1) << FShft (LCCR1_BLW)) 2761*3b58acd4Swdenk 2762*3b58acd4Swdenk #define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */ 2763*3b58acd4Swdenk #define LCCR2_DisHght(Line) /* Display Height [1..1024 lines] */ \ 2764*3b58acd4Swdenk (((Line) - 1) << FShft (LCCR2_LPP)) 2765*3b58acd4Swdenk #define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */ 2766*3b58acd4Swdenk /* Width - 1 [Tln] (L_FCLK) */ 2767*3b58acd4Swdenk #define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \ 2768*3b58acd4Swdenk /* Width [1..64 Tln] */ \ 2769*3b58acd4Swdenk (((Tln) - 1) << FShft (LCCR2_VSW)) 2770*3b58acd4Swdenk #define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */ 2771*3b58acd4Swdenk /* count [Tln] */ 2772*3b58acd4Swdenk #define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \ 2773*3b58acd4Swdenk /* [0..255 Tln] */ \ 2774*3b58acd4Swdenk ((Tln) << FShft (LCCR2_EFW)) 2775*3b58acd4Swdenk #define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */ 2776*3b58acd4Swdenk /* Wait count [Tln] */ 2777*3b58acd4Swdenk #define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \ 2778*3b58acd4Swdenk /* [0..255 Tln] */ \ 2779*3b58acd4Swdenk ((Tln) << FShft (LCCR2_BFW)) 2780*3b58acd4Swdenk 2781*3b58acd4Swdenk #define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor/2 - 2 */ 2782*3b58acd4Swdenk /* [1..255] (L_PCLK) */ 2783*3b58acd4Swdenk /* fpix = fcpu/(2*(PCD + 2)) */ 2784*3b58acd4Swdenk /* Tpix = 2*(PCD + 2)*Tcpu */ 2785*3b58acd4Swdenk #define LCCR3_PixClkDiv(Div) /* Pixel Clock Divisor [6..514] */ \ 2786*3b58acd4Swdenk (((Div) - 4)/2 << FShft (LCCR3_PCD)) 2787*3b58acd4Swdenk /* fpix = fcpu/(2*Floor (Div/2)) */ 2788*3b58acd4Swdenk /* Tpix = 2*Floor (Div/2)*Tcpu */ 2789*3b58acd4Swdenk #define LCCR3_CeilPixClkDiv(Div) /* Ceil. of PixClkDiv [6..514] */ \ 2790*3b58acd4Swdenk (((Div) - 3)/2 << FShft (LCCR3_PCD)) 2791*3b58acd4Swdenk /* fpix = fcpu/(2*Ceil (Div/2)) */ 2792*3b58acd4Swdenk /* Tpix = 2*Ceil (Div/2)*Tcpu */ 2793*3b58acd4Swdenk #define LCCR3_ACB Fld (8, 8) /* AC Bias clock half period - 1 */ 2794*3b58acd4Swdenk /* [Tln] (L_BIAS) */ 2795*3b58acd4Swdenk #define LCCR3_ACBsDiv(Div) /* AC Bias clock Divisor [2..512] */ \ 2796*3b58acd4Swdenk (((Div) - 2)/2 << FShft (LCCR3_ACB)) 2797*3b58acd4Swdenk /* fac = fln/(2*Floor (Div/2)) */ 2798*3b58acd4Swdenk /* Tac = 2*Floor (Div/2)*Tln */ 2799*3b58acd4Swdenk #define LCCR3_CeilACBsDiv(Div) /* Ceil. of ACBsDiv [2..512] */ \ 2800*3b58acd4Swdenk (((Div) - 1)/2 << FShft (LCCR3_ACB)) 2801*3b58acd4Swdenk /* fac = fln/(2*Ceil (Div/2)) */ 2802*3b58acd4Swdenk /* Tac = 2*Ceil (Div/2)*Tln */ 2803*3b58acd4Swdenk #define LCCR3_API Fld (4, 16) /* AC bias Pin transitions per */ 2804*3b58acd4Swdenk /* Interrupt */ 2805*3b58acd4Swdenk #define LCCR3_ACBsCntOff /* AC Bias clock transition Count */ \ 2806*3b58acd4Swdenk /* Off */ \ 2807*3b58acd4Swdenk (0 << FShft (LCCR3_API)) 2808*3b58acd4Swdenk #define LCCR3_ACBsCnt(Trans) /* AC Bias clock transition Count */ \ 2809*3b58acd4Swdenk /* [1..15] */ \ 2810*3b58acd4Swdenk ((Trans) << FShft (LCCR3_API)) 2811*3b58acd4Swdenk #define LCCR3_VSP 0x00100000 /* Vertical Synchronization pulse */ 2812*3b58acd4Swdenk /* Polarity (L_FCLK) */ 2813*3b58acd4Swdenk #define LCCR3_VrtSnchH (LCCR3_VSP*0) /* Vertical Synchronization pulse */ 2814*3b58acd4Swdenk /* active High */ 2815*3b58acd4Swdenk #define LCCR3_VrtSnchL (LCCR3_VSP*1) /* Vertical Synchronization pulse */ 2816*3b58acd4Swdenk /* active Low */ 2817*3b58acd4Swdenk #define LCCR3_HSP 0x00200000 /* Horizontal Synchronization */ 2818*3b58acd4Swdenk /* pulse Polarity (L_LCLK) */ 2819*3b58acd4Swdenk #define LCCR3_HorSnchH (LCCR3_HSP*0) /* Horizontal Synchronization */ 2820*3b58acd4Swdenk /* pulse active High */ 2821*3b58acd4Swdenk #define LCCR3_HorSnchL (LCCR3_HSP*1) /* Horizontal Synchronization */ 2822*3b58acd4Swdenk /* pulse active Low */ 2823*3b58acd4Swdenk #define LCCR3_PCP 0x00400000 /* Pixel Clock Polarity (L_PCLK) */ 2824*3b58acd4Swdenk #define LCCR3_PixRsEdg (LCCR3_PCP*0) /* Pixel clock Rising-Edge */ 2825*3b58acd4Swdenk #define LCCR3_PixFlEdg (LCCR3_PCP*1) /* Pixel clock Falling-Edge */ 2826*3b58acd4Swdenk #define LCCR3_OEP 0x00800000 /* Output Enable Polarity (L_BIAS, */ 2827*3b58acd4Swdenk /* active display mode) */ 2828*3b58acd4Swdenk #define LCCR3_OutEnH (LCCR3_OEP*0) /* Output Enable active High */ 2829*3b58acd4Swdenk #define LCCR3_OutEnL (LCCR3_OEP*1) /* Output Enable active Low */ 2830*3b58acd4Swdenk 2831*3b58acd4Swdenk 2832*3b58acd4Swdenk #undef C 2833*3b58acd4Swdenk #undef Assembly 2834