1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2004
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 */
6
7 #include <common.h>
8 #include <command.h>
9 #include <malloc.h>
10 #include <asm/immap.h>
11
12 DECLARE_GLOBAL_DATA_PTR;
13
checkboard(void)14 int checkboard (void) {
15 ulong val;
16 uchar val8;
17
18 puts ("Board: ");
19 puts("Freescale M5249EVB");
20 val8 = ((uchar)~((uchar)mbar2_readLong(MCFSIM_GPIO1_READ) >> 4)) & 0xf;
21 printf(" (Switch=%1X)\n", val8);
22
23 /*
24 * Set LED on
25 */
26 val = mbar2_readLong(MCFSIM_GPIO1_OUT) & ~CONFIG_SYS_GPIO1_LED;
27 mbar2_writeLong(MCFSIM_GPIO1_OUT, val); /* Set LED on */
28
29 return 0;
30 };
31
32
dram_init(void)33 int dram_init(void)
34 {
35 unsigned long junk = 0xa5a59696;
36
37 /*
38 * Note:
39 * RC = ([(RefreshTime/#rows) / (1/BusClk)] / 16) - 1
40 */
41
42 #ifdef CONFIG_SYS_FAST_CLK
43 /*
44 * Busclk=70MHz, RefreshTime=64ms, #rows=4096 (4K)
45 * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=39
46 */
47 mbar_writeShort(MCFSIM_DCR, 0x8239);
48 #elif CONFIG_SYS_PLL_BYPASS
49 /*
50 * Busclk=5.6448MHz, RefreshTime=64ms, #rows=8192 (8K)
51 * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=02
52 */
53 mbar_writeShort(MCFSIM_DCR, 0x8202);
54 #else
55 /*
56 * Busclk=36MHz, RefreshTime=64ms, #rows=4096 (4K)
57 * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=22 (562 bus clock cycles)
58 */
59 mbar_writeShort(MCFSIM_DCR, 0x8222);
60 #endif
61
62 /*
63 * SDRAM starts at 0x0000_0000, CASL=10, CBM=010, PS=10 (16bit port),
64 * PM=1 (continuous page mode)
65 */
66
67 /* RE=0 (keep auto-refresh disabled while setting up registers) */
68 mbar_writeLong(MCFSIM_DACR0, 0x00003324);
69
70 /* BAM=007c (bits 22,21 are bank selects; 256kB blocks) */
71 mbar_writeLong(MCFSIM_DMR0, 0x01fc0001);
72
73 /** Precharge sequence **/
74 mbar_writeLong(MCFSIM_DACR0, 0x0000332c); /* Set DACR0[IP] (bit 3) */
75 *((volatile unsigned long *) 0x00) = junk; /* write to a memory location to init. precharge */
76 udelay(0x10); /* Allow several Precharge cycles */
77
78 /** Refresh Sequence **/
79 mbar_writeLong(MCFSIM_DACR0, 0x0000b324); /* Enable the refresh bit, DACR0[RE] (bit 15) */
80 udelay(0x7d0); /* Allow gobs of refresh cycles */
81
82 /** Mode Register initialization **/
83 mbar_writeLong(MCFSIM_DACR0, 0x0000b364); /* Enable DACR0[IMRS] (bit 6); RE remains enabled */
84 *((volatile unsigned long *) 0x800) = junk; /* Access RAM to initialize the mode register */
85
86 gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
87
88 return 0;
89 };
90
91
testdram(void)92 int testdram (void) {
93 /* TODO: XXX XXX XXX */
94 printf ("DRAM test not implemented!\n");
95
96 return (0);
97 }
98