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/openbmc/linux/drivers/pinctrl/
H A Dpinctrl-da9062.c1 // SPDX-License-Identifier: GPL-2.0
7 * - add pinmux and pinctrl support (gpio alternate mode)
10 * [1] https://www.dialog-semiconductor.com/sites/default/files/da9062_datasheet_3v6.pdf
18 #include <linux/regmap.h>
27 * the gpio is active low without a vendor specific dt-binding.
35 #define DA9062_PIN_GPO_OD 0x02 /* gpio out open-drain */
36 #define DA9062_PIN_GPO_PP 0x03 /* gpio out push-pull */
45 static int da9062_pctl_get_pin_mode(struct da9062_pctl *pctl, in da9062_pctl_get_pin_mode() argument
48 struct regmap *regmap = pctl->da9062->regmap; in da9062_pctl_get_pin_mode() local
51 ret = regmap_read(regmap, DA9062AA_GPIO_0_1 + (offset >> 1), &val); in da9062_pctl_get_pin_mode()
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H A Dpinctrl-sx150x.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * The handling of the 4-bit chips (SX1501/SX1504/SX1507) is untested.
14 #include <linux/regmap.h>
26 #include <linux/pinctrl/pinconf-generic.h>
30 #include "pinctrl-utils.h"
101 struct regmap *regmap; member
359 return -ENOTSUPP; in sx150x_pinctrl_get_group_pins()
372 static bool sx150x_pin_is_oscio(struct sx150x_pinctrl *pctl, unsigned int pin) in sx150x_pin_is_oscio() argument
374 if (pin >= pctl->data->npins) in sx150x_pin_is_oscio()
378 if (pctl->data->model != SX150X_789) in sx150x_pin_is_oscio()
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H A Dpinctrl-axp209.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
6 * Copyright (C) 2017 Quentin Schulz <quentin.schulz@free-electrons.com>
19 #include <linux/regmap.h>
23 #include <linux/pinctrl/pinconf-generic.h>
69 struct regmap *regmap; member
124 return -EINVAL; in axp20x_gpio_get_reg()
129 return pinctrl_gpio_direction_input(chip->base + offset); in axp20x_gpio_input()
134 struct axp20x_pctl *pctl = gpiochip_get_data(chip); in axp20x_gpio_get() local
140 ret = regmap_read(pctl->regmap, AXP20X_GPIO3_CTRL, &val); in axp20x_gpio_get()
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H A Dpinctrl-apple-gpio.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Based on: pinctrl-pistachio.c
13 #include <dt-bindings/pinctrl/apple.h>
24 #include <linux/regmap.h>
29 #include "pinctrl-utils.h"
38 struct regmap *map;
80 /* No locking needed to mask/unmask IRQs as the interrupt mode is per pin-register. */
81 static void apple_gpio_set_reg(struct apple_gpio_pinctrl *pctl, in apple_gpio_set_reg() argument
84 regmap_update_bits(pctl->map, REG_GPIO(pin), mask, value); in apple_gpio_set_reg()
87 static u32 apple_gpio_get_reg(struct apple_gpio_pinctrl *pctl, in apple_gpio_get_reg() argument
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H A Dpinctrl-rk805.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * Author: Joseph Chen <chenjh@rock-chips.com>
9 * Author: Xu Shengfei <xsf@rock-chips.com>
11 * Based on the pinctrl-as3722 driver
26 #include <linux/pinctrl/pinconf-generic.h>
32 #include "pinctrl-utils.h"
71 struct pinctrl_dev *pctl; member
264 ret = regmap_read(pci->rk808->regmap, pci->pin_cfg[offset].reg, &val); in rk805_gpio_get()
266 dev_err(pci->dev, "get gpio%d value failed\n", offset); in rk805_gpio_get()
270 return !!(val & pci->pin_cfg[offset].val_msk); in rk805_gpio_get()
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H A Dpinctrl-max77620.c1 // SPDX-License-Identifier: GPL-2.0-only
17 #include <linux/regmap.h>
20 #include <linux/pinctrl/pinconf-generic.h>
26 #include "pinctrl-utils.h"
52 .property = "maxim,active-fps-source",
55 .property = "maxim,active-fps-power-up-slot",
58 .property = "maxim,active-fps-power-down-slot",
61 .property = "maxim,suspend-fps-source",
64 .property = "maxim,suspend-fps-power-up-slot",
67 .property = "maxim,suspend-fps-power-down-slot",
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H A Dpinctrl-st.c1 // SPDX-License-Identifier: GPL-2.0-only
18 #include <linux/regmap.h>
100 * (direction, retime-type, retime-clk, retime-delay)
102 * +----------------+
103 *[31:28]| reserved-3 |
104 * +----------------+-------------
106 * +----------------+ v
108 * +----------------+ ^
110 * +----------------+-------------
111 *[24] | reserved-2 |
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H A Dpinctrl-rockchip.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2020-2021 Rockchip Electronics Co. Ltd.
8 * With some ideas taken from pinctrl-samsung:
14 * and pinctrl-at91:
15 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
242 * @offset: if initialized to -1 it will be autocalculated, by specifying
275 * @offset: if initialized to -1 it will be autocalculated, by specifying
318 struct regmap *regmap_pull;
402 int pin_num, struct regmap **regmap,
405 int pin_num, struct regmap **regmap,
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/openbmc/linux/drivers/pinctrl/mediatek/
H A Dpinctrl-mtk-common.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/pinctrl/pinconf-generic.h>
21 #include <linux/regmap.h>
26 #include <dt-bindings/pinctrl/mt65xx.h>
30 #include "../pinctrl-utils.h"
31 #include "mtk-eint.h"
32 #include "pinctrl-mtk-common.h"
50 static struct regmap *mtk_get_regmap(struct mtk_pinctrl *pctl, in mtk_get_regmap() argument
53 if (pin >= pctl->devdata->type1_start && pin < pctl->devdata->type1_end) in mtk_get_regmap()
54 return pctl->regmap2; in mtk_get_regmap()
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/openbmc/linux/drivers/pinctrl/mvebu/
H A Dpinctrl-mvebu.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
15 #include <linux/regmap.h>
24 #include "pinctrl-mvebu.h"
64 *config = (readl(data->base + off) >> shift) & MVEBU_MPP_MASK; in mvebu_mmio_mpp_ctrl_get()
76 reg = readl(data->base + off) & ~(MVEBU_MPP_MASK << shift); in mvebu_mmio_mpp_ctrl_set()
77 writel(reg | (config << shift), data->base + off); in mvebu_mmio_mpp_ctrl_set()
83 struct mvebu_pinctrl *pctl, unsigned pid) in mvebu_pinctrl_find_group_by_pid() argument
86 for (n = 0; n < pctl->num_groups; n++) { in mvebu_pinctrl_find_group_by_pid()
87 if (pid >= pctl->groups[n].pins[0] && in mvebu_pinctrl_find_group_by_pid()
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/openbmc/linux/drivers/pinctrl/stm32/
H A Dpinctrl-stm32.c1 // SPDX-License-Identifier: GPL-2.0
21 #include <linux/regmap.h>
28 #include <linux/pinctrl/pinconf-generic.h>
35 #include "../pinctrl-utils.h"
36 #include "pinctrl-stm32.h"
114 struct regmap *regmap; member
149 return function - 1; in stm32_gpio_get_alt()
160 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_VAL); in stm32_gpio_backup_value()
161 bank->pin_backup[offset] |= value << STM32_GPIO_BKP_VAL; in stm32_gpio_backup_value()
167 bank->pin_backup[offset] &= ~(STM32_GPIO_BKP_MODE_MASK | in stm32_gpio_backup_mode()
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/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmediatek,mt65xx-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt65xx-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@kernel.org>
18 - mediatek,mt2701-pinctrl
19 - mediatek,mt2712-pinctrl
20 - mediatek,mt6397-pinctrl
21 - mediatek,mt7623-pinctrl
22 - mediatek,mt8127-pinctrl
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H A Dmediatek,mt8365-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8365-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Zhiyong Tao <zhiyong.tao@mediatek.com>
11 - Bernhard Rosenkränzer <bero@baylibre.com>
18 const: mediatek,mt8365-pinctrl
23 mediatek,pctl-regmap:
24 $ref: /schemas/types.yaml#/definitions/phandle-array
32 gpio-controller: true
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/openbmc/u-boot/drivers/ram/rockchip/
H A Dsdram_rk3188.c1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
12 #include <dt-structs.h>
15 #include <regmap.h>
28 struct rk3288_ddr_pctl *pctl; member
52 struct regmap *map;
103 rk_clrsetreg(&cru->cru_softrst_con[5], in ddr_reset()
116 rk_clrsetreg(&cru->cru_softrst_con[5], in ddr_phy_ctl_reset()
128 clrbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST); in phy_pctrl_reset()
130 clrbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST); in phy_pctrl_reset()
133 setbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST); in phy_pctrl_reset()
[all …]
H A Dsdram_rk3288.c1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
12 #include <dt-structs.h>
15 #include <regmap.h>
30 struct rk3288_ddr_pctl *pctl; member
55 struct regmap *map;
102 rk_clrsetreg(&cru->cru_softrst_con[10], in ddr_reset()
115 rk_clrsetreg(&cru->cru_softrst_con[10], in ddr_phy_ctl_reset()
127 clrbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST); in phy_pctrl_reset()
129 clrbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST); in phy_pctrl_reset()
132 setbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST); in phy_pctrl_reset()
[all …]
H A Dsdram_rk322x.c1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
8 #include <dt-structs.h>
11 #include <regmap.h>
27 struct rk322x_ddr_pctl *pctl; member
49 struct regmap *map;
93 rk_clrsetreg(&cru->cru_softrst_con[5], 1 << DDRCTRL_PSRST_SHIFT | in phy_pctrl_reset()
101 rk_clrreg(&cru->cru_softrst_con[5], 1 << DDRPHY_PSRST_SHIFT | in phy_pctrl_reset()
105 rk_clrreg(&cru->cru_softrst_con[5], 1 << DDRCTRL_PSRST_SHIFT | in phy_pctrl_reset()
109 clrbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
112 setbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
[all …]
H A Ddmc-rk3368.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/memory/rk3368-dmc.h>
10 #include <dt-structs.h>
12 #include <regmap.h>
27 struct rk3368_ddr_pctl *pctl; member
40 struct regmap *map;
123 ((n <= 8) ? ((n - 4) << 9) : (((n >> 1) & 0x7) << 9))
125 ((((n - 4) & 0x7) << 4) | (((n - 4) & 0x8) >> 2))
133 (((n - 5) & 0x7) << 3)
141 rk_setreg(&grf->ddrc0_con0, NOC_RSP_ERR_STALL); in ddr_set_noc_spr_err_stall()
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/openbmc/linux/drivers/pinctrl/ti/
H A Dpinctrl-ti-iodelay.c5 * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/
19 #include <linux/regmap.h>
23 #include <linux/pinctrl/pinconf-generic.h>
30 #define DRIVER_NAME "ti-iodelay"
33 * struct ti_iodelay_reg_data - Describes the registers for the iodelay instance
55 * @regmap_config: Regmap configuration for the IODelay region
89 * struct ti_iodelay_reg_values - Computed io_reg configuration values (see TRM)
112 * struct ti_iodelay_cfg - Description of each configuration parameters
124 * struct ti_iodelay_pingroup - Structure that describes one group
127 * @config: pinconf "Config" - currently a dummy value
[all …]
/openbmc/linux/drivers/pinctrl/spear/
H A Dpinctrl-spear.c8 * - U300 Pinctl drivers
9 * - Tegra Pinctl drivers
29 #include "pinctrl-spear.h"
31 #define DRIVER_NAME "spear-pinmux"
42 val = pmx_readl(pmx, muxreg->reg); in muxregs_endisable()
43 val &= ~muxreg->mask; in muxregs_endisable()
46 temp = muxreg->val; in muxregs_endisable()
48 temp = ~muxreg->val; in muxregs_endisable()
50 val |= muxreg->mask & temp; in muxregs_endisable()
51 pmx_writel(pmx, val, muxreg->reg); in muxregs_endisable()
[all …]
H A Dpinctrl-spear.h18 #include <linux/regmap.h>
26 * struct spear_pmx_mode - SPEAr pmx mode
42 * struct spear_muxreg - SPEAr mux reg configuration
92 * struct spear_modemux - SPEAr mode mux configuration
104 * struct spear_pingroup - SPEAr pin group configurations
123 * struct spear_function - SPEAr pinctrl mux function
135 * struct spear_pinctrl_machdata - SPEAr pin controller machine driver
172 * struct spear_pmx - SPEAr pinctrl mux
174 * @pctl: pointer to struct pinctrl_dev
176 * @regmap: regmap of pinmux controller
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/openbmc/linux/arch/arm/boot/dts/mediatek/
H A Dmt8135.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/mt8135-clk.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/mt8135-resets.h>
12 #include <dt-bindings/pinctrl/mt8135-pinfunc.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
18 interrupt-parent = <&sysirq>;
20 cpu-map {
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/openbmc/linux/drivers/pinctrl/freescale/
H A Dpinctrl-imx.c1 // SPDX-License-Identifier: GPL-2.0+
18 #include <linux/regmap.h>
30 #include "pinctrl-imx.h"
43 for (i = 0; i < pctldev->num_groups; i++) { in imx_pinctrl_find_group_by_name()
45 if (grp && !strcmp(grp->name, name)) in imx_pinctrl_find_group_by_name()
55 seq_printf(s, "%s", dev_name(pctldev->dev)); in imx_pin_dbg_show()
63 const struct imx_pinctrl_soc_info *info = ipctl->info; in imx_dt_node_to_map()
75 grp = imx_pinctrl_find_group_by_name(pctldev, np->name); in imx_dt_node_to_map()
77 dev_err(ipctl->dev, "unable to find group for node %pOFn\n", np); in imx_dt_node_to_map()
78 return -EINVAL; in imx_dt_node_to_map()
[all …]
/openbmc/linux/drivers/pinctrl/nxp/
H A Dpinctrl-s32cc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2017-2022 NXP
7 * Copyright 2015-2016 Freescale Semiconductor, Inc.
22 #include <linux/regmap.h>
28 #include "../pinctrl-utils.h"
29 #include "pinctrl-s32.h"
59 struct regmap *map;
85 * @pctl: a pointer to the pinctrl device structure
94 struct pinctrl_dev *pctl; member
109 unsigned int mem_regions = ipctl->info->soc_data->mem_regions; in s32_get_region()
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/openbmc/linux/drivers/pinctrl/cirrus/
H A Dpinctrl-lochnagar.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2017-2018 Cirrus Logic, Inc. and
17 #include <linux/regmap.h>
20 #include <linux/pinctrl/pinconf-generic.h>
29 #include <dt-bindings/pinctrl/lochnagar.h>
31 #include "../pinctrl-utils.h"
35 #define LN_CDC_AIF1_STR "codec-aif1"
36 #define LN_CDC_AIF2_STR "codec-aif2"
37 #define LN_CDC_AIF3_STR "codec-aif3"
38 #define LN_DSP_AIF1_STR "dsp-aif1"
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/openbmc/linux/drivers/pinctrl/bcm/
H A Dpinctrl-bcm281xx.c1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (C) 2013-2017 Broadcom
9 #include <linux/regmap.h>
13 #include <linux/pinctrl/pinconf-generic.h>
19 #include "../pinctrl-utils.h"
56 * bcm281xx_pin_type - types of pin register
70 * bcm281xx_pin_function- define pin function
79 * bcm281xx_pinctrl_data - Broadcom-specific pinctrl data
80 * @reg_base - base of pinctrl registers
92 struct regmap *regmap; member
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