Lines Matching +full:pctl +full:- +full:regmap
1 // SPDX-License-Identifier: GPL-2.0+
18 #include <linux/regmap.h>
30 #include "pinctrl-imx.h"
43 for (i = 0; i < pctldev->num_groups; i++) { in imx_pinctrl_find_group_by_name()
45 if (grp && !strcmp(grp->name, name)) in imx_pinctrl_find_group_by_name()
55 seq_printf(s, "%s", dev_name(pctldev->dev)); in imx_pin_dbg_show()
63 const struct imx_pinctrl_soc_info *info = ipctl->info; in imx_dt_node_to_map()
75 grp = imx_pinctrl_find_group_by_name(pctldev, np->name); in imx_dt_node_to_map()
77 dev_err(ipctl->dev, "unable to find group for node %pOFn\n", np); in imx_dt_node_to_map()
78 return -EINVAL; in imx_dt_node_to_map()
81 if (info->flags & IMX_USE_SCU) { in imx_dt_node_to_map()
82 map_num += grp->num_pins; in imx_dt_node_to_map()
84 for (i = 0; i < grp->num_pins; i++) { in imx_dt_node_to_map()
85 pin = &((struct imx_pin *)(grp->data))[i]; in imx_dt_node_to_map()
86 if (!(pin->conf.mmio.config & IMX_NO_PAD_CTL)) in imx_dt_node_to_map()
94 return -ENOMEM; in imx_dt_node_to_map()
103 return -EINVAL; in imx_dt_node_to_map()
106 new_map[0].data.mux.function = parent->name; in imx_dt_node_to_map()
107 new_map[0].data.mux.group = np->name; in imx_dt_node_to_map()
112 for (i = j = 0; i < grp->num_pins; i++) { in imx_dt_node_to_map()
113 pin = &((struct imx_pin *)(grp->data))[i]; in imx_dt_node_to_map()
119 if (!(info->flags & IMX_USE_SCU) && in imx_dt_node_to_map()
120 (pin->conf.mmio.config & IMX_NO_PAD_CTL)) in imx_dt_node_to_map()
125 pin_get_name(pctldev, pin->pin); in imx_dt_node_to_map()
127 if (info->flags & IMX_USE_SCU) { in imx_dt_node_to_map()
133 (unsigned long *)&pin->conf.scu; in imx_dt_node_to_map()
137 &pin->conf.mmio.config; in imx_dt_node_to_map()
144 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", in imx_dt_node_to_map()
145 (*map)->data.mux.function, (*map)->data.mux.group, map_num); in imx_dt_node_to_map()
168 const struct imx_pinctrl_soc_info *info = ipctl->info; in imx_pmx_set_one_pin_mmio()
169 struct imx_pin_mmio *pin_mmio = &pin->conf.mmio; in imx_pmx_set_one_pin_mmio()
173 pin_id = pin->pin; in imx_pmx_set_one_pin_mmio()
174 pin_reg = &ipctl->pin_regs[pin_id]; in imx_pmx_set_one_pin_mmio()
176 if (pin_reg->mux_reg == -1) { in imx_pmx_set_one_pin_mmio()
177 dev_dbg(ipctl->dev, "Pin(%s) does not support mux function\n", in imx_pmx_set_one_pin_mmio()
178 info->pins[pin_id].name); in imx_pmx_set_one_pin_mmio()
182 if (info->flags & SHARE_MUX_CONF_REG) { in imx_pmx_set_one_pin_mmio()
185 reg = readl(ipctl->base + pin_reg->mux_reg); in imx_pmx_set_one_pin_mmio()
186 reg &= ~info->mux_mask; in imx_pmx_set_one_pin_mmio()
187 reg |= (pin_mmio->mux_mode << info->mux_shift); in imx_pmx_set_one_pin_mmio()
188 writel(reg, ipctl->base + pin_reg->mux_reg); in imx_pmx_set_one_pin_mmio()
189 dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n", in imx_pmx_set_one_pin_mmio()
190 pin_reg->mux_reg, reg); in imx_pmx_set_one_pin_mmio()
192 writel(pin_mmio->mux_mode, ipctl->base + pin_reg->mux_reg); in imx_pmx_set_one_pin_mmio()
193 dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n", in imx_pmx_set_one_pin_mmio()
194 pin_reg->mux_reg, pin_mmio->mux_mode); in imx_pmx_set_one_pin_mmio()
210 if (pin_mmio->input_val >> 24 == 0xff) { in imx_pmx_set_one_pin_mmio()
211 u32 val = pin_mmio->input_val; in imx_pmx_set_one_pin_mmio()
215 u32 mask = ((1 << width) - 1) << shift; in imx_pmx_set_one_pin_mmio()
220 val = readl(ipctl->base + pin_mmio->input_reg); in imx_pmx_set_one_pin_mmio()
223 writel(val, ipctl->base + pin_mmio->input_reg); in imx_pmx_set_one_pin_mmio()
224 } else if (pin_mmio->input_reg) { in imx_pmx_set_one_pin_mmio()
229 if (ipctl->input_sel_base) in imx_pmx_set_one_pin_mmio()
230 writel(pin_mmio->input_val, ipctl->input_sel_base + in imx_pmx_set_one_pin_mmio()
231 pin_mmio->input_reg); in imx_pmx_set_one_pin_mmio()
233 writel(pin_mmio->input_val, ipctl->base + in imx_pmx_set_one_pin_mmio()
234 pin_mmio->input_reg); in imx_pmx_set_one_pin_mmio()
235 dev_dbg(ipctl->dev, in imx_pmx_set_one_pin_mmio()
237 pin_mmio->input_reg, pin_mmio->input_val); in imx_pmx_set_one_pin_mmio()
247 const struct imx_pinctrl_soc_info *info = ipctl->info; in imx_pmx_set()
260 return -EINVAL; in imx_pmx_set()
264 return -EINVAL; in imx_pmx_set()
266 npins = grp->num_pins; in imx_pmx_set()
268 dev_dbg(ipctl->dev, "enable function %s group %s\n", in imx_pmx_set()
269 func->name, grp->name); in imx_pmx_set()
277 pin = &((struct imx_pin *)(grp->data))[i]; in imx_pmx_set()
278 if (!(info->flags & IMX_USE_SCU)) { in imx_pmx_set()
299 const struct imx_pinctrl_soc_info *info = ipctl->info; in imx_pinconf_get_mmio()
300 const struct imx_pin_reg *pin_reg = &ipctl->pin_regs[pin_id]; in imx_pinconf_get_mmio()
302 if (pin_reg->conf_reg == -1) { in imx_pinconf_get_mmio()
303 dev_err(ipctl->dev, "Pin(%s) does not support config function\n", in imx_pinconf_get_mmio()
304 info->pins[pin_id].name); in imx_pinconf_get_mmio()
305 return -EINVAL; in imx_pinconf_get_mmio()
308 *config = readl(ipctl->base + pin_reg->conf_reg); in imx_pinconf_get_mmio()
310 if (info->flags & SHARE_MUX_CONF_REG) in imx_pinconf_get_mmio()
311 *config &= ~info->mux_mask; in imx_pinconf_get_mmio()
320 const struct imx_pinctrl_soc_info *info = ipctl->info; in imx_pinconf_get()
322 if (info->flags & IMX_USE_SCU) in imx_pinconf_get()
323 return info->imx_pinconf_get(pctldev, pin_id, config); in imx_pinconf_get()
333 const struct imx_pinctrl_soc_info *info = ipctl->info; in imx_pinconf_set_mmio()
334 const struct imx_pin_reg *pin_reg = &ipctl->pin_regs[pin_id]; in imx_pinconf_set_mmio()
337 if (pin_reg->conf_reg == -1) { in imx_pinconf_set_mmio()
338 dev_err(ipctl->dev, "Pin(%s) does not support config function\n", in imx_pinconf_set_mmio()
339 info->pins[pin_id].name); in imx_pinconf_set_mmio()
340 return -EINVAL; in imx_pinconf_set_mmio()
343 dev_dbg(ipctl->dev, "pinconf set pin %s\n", in imx_pinconf_set_mmio()
344 info->pins[pin_id].name); in imx_pinconf_set_mmio()
347 if (info->flags & SHARE_MUX_CONF_REG) { in imx_pinconf_set_mmio()
349 reg = readl(ipctl->base + pin_reg->conf_reg); in imx_pinconf_set_mmio()
350 reg &= info->mux_mask; in imx_pinconf_set_mmio()
352 writel(reg, ipctl->base + pin_reg->conf_reg); in imx_pinconf_set_mmio()
353 dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n", in imx_pinconf_set_mmio()
354 pin_reg->conf_reg, reg); in imx_pinconf_set_mmio()
356 writel(configs[i], ipctl->base + pin_reg->conf_reg); in imx_pinconf_set_mmio()
357 dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n", in imx_pinconf_set_mmio()
358 pin_reg->conf_reg, configs[i]); in imx_pinconf_set_mmio()
370 const struct imx_pinctrl_soc_info *info = ipctl->info; in imx_pinconf_set()
372 if (info->flags & IMX_USE_SCU) in imx_pinconf_set()
373 return info->imx_pinconf_set(pctldev, pin_id, in imx_pinconf_set()
384 const struct imx_pinctrl_soc_info *info = ipctl->info; in imx_pinconf_dbg_show()
389 if (info->flags & IMX_USE_SCU) { in imx_pinconf_dbg_show()
390 ret = info->imx_pinconf_get(pctldev, pin_id, &config); in imx_pinconf_dbg_show()
392 dev_err(ipctl->dev, "failed to get %s pinconf\n", in imx_pinconf_dbg_show()
398 pin_reg = &ipctl->pin_regs[pin_id]; in imx_pinconf_dbg_show()
399 if (pin_reg->conf_reg == -1) { in imx_pinconf_dbg_show()
404 config = readl(ipctl->base + pin_reg->conf_reg); in imx_pinconf_dbg_show()
418 if (group >= pctldev->num_groups) in imx_pinconf_group_dbg_show()
426 for (i = 0; i < grp->num_pins; i++) { in imx_pinconf_group_dbg_show()
427 struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i]; in imx_pinconf_group_dbg_show()
429 name = pin_get_name(pctldev, pin->pin); in imx_pinconf_group_dbg_show()
430 ret = imx_pinconf_get(pctldev, pin->pin, &config); in imx_pinconf_group_dbg_show()
465 const struct imx_pinctrl_soc_info *info = ipctl->info; in imx_pinctrl_parse_pin_mmio()
466 struct imx_pin_mmio *pin_mmio = &pin->conf.mmio; in imx_pinctrl_parse_pin_mmio()
474 if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg) in imx_pinctrl_parse_pin_mmio()
475 mux_reg = -1; in imx_pinctrl_parse_pin_mmio()
477 if (info->flags & SHARE_MUX_CONF_REG) { in imx_pinctrl_parse_pin_mmio()
482 conf_reg = -1; in imx_pinctrl_parse_pin_mmio()
485 *pin_id = (mux_reg != -1) ? mux_reg / 4 : conf_reg / 4; in imx_pinctrl_parse_pin_mmio()
486 pin_reg = &ipctl->pin_regs[*pin_id]; in imx_pinctrl_parse_pin_mmio()
487 pin->pin = *pin_id; in imx_pinctrl_parse_pin_mmio()
488 pin_reg->mux_reg = mux_reg; in imx_pinctrl_parse_pin_mmio()
489 pin_reg->conf_reg = conf_reg; in imx_pinctrl_parse_pin_mmio()
490 pin_mmio->input_reg = be32_to_cpu(*list++); in imx_pinctrl_parse_pin_mmio()
491 pin_mmio->mux_mode = be32_to_cpu(*list++); in imx_pinctrl_parse_pin_mmio()
492 pin_mmio->input_val = be32_to_cpu(*list++); in imx_pinctrl_parse_pin_mmio()
498 pin_mmio->mux_mode |= IOMUXC_CONFIG_SION; in imx_pinctrl_parse_pin_mmio()
499 pin_mmio->config = config & ~IMX_PAD_SION; in imx_pinctrl_parse_pin_mmio()
503 dev_dbg(ipctl->dev, "%s: 0x%x 0x%08lx", info->pins[*pin_id].name, in imx_pinctrl_parse_pin_mmio()
504 pin_mmio->mux_mode, pin_mmio->config); in imx_pinctrl_parse_pin_mmio()
512 const struct imx_pinctrl_soc_info *info = ipctl->info; in imx_pinctrl_parse_groups()
518 dev_dbg(ipctl->dev, "group(%d): %pOFn\n", index, np); in imx_pinctrl_parse_groups()
520 if (info->flags & IMX_USE_SCU) in imx_pinctrl_parse_groups()
522 else if (info->flags & SHARE_MUX_CONF_REG) in imx_pinctrl_parse_groups()
528 grp->name = np->name; in imx_pinctrl_parse_groups()
544 dev_err(ipctl->dev, in imx_pinctrl_parse_groups()
546 return -EINVAL; in imx_pinctrl_parse_groups()
552 dev_err(ipctl->dev, "Invalid fsl,pins or pins property in node %pOF\n", np); in imx_pinctrl_parse_groups()
553 return -EINVAL; in imx_pinctrl_parse_groups()
556 grp->num_pins = size / pin_size; in imx_pinctrl_parse_groups()
557 grp->data = devm_kcalloc(ipctl->dev, in imx_pinctrl_parse_groups()
558 grp->num_pins, sizeof(struct imx_pin), in imx_pinctrl_parse_groups()
560 grp->pins = devm_kcalloc(ipctl->dev, in imx_pinctrl_parse_groups()
561 grp->num_pins, sizeof(unsigned int), in imx_pinctrl_parse_groups()
563 if (!grp->pins || !grp->data) in imx_pinctrl_parse_groups()
564 return -ENOMEM; in imx_pinctrl_parse_groups()
566 for (i = 0; i < grp->num_pins; i++) { in imx_pinctrl_parse_groups()
567 pin = &((struct imx_pin *)(grp->data))[i]; in imx_pinctrl_parse_groups()
568 if (info->flags & IMX_USE_SCU) in imx_pinctrl_parse_groups()
569 info->imx_pinctrl_parse_pin(ipctl, &grp->pins[i], in imx_pinctrl_parse_groups()
572 imx_pinctrl_parse_pin_mmio(ipctl, &grp->pins[i], in imx_pinctrl_parse_groups()
583 struct pinctrl_dev *pctl = ipctl->pctl; in imx_pinctrl_parse_functions() local
590 dev_dbg(pctl->dev, "parse function(%d): %pOFn\n", index, np); in imx_pinctrl_parse_functions()
592 func = pinmux_generic_get_function(pctl, index); in imx_pinctrl_parse_functions()
594 return -EINVAL; in imx_pinctrl_parse_functions()
597 func->name = np->name; in imx_pinctrl_parse_functions()
598 func->num_group_names = of_get_child_count(np); in imx_pinctrl_parse_functions()
599 if (func->num_group_names == 0) { in imx_pinctrl_parse_functions()
600 dev_info(ipctl->dev, "no groups defined in %pOF\n", np); in imx_pinctrl_parse_functions()
601 return -EINVAL; in imx_pinctrl_parse_functions()
604 group_names = devm_kcalloc(ipctl->dev, func->num_group_names, in imx_pinctrl_parse_functions()
607 return -ENOMEM; in imx_pinctrl_parse_functions()
610 group_names[i++] = child->name; in imx_pinctrl_parse_functions()
611 func->group_names = group_names; in imx_pinctrl_parse_functions()
615 grp = devm_kzalloc(ipctl->dev, sizeof(struct group_desc), in imx_pinctrl_parse_functions()
619 return -ENOMEM; in imx_pinctrl_parse_functions()
622 mutex_lock(&ipctl->mutex); in imx_pinctrl_parse_functions()
623 radix_tree_insert(&pctl->pin_group_tree, in imx_pinctrl_parse_functions()
624 ipctl->group_index++, grp); in imx_pinctrl_parse_functions()
625 mutex_unlock(&ipctl->mutex); in imx_pinctrl_parse_functions()
664 struct device_node *np = pdev->dev.of_node; in imx_pinctrl_probe_dt()
666 struct pinctrl_dev *pctl = ipctl->pctl; in imx_pinctrl_probe_dt() local
672 return -ENODEV; in imx_pinctrl_probe_dt()
680 dev_err(&pdev->dev, "no functions defined\n"); in imx_pinctrl_probe_dt()
681 return -EINVAL; in imx_pinctrl_probe_dt()
688 function = devm_kzalloc(&pdev->dev, sizeof(*function), in imx_pinctrl_probe_dt()
691 return -ENOMEM; in imx_pinctrl_probe_dt()
693 mutex_lock(&ipctl->mutex); in imx_pinctrl_probe_dt()
694 radix_tree_insert(&pctl->pin_function_tree, i, function); in imx_pinctrl_probe_dt()
695 mutex_unlock(&ipctl->mutex); in imx_pinctrl_probe_dt()
697 pctl->num_functions = nfuncs; in imx_pinctrl_probe_dt()
699 ipctl->group_index = 0; in imx_pinctrl_probe_dt()
701 pctl->num_groups = of_get_child_count(np); in imx_pinctrl_probe_dt()
703 pctl->num_groups = 0; in imx_pinctrl_probe_dt()
705 pctl->num_groups += of_get_child_count(child); in imx_pinctrl_probe_dt()
723 struct device_node *dev_np = pdev->dev.of_node; in imx_pinctrl_probe()
727 struct regmap *gpr; in imx_pinctrl_probe()
730 if (!info || !info->pins || !info->npins) { in imx_pinctrl_probe()
731 dev_err(&pdev->dev, "wrong pinctrl info\n"); in imx_pinctrl_probe()
732 return -EINVAL; in imx_pinctrl_probe()
735 if (info->gpr_compatible) { in imx_pinctrl_probe()
736 gpr = syscon_regmap_lookup_by_compatible(info->gpr_compatible); in imx_pinctrl_probe()
738 regmap_attach_dev(&pdev->dev, gpr, &config); in imx_pinctrl_probe()
742 ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL); in imx_pinctrl_probe()
744 return -ENOMEM; in imx_pinctrl_probe()
746 if (!(info->flags & IMX_USE_SCU)) { in imx_pinctrl_probe()
747 ipctl->pin_regs = devm_kmalloc_array(&pdev->dev, info->npins, in imx_pinctrl_probe()
748 sizeof(*ipctl->pin_regs), in imx_pinctrl_probe()
750 if (!ipctl->pin_regs) in imx_pinctrl_probe()
751 return -ENOMEM; in imx_pinctrl_probe()
753 for (i = 0; i < info->npins; i++) { in imx_pinctrl_probe()
754 ipctl->pin_regs[i].mux_reg = -1; in imx_pinctrl_probe()
755 ipctl->pin_regs[i].conf_reg = -1; in imx_pinctrl_probe()
758 ipctl->base = devm_platform_ioremap_resource(pdev, 0); in imx_pinctrl_probe()
759 if (IS_ERR(ipctl->base)) in imx_pinctrl_probe()
760 return PTR_ERR(ipctl->base); in imx_pinctrl_probe()
762 if (of_property_read_bool(dev_np, "fsl,input-sel")) { in imx_pinctrl_probe()
763 np = of_parse_phandle(dev_np, "fsl,input-sel", 0); in imx_pinctrl_probe()
765 dev_err(&pdev->dev, "iomuxc fsl,input-sel property not found\n"); in imx_pinctrl_probe()
766 return -EINVAL; in imx_pinctrl_probe()
769 ipctl->input_sel_base = of_iomap(np, 0); in imx_pinctrl_probe()
771 if (!ipctl->input_sel_base) { in imx_pinctrl_probe()
772 dev_err(&pdev->dev, in imx_pinctrl_probe()
774 return -ENOMEM; in imx_pinctrl_probe()
779 imx_pinctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*imx_pinctrl_desc), in imx_pinctrl_probe()
782 return -ENOMEM; in imx_pinctrl_probe()
784 imx_pinctrl_desc->name = dev_name(&pdev->dev); in imx_pinctrl_probe()
785 imx_pinctrl_desc->pins = info->pins; in imx_pinctrl_probe()
786 imx_pinctrl_desc->npins = info->npins; in imx_pinctrl_probe()
787 imx_pinctrl_desc->pctlops = &imx_pctrl_ops; in imx_pinctrl_probe()
788 imx_pinctrl_desc->pmxops = &imx_pmx_ops; in imx_pinctrl_probe()
789 imx_pinctrl_desc->confops = &imx_pinconf_ops; in imx_pinctrl_probe()
790 imx_pinctrl_desc->owner = THIS_MODULE; in imx_pinctrl_probe()
793 imx_pmx_ops.gpio_set_direction = info->gpio_set_direction; in imx_pinctrl_probe()
795 mutex_init(&ipctl->mutex); in imx_pinctrl_probe()
797 ipctl->info = info; in imx_pinctrl_probe()
798 ipctl->dev = &pdev->dev; in imx_pinctrl_probe()
800 ret = devm_pinctrl_register_and_init(&pdev->dev, in imx_pinctrl_probe()
802 &ipctl->pctl); in imx_pinctrl_probe()
804 dev_err(&pdev->dev, "could not register IMX pinctrl driver\n"); in imx_pinctrl_probe()
810 dev_err(&pdev->dev, "fail to probe dt properties\n"); in imx_pinctrl_probe()
814 dev_info(&pdev->dev, "initialized IMX pinctrl driver\n"); in imx_pinctrl_probe()
816 return pinctrl_enable(ipctl->pctl); in imx_pinctrl_probe()
824 return pinctrl_force_sleep(ipctl->pctl); in imx_pinctrl_suspend()
831 return pinctrl_force_default(ipctl->pctl); in imx_pinctrl_resume()