1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * MAX77620 pin control driver.
4  *
5  * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
6  *
7  * Author:
8  *	Chaitanya Bandi <bandik@nvidia.com>
9  *	Laxman Dewangan <ldewangan@nvidia.com>
10  */
11 
12 #include <linux/mfd/max77620.h>
13 #include <linux/mod_devicetable.h>
14 #include <linux/module.h>
15 #include <linux/platform_device.h>
16 #include <linux/property.h>
17 #include <linux/regmap.h>
18 
19 #include <linux/pinctrl/pinctrl.h>
20 #include <linux/pinctrl/pinconf-generic.h>
21 #include <linux/pinctrl/pinconf.h>
22 #include <linux/pinctrl/pinmux.h>
23 
24 #include "core.h"
25 #include "pinconf.h"
26 #include "pinctrl-utils.h"
27 
28 #define MAX77620_PIN_NUM 8
29 
30 enum max77620_pin_ppdrv {
31 	MAX77620_PIN_UNCONFIG_DRV,
32 	MAX77620_PIN_OD_DRV,
33 	MAX77620_PIN_PP_DRV,
34 };
35 
36 #define MAX77620_ACTIVE_FPS_SOURCE		(PIN_CONFIG_END + 1)
37 #define MAX77620_ACTIVE_FPS_POWER_ON_SLOTS	(PIN_CONFIG_END + 2)
38 #define MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS	(PIN_CONFIG_END + 3)
39 #define MAX77620_SUSPEND_FPS_SOURCE		(PIN_CONFIG_END + 4)
40 #define MAX77620_SUSPEND_FPS_POWER_ON_SLOTS	(PIN_CONFIG_END + 5)
41 #define MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS	(PIN_CONFIG_END + 6)
42 
43 struct max77620_pin_function {
44 	const char *name;
45 	const char * const *groups;
46 	unsigned int ngroups;
47 	int mux_option;
48 };
49 
50 static const struct pinconf_generic_params max77620_cfg_params[] = {
51 	{
52 		.property = "maxim,active-fps-source",
53 		.param = MAX77620_ACTIVE_FPS_SOURCE,
54 	}, {
55 		.property = "maxim,active-fps-power-up-slot",
56 		.param = MAX77620_ACTIVE_FPS_POWER_ON_SLOTS,
57 	}, {
58 		.property = "maxim,active-fps-power-down-slot",
59 		.param = MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS,
60 	}, {
61 		.property = "maxim,suspend-fps-source",
62 		.param = MAX77620_SUSPEND_FPS_SOURCE,
63 	}, {
64 		.property = "maxim,suspend-fps-power-up-slot",
65 		.param = MAX77620_SUSPEND_FPS_POWER_ON_SLOTS,
66 	}, {
67 		.property = "maxim,suspend-fps-power-down-slot",
68 		.param = MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS,
69 	},
70 };
71 
72 enum max77620_alternate_pinmux_option {
73 	MAX77620_PINMUX_GPIO				= 0,
74 	MAX77620_PINMUX_LOW_POWER_MODE_CONTROL_IN	= 1,
75 	MAX77620_PINMUX_FLEXIBLE_POWER_SEQUENCER_OUT	= 2,
76 	MAX77620_PINMUX_32K_OUT1			= 3,
77 	MAX77620_PINMUX_SD0_DYNAMIC_VOLTAGE_SCALING_IN	= 4,
78 	MAX77620_PINMUX_SD1_DYNAMIC_VOLTAGE_SCALING_IN	= 5,
79 	MAX77620_PINMUX_REFERENCE_OUT			= 6,
80 };
81 
82 struct max77620_pingroup {
83 	const char *name;
84 	const unsigned int pins[1];
85 	unsigned int npins;
86 	enum max77620_alternate_pinmux_option alt_option;
87 };
88 
89 struct max77620_pin_info {
90 	enum max77620_pin_ppdrv drv_type;
91 	int pull_config;
92 };
93 
94 struct max77620_fps_config {
95 	int active_fps_src;
96 	int active_power_up_slots;
97 	int active_power_down_slots;
98 	int suspend_fps_src;
99 	int suspend_power_up_slots;
100 	int suspend_power_down_slots;
101 };
102 
103 struct max77620_pctrl_info {
104 	struct device *dev;
105 	struct pinctrl_dev *pctl;
106 	struct regmap *rmap;
107 	int pins_current_opt[MAX77620_GPIO_NR];
108 	const struct max77620_pin_function *functions;
109 	unsigned int num_functions;
110 	const struct max77620_pingroup *pin_groups;
111 	int num_pin_groups;
112 	const struct pinctrl_pin_desc *pins;
113 	unsigned int num_pins;
114 	struct max77620_pin_info pin_info[MAX77620_PIN_NUM];
115 	struct max77620_fps_config fps_config[MAX77620_PIN_NUM];
116 };
117 
118 static const struct pinctrl_pin_desc max77620_pins_desc[] = {
119 	PINCTRL_PIN(MAX77620_GPIO0, "gpio0"),
120 	PINCTRL_PIN(MAX77620_GPIO1, "gpio1"),
121 	PINCTRL_PIN(MAX77620_GPIO2, "gpio2"),
122 	PINCTRL_PIN(MAX77620_GPIO3, "gpio3"),
123 	PINCTRL_PIN(MAX77620_GPIO4, "gpio4"),
124 	PINCTRL_PIN(MAX77620_GPIO5, "gpio5"),
125 	PINCTRL_PIN(MAX77620_GPIO6, "gpio6"),
126 	PINCTRL_PIN(MAX77620_GPIO7, "gpio7"),
127 };
128 
129 static const char * const gpio_groups[] = {
130 	"gpio0",
131 	"gpio1",
132 	"gpio2",
133 	"gpio3",
134 	"gpio4",
135 	"gpio5",
136 	"gpio6",
137 	"gpio7",
138 };
139 
140 #define FUNCTION_GROUP(fname, mux)			\
141 	{						\
142 		.name = fname,				\
143 		.groups = gpio_groups,			\
144 		.ngroups = ARRAY_SIZE(gpio_groups),	\
145 		.mux_option = MAX77620_PINMUX_##mux,	\
146 	}
147 
148 static const struct max77620_pin_function max77620_pin_function[] = {
149 	FUNCTION_GROUP("gpio", GPIO),
150 	FUNCTION_GROUP("lpm-control-in", LOW_POWER_MODE_CONTROL_IN),
151 	FUNCTION_GROUP("fps-out", FLEXIBLE_POWER_SEQUENCER_OUT),
152 	FUNCTION_GROUP("32k-out1", 32K_OUT1),
153 	FUNCTION_GROUP("sd0-dvs-in", SD0_DYNAMIC_VOLTAGE_SCALING_IN),
154 	FUNCTION_GROUP("sd1-dvs-in", SD1_DYNAMIC_VOLTAGE_SCALING_IN),
155 	FUNCTION_GROUP("reference-out", REFERENCE_OUT),
156 };
157 
158 #define MAX77620_PINGROUP(pg_name, pin_id, option) \
159 	{								\
160 		.name = #pg_name,					\
161 		.pins = {MAX77620_##pin_id},				\
162 		.npins = 1,						\
163 		.alt_option = MAX77620_PINMUX_##option,			\
164 	}
165 
166 static const struct max77620_pingroup max77620_pingroups[] = {
167 	MAX77620_PINGROUP(gpio0, GPIO0, LOW_POWER_MODE_CONTROL_IN),
168 	MAX77620_PINGROUP(gpio1, GPIO1, FLEXIBLE_POWER_SEQUENCER_OUT),
169 	MAX77620_PINGROUP(gpio2, GPIO2, FLEXIBLE_POWER_SEQUENCER_OUT),
170 	MAX77620_PINGROUP(gpio3, GPIO3, FLEXIBLE_POWER_SEQUENCER_OUT),
171 	MAX77620_PINGROUP(gpio4, GPIO4, 32K_OUT1),
172 	MAX77620_PINGROUP(gpio5, GPIO5, SD0_DYNAMIC_VOLTAGE_SCALING_IN),
173 	MAX77620_PINGROUP(gpio6, GPIO6, SD1_DYNAMIC_VOLTAGE_SCALING_IN),
174 	MAX77620_PINGROUP(gpio7, GPIO7, REFERENCE_OUT),
175 };
176 
max77620_pinctrl_get_groups_count(struct pinctrl_dev * pctldev)177 static int max77620_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
178 {
179 	struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
180 
181 	return mpci->num_pin_groups;
182 }
183 
max77620_pinctrl_get_group_name(struct pinctrl_dev * pctldev,unsigned int group)184 static const char *max77620_pinctrl_get_group_name(
185 		struct pinctrl_dev *pctldev, unsigned int group)
186 {
187 	struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
188 
189 	return mpci->pin_groups[group].name;
190 }
191 
max77620_pinctrl_get_group_pins(struct pinctrl_dev * pctldev,unsigned int group,const unsigned int ** pins,unsigned int * num_pins)192 static int max77620_pinctrl_get_group_pins(
193 		struct pinctrl_dev *pctldev, unsigned int group,
194 		const unsigned int **pins, unsigned int *num_pins)
195 {
196 	struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
197 
198 	*pins = mpci->pin_groups[group].pins;
199 	*num_pins = mpci->pin_groups[group].npins;
200 
201 	return 0;
202 }
203 
204 static const struct pinctrl_ops max77620_pinctrl_ops = {
205 	.get_groups_count = max77620_pinctrl_get_groups_count,
206 	.get_group_name = max77620_pinctrl_get_group_name,
207 	.get_group_pins = max77620_pinctrl_get_group_pins,
208 	.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
209 	.dt_free_map = pinctrl_utils_free_map,
210 };
211 
max77620_pinctrl_get_funcs_count(struct pinctrl_dev * pctldev)212 static int max77620_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
213 {
214 	struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
215 
216 	return mpci->num_functions;
217 }
218 
max77620_pinctrl_get_func_name(struct pinctrl_dev * pctldev,unsigned int function)219 static const char *max77620_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
220 						  unsigned int function)
221 {
222 	struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
223 
224 	return mpci->functions[function].name;
225 }
226 
max77620_pinctrl_get_func_groups(struct pinctrl_dev * pctldev,unsigned int function,const char * const ** groups,unsigned int * const num_groups)227 static int max77620_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
228 					    unsigned int function,
229 					    const char * const **groups,
230 					    unsigned int * const num_groups)
231 {
232 	struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
233 
234 	*groups = mpci->functions[function].groups;
235 	*num_groups = mpci->functions[function].ngroups;
236 
237 	return 0;
238 }
239 
max77620_pinctrl_enable(struct pinctrl_dev * pctldev,unsigned int function,unsigned int group)240 static int max77620_pinctrl_enable(struct pinctrl_dev *pctldev,
241 				   unsigned int function, unsigned int group)
242 {
243 	struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
244 	u8 val;
245 	int ret;
246 
247 	if (function == MAX77620_PINMUX_GPIO) {
248 		val = 0;
249 	} else if (function == mpci->pin_groups[group].alt_option) {
250 		val = 1 << group;
251 	} else {
252 		dev_err(mpci->dev, "GPIO %u doesn't have function %u\n",
253 			group, function);
254 		return -EINVAL;
255 	}
256 	ret = regmap_update_bits(mpci->rmap, MAX77620_REG_AME_GPIO,
257 				 BIT(group), val);
258 	if (ret < 0)
259 		dev_err(mpci->dev, "REG AME GPIO update failed: %d\n", ret);
260 
261 	return ret;
262 }
263 
264 static const struct pinmux_ops max77620_pinmux_ops = {
265 	.get_functions_count	= max77620_pinctrl_get_funcs_count,
266 	.get_function_name	= max77620_pinctrl_get_func_name,
267 	.get_function_groups	= max77620_pinctrl_get_func_groups,
268 	.set_mux		= max77620_pinctrl_enable,
269 };
270 
max77620_pinconf_get(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * config)271 static int max77620_pinconf_get(struct pinctrl_dev *pctldev,
272 				unsigned int pin, unsigned long *config)
273 {
274 	struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
275 	struct device *dev = mpci->dev;
276 	enum pin_config_param param = pinconf_to_config_param(*config);
277 	unsigned int val;
278 	int arg = 0;
279 	int ret;
280 
281 	switch (param) {
282 	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
283 		if (mpci->pin_info[pin].drv_type == MAX77620_PIN_OD_DRV)
284 			arg = 1;
285 		break;
286 
287 	case PIN_CONFIG_DRIVE_PUSH_PULL:
288 		if (mpci->pin_info[pin].drv_type == MAX77620_PIN_PP_DRV)
289 			arg = 1;
290 		break;
291 
292 	case PIN_CONFIG_BIAS_PULL_UP:
293 		ret = regmap_read(mpci->rmap, MAX77620_REG_PUE_GPIO, &val);
294 		if (ret < 0) {
295 			dev_err(dev, "Reg PUE_GPIO read failed: %d\n", ret);
296 			return ret;
297 		}
298 		if (val & BIT(pin))
299 			arg = 1;
300 		break;
301 
302 	case PIN_CONFIG_BIAS_PULL_DOWN:
303 		ret = regmap_read(mpci->rmap, MAX77620_REG_PDE_GPIO, &val);
304 		if (ret < 0) {
305 			dev_err(dev, "Reg PDE_GPIO read failed: %d\n", ret);
306 			return ret;
307 		}
308 		if (val & BIT(pin))
309 			arg = 1;
310 		break;
311 
312 	default:
313 		dev_err(dev, "Properties not supported\n");
314 		return -ENOTSUPP;
315 	}
316 
317 	*config = pinconf_to_config_packed(param, (u16)arg);
318 
319 	return 0;
320 }
321 
max77620_get_default_fps(struct max77620_pctrl_info * mpci,int addr,int * fps)322 static int max77620_get_default_fps(struct max77620_pctrl_info *mpci,
323 				    int addr, int *fps)
324 {
325 	unsigned int val;
326 	int ret;
327 
328 	ret = regmap_read(mpci->rmap, addr, &val);
329 	if (ret < 0) {
330 		dev_err(mpci->dev, "Reg PUE_GPIO read failed: %d\n", ret);
331 		return ret;
332 	}
333 	*fps = (val & MAX77620_FPS_SRC_MASK) >> MAX77620_FPS_SRC_SHIFT;
334 
335 	return 0;
336 }
337 
max77620_set_fps_param(struct max77620_pctrl_info * mpci,int pin,int param)338 static int max77620_set_fps_param(struct max77620_pctrl_info *mpci,
339 				  int pin, int param)
340 {
341 	struct max77620_fps_config *fps_config = &mpci->fps_config[pin];
342 	int addr, ret;
343 	int param_val;
344 	int mask, shift;
345 
346 	if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
347 		return 0;
348 
349 	addr = MAX77620_REG_FPS_GPIO1 + pin - 1;
350 	switch (param) {
351 	case MAX77620_ACTIVE_FPS_SOURCE:
352 	case MAX77620_SUSPEND_FPS_SOURCE:
353 		mask = MAX77620_FPS_SRC_MASK;
354 		shift = MAX77620_FPS_SRC_SHIFT;
355 		param_val = fps_config->active_fps_src;
356 		if (param == MAX77620_SUSPEND_FPS_SOURCE)
357 			param_val = fps_config->suspend_fps_src;
358 		break;
359 
360 	case MAX77620_ACTIVE_FPS_POWER_ON_SLOTS:
361 	case MAX77620_SUSPEND_FPS_POWER_ON_SLOTS:
362 		mask = MAX77620_FPS_PU_PERIOD_MASK;
363 		shift = MAX77620_FPS_PU_PERIOD_SHIFT;
364 		param_val = fps_config->active_power_up_slots;
365 		if (param == MAX77620_SUSPEND_FPS_POWER_ON_SLOTS)
366 			param_val = fps_config->suspend_power_up_slots;
367 		break;
368 
369 	case MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS:
370 	case MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS:
371 		mask = MAX77620_FPS_PD_PERIOD_MASK;
372 		shift = MAX77620_FPS_PD_PERIOD_SHIFT;
373 		param_val = fps_config->active_power_down_slots;
374 		if (param == MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS)
375 			param_val = fps_config->suspend_power_down_slots;
376 		break;
377 
378 	default:
379 		dev_err(mpci->dev, "Invalid parameter %d for pin %d\n",
380 			param, pin);
381 		return -EINVAL;
382 	}
383 
384 	if (param_val < 0)
385 		return 0;
386 
387 	ret = regmap_update_bits(mpci->rmap, addr, mask, param_val << shift);
388 	if (ret < 0)
389 		dev_err(mpci->dev, "Reg 0x%02x update failed %d\n", addr, ret);
390 
391 	return ret;
392 }
393 
max77620_pinconf_set(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * configs,unsigned int num_configs)394 static int max77620_pinconf_set(struct pinctrl_dev *pctldev,
395 				unsigned int pin, unsigned long *configs,
396 				unsigned int num_configs)
397 {
398 	struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
399 	struct device *dev = mpci->dev;
400 	struct max77620_fps_config *fps_config;
401 	int param;
402 	u32 param_val;
403 	unsigned int val;
404 	unsigned int pu_val;
405 	unsigned int pd_val;
406 	int addr, ret;
407 	int i;
408 
409 	for (i = 0; i < num_configs; i++) {
410 		param = pinconf_to_config_param(configs[i]);
411 		param_val = pinconf_to_config_argument(configs[i]);
412 
413 		switch (param) {
414 		case PIN_CONFIG_DRIVE_OPEN_DRAIN:
415 			val = param_val ? 0 : 1;
416 			ret = regmap_update_bits(mpci->rmap,
417 						 MAX77620_REG_GPIO0 + pin,
418 						 MAX77620_CNFG_GPIO_DRV_MASK,
419 						 val);
420 			if (ret)
421 				goto report_update_failure;
422 
423 			mpci->pin_info[pin].drv_type = val ?
424 				MAX77620_PIN_PP_DRV : MAX77620_PIN_OD_DRV;
425 			break;
426 
427 		case PIN_CONFIG_DRIVE_PUSH_PULL:
428 			val = param_val ? 1 : 0;
429 			ret = regmap_update_bits(mpci->rmap,
430 						 MAX77620_REG_GPIO0 + pin,
431 						 MAX77620_CNFG_GPIO_DRV_MASK,
432 						 val);
433 			if (ret)
434 				goto report_update_failure;
435 
436 			mpci->pin_info[pin].drv_type = val ?
437 				MAX77620_PIN_PP_DRV : MAX77620_PIN_OD_DRV;
438 			break;
439 
440 		case MAX77620_ACTIVE_FPS_SOURCE:
441 		case MAX77620_ACTIVE_FPS_POWER_ON_SLOTS:
442 		case MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS:
443 			if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
444 				return -EINVAL;
445 
446 			fps_config = &mpci->fps_config[pin];
447 
448 			if ((param == MAX77620_ACTIVE_FPS_SOURCE) &&
449 			    (param_val == MAX77620_FPS_SRC_DEF)) {
450 				addr = MAX77620_REG_FPS_GPIO1 + pin - 1;
451 				ret = max77620_get_default_fps(
452 						mpci, addr,
453 						&fps_config->active_fps_src);
454 				if (ret < 0)
455 					return ret;
456 				break;
457 			}
458 
459 			if (param == MAX77620_ACTIVE_FPS_SOURCE)
460 				fps_config->active_fps_src = param_val;
461 			else if (param == MAX77620_ACTIVE_FPS_POWER_ON_SLOTS)
462 				fps_config->active_power_up_slots = param_val;
463 			else
464 				fps_config->active_power_down_slots = param_val;
465 
466 			ret = max77620_set_fps_param(mpci, pin, param);
467 			if (ret < 0)
468 				return ret;
469 			break;
470 
471 		case MAX77620_SUSPEND_FPS_SOURCE:
472 		case MAX77620_SUSPEND_FPS_POWER_ON_SLOTS:
473 		case MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS:
474 			if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
475 				return -EINVAL;
476 
477 			fps_config = &mpci->fps_config[pin];
478 
479 			if ((param == MAX77620_SUSPEND_FPS_SOURCE) &&
480 			    (param_val == MAX77620_FPS_SRC_DEF)) {
481 				addr = MAX77620_REG_FPS_GPIO1 + pin - 1;
482 				ret = max77620_get_default_fps(
483 						mpci, addr,
484 						&fps_config->suspend_fps_src);
485 				if (ret < 0)
486 					return ret;
487 				break;
488 			}
489 
490 			if (param == MAX77620_SUSPEND_FPS_SOURCE)
491 				fps_config->suspend_fps_src = param_val;
492 			else if (param == MAX77620_SUSPEND_FPS_POWER_ON_SLOTS)
493 				fps_config->suspend_power_up_slots = param_val;
494 			else
495 				fps_config->suspend_power_down_slots =
496 								param_val;
497 			break;
498 
499 		case PIN_CONFIG_BIAS_PULL_UP:
500 		case PIN_CONFIG_BIAS_PULL_DOWN:
501 			pu_val = (param == PIN_CONFIG_BIAS_PULL_UP) ?
502 							BIT(pin) : 0;
503 			pd_val = (param == PIN_CONFIG_BIAS_PULL_DOWN) ?
504 							BIT(pin) : 0;
505 
506 			ret = regmap_update_bits(mpci->rmap,
507 						 MAX77620_REG_PUE_GPIO,
508 						 BIT(pin), pu_val);
509 			if (ret < 0) {
510 				dev_err(dev, "PUE_GPIO update failed: %d\n",
511 					ret);
512 				return ret;
513 			}
514 
515 			ret = regmap_update_bits(mpci->rmap,
516 						 MAX77620_REG_PDE_GPIO,
517 						 BIT(pin), pd_val);
518 			if (ret < 0) {
519 				dev_err(dev, "PDE_GPIO update failed: %d\n",
520 					ret);
521 				return ret;
522 			}
523 			break;
524 
525 		default:
526 			dev_err(dev, "Properties not supported\n");
527 			return -ENOTSUPP;
528 		}
529 	}
530 
531 	return 0;
532 
533 report_update_failure:
534 	dev_err(dev, "Reg 0x%02x update failed %d\n",
535 		MAX77620_REG_GPIO0 + pin, ret);
536 	return ret;
537 }
538 
539 static const struct pinconf_ops max77620_pinconf_ops = {
540 	.pin_config_get = max77620_pinconf_get,
541 	.pin_config_set = max77620_pinconf_set,
542 };
543 
544 static struct pinctrl_desc max77620_pinctrl_desc = {
545 	.pctlops = &max77620_pinctrl_ops,
546 	.pmxops = &max77620_pinmux_ops,
547 	.confops = &max77620_pinconf_ops,
548 };
549 
max77620_pinctrl_probe(struct platform_device * pdev)550 static int max77620_pinctrl_probe(struct platform_device *pdev)
551 {
552 	struct max77620_chip *max77620 = dev_get_drvdata(pdev->dev.parent);
553 	struct max77620_pctrl_info *mpci;
554 	int i;
555 
556 	device_set_node(&pdev->dev, dev_fwnode(pdev->dev.parent));
557 
558 	mpci = devm_kzalloc(&pdev->dev, sizeof(*mpci), GFP_KERNEL);
559 	if (!mpci)
560 		return -ENOMEM;
561 
562 	mpci->dev = &pdev->dev;
563 	mpci->rmap = max77620->rmap;
564 
565 	mpci->pins = max77620_pins_desc;
566 	mpci->num_pins = ARRAY_SIZE(max77620_pins_desc);
567 	mpci->functions = max77620_pin_function;
568 	mpci->num_functions = ARRAY_SIZE(max77620_pin_function);
569 	mpci->pin_groups = max77620_pingroups;
570 	mpci->num_pin_groups = ARRAY_SIZE(max77620_pingroups);
571 	platform_set_drvdata(pdev, mpci);
572 
573 	max77620_pinctrl_desc.name = dev_name(&pdev->dev);
574 	max77620_pinctrl_desc.pins = max77620_pins_desc;
575 	max77620_pinctrl_desc.npins = ARRAY_SIZE(max77620_pins_desc);
576 	max77620_pinctrl_desc.num_custom_params =
577 				ARRAY_SIZE(max77620_cfg_params);
578 	max77620_pinctrl_desc.custom_params = max77620_cfg_params;
579 
580 	for (i = 0; i < MAX77620_PIN_NUM; ++i) {
581 		mpci->fps_config[i].active_fps_src = -1;
582 		mpci->fps_config[i].active_power_up_slots = -1;
583 		mpci->fps_config[i].active_power_down_slots = -1;
584 		mpci->fps_config[i].suspend_fps_src = -1;
585 		mpci->fps_config[i].suspend_power_up_slots = -1;
586 		mpci->fps_config[i].suspend_power_down_slots = -1;
587 	}
588 
589 	mpci->pctl = devm_pinctrl_register(&pdev->dev, &max77620_pinctrl_desc,
590 					   mpci);
591 	if (IS_ERR(mpci->pctl)) {
592 		dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
593 		return PTR_ERR(mpci->pctl);
594 	}
595 
596 	return 0;
597 }
598 
599 #ifdef CONFIG_PM_SLEEP
600 static int max77620_suspend_fps_param[] = {
601 	MAX77620_SUSPEND_FPS_SOURCE,
602 	MAX77620_SUSPEND_FPS_POWER_ON_SLOTS,
603 	MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS,
604 };
605 
606 static int max77620_active_fps_param[] = {
607 	MAX77620_ACTIVE_FPS_SOURCE,
608 	MAX77620_ACTIVE_FPS_POWER_ON_SLOTS,
609 	MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS,
610 };
611 
max77620_pinctrl_suspend(struct device * dev)612 static int max77620_pinctrl_suspend(struct device *dev)
613 {
614 	struct max77620_pctrl_info *mpci = dev_get_drvdata(dev);
615 	int pin, p;
616 
617 	for (pin = 0; pin < MAX77620_PIN_NUM; ++pin) {
618 		if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
619 			continue;
620 		for (p = 0; p < 3; ++p)
621 			max77620_set_fps_param(
622 				mpci, pin, max77620_suspend_fps_param[p]);
623 	}
624 
625 	return 0;
626 };
627 
max77620_pinctrl_resume(struct device * dev)628 static int max77620_pinctrl_resume(struct device *dev)
629 {
630 	struct max77620_pctrl_info *mpci = dev_get_drvdata(dev);
631 	int pin, p;
632 
633 	for (pin = 0; pin < MAX77620_PIN_NUM; ++pin) {
634 		if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
635 			continue;
636 		for (p = 0; p < 3; ++p)
637 			max77620_set_fps_param(
638 				mpci, pin, max77620_active_fps_param[p]);
639 	}
640 
641 	return 0;
642 }
643 #endif
644 
645 static const struct dev_pm_ops max77620_pinctrl_pm_ops = {
646 	SET_SYSTEM_SLEEP_PM_OPS(
647 		max77620_pinctrl_suspend, max77620_pinctrl_resume)
648 };
649 
650 static const struct platform_device_id max77620_pinctrl_devtype[] = {
651 	{ .name = "max77620-pinctrl", },
652 	{ .name = "max20024-pinctrl", },
653 	{},
654 };
655 MODULE_DEVICE_TABLE(platform, max77620_pinctrl_devtype);
656 
657 static struct platform_driver max77620_pinctrl_driver = {
658 	.driver = {
659 		.name = "max77620-pinctrl",
660 		.pm = &max77620_pinctrl_pm_ops,
661 	},
662 	.probe = max77620_pinctrl_probe,
663 	.id_table = max77620_pinctrl_devtype,
664 };
665 
666 module_platform_driver(max77620_pinctrl_driver);
667 
668 MODULE_DESCRIPTION("MAX77620/MAX20024 pin control driver");
669 MODULE_AUTHOR("Chaitanya Bandi<bandik@nvidia.com>");
670 MODULE_AUTHOR("Laxman Dewangan<ldewangan@nvidia.com>");
671 MODULE_LICENSE("GPL v2");
672