183d290c5STom Rini // SPDX-License-Identifier: GPL-2.0
2403e9cbcSPhilipp Tomsich /*
3403e9cbcSPhilipp Tomsich * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
4403e9cbcSPhilipp Tomsich */
5403e9cbcSPhilipp Tomsich
6403e9cbcSPhilipp Tomsich #include <common.h>
7403e9cbcSPhilipp Tomsich #include <clk.h>
8403e9cbcSPhilipp Tomsich #include <dm.h>
9403e9cbcSPhilipp Tomsich #include <dt-bindings/memory/rk3368-dmc.h>
10403e9cbcSPhilipp Tomsich #include <dt-structs.h>
11403e9cbcSPhilipp Tomsich #include <ram.h>
12403e9cbcSPhilipp Tomsich #include <regmap.h>
13403e9cbcSPhilipp Tomsich #include <syscon.h>
14403e9cbcSPhilipp Tomsich #include <asm/io.h>
15403e9cbcSPhilipp Tomsich #include <asm/arch/clock.h>
16403e9cbcSPhilipp Tomsich #include <asm/arch/cru_rk3368.h>
17403e9cbcSPhilipp Tomsich #include <asm/arch/grf_rk3368.h>
18403e9cbcSPhilipp Tomsich #include <asm/arch/ddr_rk3368.h>
19403e9cbcSPhilipp Tomsich #include <asm/arch/sdram.h>
20403e9cbcSPhilipp Tomsich #include <asm/arch/sdram_common.h>
21403e9cbcSPhilipp Tomsich
22403e9cbcSPhilipp Tomsich struct dram_info {
23403e9cbcSPhilipp Tomsich struct ram_info info;
24403e9cbcSPhilipp Tomsich struct clk ddr_clk;
25403e9cbcSPhilipp Tomsich struct rk3368_cru *cru;
26403e9cbcSPhilipp Tomsich struct rk3368_grf *grf;
27403e9cbcSPhilipp Tomsich struct rk3368_ddr_pctl *pctl;
28403e9cbcSPhilipp Tomsich struct rk3368_ddrphy *phy;
29403e9cbcSPhilipp Tomsich struct rk3368_pmu_grf *pmugrf;
30403e9cbcSPhilipp Tomsich struct rk3368_msch *msch;
31403e9cbcSPhilipp Tomsich };
32403e9cbcSPhilipp Tomsich
33403e9cbcSPhilipp Tomsich struct rk3368_sdram_params {
34403e9cbcSPhilipp Tomsich #if CONFIG_IS_ENABLED(OF_PLATDATA)
35403e9cbcSPhilipp Tomsich struct dtd_rockchip_rk3368_dmc of_plat;
36403e9cbcSPhilipp Tomsich #endif
37403e9cbcSPhilipp Tomsich struct rk3288_sdram_pctl_timing pctl_timing;
38403e9cbcSPhilipp Tomsich u32 trefi_mem_ddr3;
39403e9cbcSPhilipp Tomsich struct rk3288_sdram_channel chan;
40403e9cbcSPhilipp Tomsich struct regmap *map;
41403e9cbcSPhilipp Tomsich u32 ddr_freq;
42403e9cbcSPhilipp Tomsich u32 memory_schedule;
43403e9cbcSPhilipp Tomsich u32 ddr_speed_bin;
44403e9cbcSPhilipp Tomsich u32 tfaw_mult;
45403e9cbcSPhilipp Tomsich };
46403e9cbcSPhilipp Tomsich
47403e9cbcSPhilipp Tomsich /* PTCL bits */
48403e9cbcSPhilipp Tomsich enum {
49403e9cbcSPhilipp Tomsich /* PCTL_DFISTCFG0 */
50403e9cbcSPhilipp Tomsich DFI_INIT_START = BIT(0),
51403e9cbcSPhilipp Tomsich DFI_DATA_BYTE_DISABLE_EN = BIT(2),
52403e9cbcSPhilipp Tomsich
53403e9cbcSPhilipp Tomsich /* PCTL_DFISTCFG1 */
54403e9cbcSPhilipp Tomsich DFI_DRAM_CLK_SR_EN = BIT(0),
55403e9cbcSPhilipp Tomsich DFI_DRAM_CLK_DPD_EN = BIT(1),
56403e9cbcSPhilipp Tomsich ODT_LEN_BL8_W_SHIFT = 16,
57403e9cbcSPhilipp Tomsich
58403e9cbcSPhilipp Tomsich /* PCTL_DFISTCFG2 */
59403e9cbcSPhilipp Tomsich DFI_PARITY_INTR_EN = BIT(0),
60403e9cbcSPhilipp Tomsich DFI_PARITY_EN = BIT(1),
61403e9cbcSPhilipp Tomsich
62403e9cbcSPhilipp Tomsich /* PCTL_DFILPCFG0 */
63403e9cbcSPhilipp Tomsich TLP_RESP_TIME_SHIFT = 16,
64403e9cbcSPhilipp Tomsich LP_SR_EN = BIT(8),
65403e9cbcSPhilipp Tomsich LP_PD_EN = BIT(0),
66403e9cbcSPhilipp Tomsich
67403e9cbcSPhilipp Tomsich /* PCTL_DFIODTCFG */
68403e9cbcSPhilipp Tomsich RANK0_ODT_WRITE_SEL = BIT(3),
69403e9cbcSPhilipp Tomsich RANK1_ODT_WRITE_SEL = BIT(11),
70403e9cbcSPhilipp Tomsich
71403e9cbcSPhilipp Tomsich /* PCTL_SCFG */
72403e9cbcSPhilipp Tomsich HW_LOW_POWER_EN = BIT(0),
73403e9cbcSPhilipp Tomsich
74403e9cbcSPhilipp Tomsich /* PCTL_MCMD */
75403e9cbcSPhilipp Tomsich START_CMD = BIT(31),
76403e9cbcSPhilipp Tomsich MCMD_RANK0 = BIT(20),
77403e9cbcSPhilipp Tomsich MCMD_RANK1 = BIT(21),
78403e9cbcSPhilipp Tomsich DESELECT_CMD = 0,
79403e9cbcSPhilipp Tomsich PREA_CMD,
80403e9cbcSPhilipp Tomsich REF_CMD,
81403e9cbcSPhilipp Tomsich MRS_CMD,
82403e9cbcSPhilipp Tomsich ZQCS_CMD,
83403e9cbcSPhilipp Tomsich ZQCL_CMD,
84403e9cbcSPhilipp Tomsich RSTL_CMD,
85403e9cbcSPhilipp Tomsich MRR_CMD = 8,
86403e9cbcSPhilipp Tomsich DPDE_CMD,
87403e9cbcSPhilipp Tomsich
88403e9cbcSPhilipp Tomsich /* PCTL_POWCTL */
89403e9cbcSPhilipp Tomsich POWER_UP_START = BIT(0),
90403e9cbcSPhilipp Tomsich
91403e9cbcSPhilipp Tomsich /* PCTL_POWSTAT */
92403e9cbcSPhilipp Tomsich POWER_UP_DONE = BIT(0),
93403e9cbcSPhilipp Tomsich
94403e9cbcSPhilipp Tomsich /* PCTL_SCTL */
95403e9cbcSPhilipp Tomsich INIT_STATE = 0,
96403e9cbcSPhilipp Tomsich CFG_STATE,
97403e9cbcSPhilipp Tomsich GO_STATE,
98403e9cbcSPhilipp Tomsich SLEEP_STATE,
99403e9cbcSPhilipp Tomsich WAKEUP_STATE,
100403e9cbcSPhilipp Tomsich
101403e9cbcSPhilipp Tomsich /* PCTL_STAT */
102403e9cbcSPhilipp Tomsich LP_TRIG_SHIFT = 4,
103403e9cbcSPhilipp Tomsich LP_TRIG_MASK = 7,
104403e9cbcSPhilipp Tomsich PCTL_STAT_MSK = 7,
105403e9cbcSPhilipp Tomsich INIT_MEM = 0,
106403e9cbcSPhilipp Tomsich CONFIG,
107403e9cbcSPhilipp Tomsich CONFIG_REQ,
108403e9cbcSPhilipp Tomsich ACCESS,
109403e9cbcSPhilipp Tomsich ACCESS_REQ,
110403e9cbcSPhilipp Tomsich LOW_POWER,
111403e9cbcSPhilipp Tomsich LOW_POWER_ENTRY_REQ,
112403e9cbcSPhilipp Tomsich LOW_POWER_EXIT_REQ,
113403e9cbcSPhilipp Tomsich
114403e9cbcSPhilipp Tomsich /* PCTL_MCFG */
115403e9cbcSPhilipp Tomsich DDR2_DDR3_BL_8 = BIT(0),
116403e9cbcSPhilipp Tomsich DDR3_EN = BIT(5),
117403e9cbcSPhilipp Tomsich TFAW_TRRD_MULT4 = (0 << 18),
118403e9cbcSPhilipp Tomsich TFAW_TRRD_MULT5 = (1 << 18),
119403e9cbcSPhilipp Tomsich TFAW_TRRD_MULT6 = (2 << 18),
120403e9cbcSPhilipp Tomsich };
121403e9cbcSPhilipp Tomsich
122403e9cbcSPhilipp Tomsich #define DDR3_MR0_WR(n) \
123403e9cbcSPhilipp Tomsich ((n <= 8) ? ((n - 4) << 9) : (((n >> 1) & 0x7) << 9))
124403e9cbcSPhilipp Tomsich #define DDR3_MR0_CL(n) \
125403e9cbcSPhilipp Tomsich ((((n - 4) & 0x7) << 4) | (((n - 4) & 0x8) >> 2))
126403e9cbcSPhilipp Tomsich #define DDR3_MR0_BL8 \
127403e9cbcSPhilipp Tomsich (0 << 0)
128403e9cbcSPhilipp Tomsich #define DDR3_MR0_DLL_RESET \
129403e9cbcSPhilipp Tomsich (1 << 8)
130403e9cbcSPhilipp Tomsich #define DDR3_MR1_RTT120OHM \
131403e9cbcSPhilipp Tomsich ((0 << 9) | (1 << 6) | (0 << 2))
132403e9cbcSPhilipp Tomsich #define DDR3_MR2_TWL(n) \
133403e9cbcSPhilipp Tomsich (((n - 5) & 0x7) << 3)
134403e9cbcSPhilipp Tomsich
135403e9cbcSPhilipp Tomsich
136403e9cbcSPhilipp Tomsich #ifdef CONFIG_TPL_BUILD
137403e9cbcSPhilipp Tomsich
ddr_set_noc_spr_err_stall(struct rk3368_grf * grf,bool enable)138403e9cbcSPhilipp Tomsich static void ddr_set_noc_spr_err_stall(struct rk3368_grf *grf, bool enable)
139403e9cbcSPhilipp Tomsich {
140403e9cbcSPhilipp Tomsich if (enable)
141403e9cbcSPhilipp Tomsich rk_setreg(&grf->ddrc0_con0, NOC_RSP_ERR_STALL);
142403e9cbcSPhilipp Tomsich else
143403e9cbcSPhilipp Tomsich rk_clrreg(&grf->ddrc0_con0, NOC_RSP_ERR_STALL);
144403e9cbcSPhilipp Tomsich }
145403e9cbcSPhilipp Tomsich
ddr_set_ddr3_mode(struct rk3368_grf * grf,bool ddr3_mode)146403e9cbcSPhilipp Tomsich static void ddr_set_ddr3_mode(struct rk3368_grf *grf, bool ddr3_mode)
147403e9cbcSPhilipp Tomsich {
148403e9cbcSPhilipp Tomsich if (ddr3_mode)
149403e9cbcSPhilipp Tomsich rk_setreg(&grf->ddrc0_con0, MSCH0_MAINDDR3_DDR3);
150403e9cbcSPhilipp Tomsich else
151403e9cbcSPhilipp Tomsich rk_clrreg(&grf->ddrc0_con0, MSCH0_MAINDDR3_DDR3);
152403e9cbcSPhilipp Tomsich }
153403e9cbcSPhilipp Tomsich
ddrphy_config(struct rk3368_ddrphy * phy,u32 tcl,u32 tal,u32 tcwl)154403e9cbcSPhilipp Tomsich static void ddrphy_config(struct rk3368_ddrphy *phy,
155403e9cbcSPhilipp Tomsich u32 tcl, u32 tal, u32 tcwl)
156403e9cbcSPhilipp Tomsich {
157403e9cbcSPhilipp Tomsich int i;
158403e9cbcSPhilipp Tomsich
159403e9cbcSPhilipp Tomsich /* Set to DDR3 mode */
160403e9cbcSPhilipp Tomsich clrsetbits_le32(&phy->reg[1], 0x3, 0x0);
161403e9cbcSPhilipp Tomsich
162403e9cbcSPhilipp Tomsich /* DDRPHY_REGB: CL, AL */
163403e9cbcSPhilipp Tomsich clrsetbits_le32(&phy->reg[0xb], 0xff, tcl << 4 | tal);
164403e9cbcSPhilipp Tomsich /* DDRPHY_REGC: CWL */
165403e9cbcSPhilipp Tomsich clrsetbits_le32(&phy->reg[0xc], 0x0f, tcwl);
166403e9cbcSPhilipp Tomsich
167403e9cbcSPhilipp Tomsich /* Update drive-strength */
168403e9cbcSPhilipp Tomsich writel(0xcc, &phy->reg[0x11]);
169403e9cbcSPhilipp Tomsich writel(0xaa, &phy->reg[0x16]);
170403e9cbcSPhilipp Tomsich /*
171403e9cbcSPhilipp Tomsich * Update NRCOMP/PRCOMP for all 4 channels (for details of all
172403e9cbcSPhilipp Tomsich * affected registers refer to the documentation of DDRPHY_REG20
173403e9cbcSPhilipp Tomsich * and DDRPHY_REG21 in the RK3368 TRM.
174403e9cbcSPhilipp Tomsich */
175403e9cbcSPhilipp Tomsich for (i = 0; i < 4; ++i) {
176403e9cbcSPhilipp Tomsich writel(0xcc, &phy->reg[0x20 + i * 0x10]);
177403e9cbcSPhilipp Tomsich writel(0x44, &phy->reg[0x21 + i * 0x10]);
178403e9cbcSPhilipp Tomsich }
179403e9cbcSPhilipp Tomsich
180403e9cbcSPhilipp Tomsich /* Enable write-leveling calibration bypass */
181403e9cbcSPhilipp Tomsich setbits_le32(&phy->reg[2], BIT(3));
182403e9cbcSPhilipp Tomsich }
183403e9cbcSPhilipp Tomsich
copy_to_reg(u32 * dest,const u32 * src,u32 n)184403e9cbcSPhilipp Tomsich static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
185403e9cbcSPhilipp Tomsich {
186403e9cbcSPhilipp Tomsich int i;
187403e9cbcSPhilipp Tomsich
188403e9cbcSPhilipp Tomsich for (i = 0; i < n / sizeof(u32); i++)
189403e9cbcSPhilipp Tomsich writel(*src++, dest++);
190403e9cbcSPhilipp Tomsich }
191403e9cbcSPhilipp Tomsich
send_command(struct rk3368_ddr_pctl * pctl,u32 rank,u32 cmd)192403e9cbcSPhilipp Tomsich static void send_command(struct rk3368_ddr_pctl *pctl, u32 rank, u32 cmd)
193403e9cbcSPhilipp Tomsich {
194403e9cbcSPhilipp Tomsich u32 mcmd = START_CMD | cmd | rank;
195403e9cbcSPhilipp Tomsich
196403e9cbcSPhilipp Tomsich debug("%s: writing %x to MCMD\n", __func__, mcmd);
197403e9cbcSPhilipp Tomsich writel(mcmd, &pctl->mcmd);
198403e9cbcSPhilipp Tomsich while (readl(&pctl->mcmd) & START_CMD)
199403e9cbcSPhilipp Tomsich /* spin */;
200403e9cbcSPhilipp Tomsich }
201403e9cbcSPhilipp Tomsich
send_mrs(struct rk3368_ddr_pctl * pctl,u32 rank,u32 mr_num,u32 mr_data)202403e9cbcSPhilipp Tomsich static void send_mrs(struct rk3368_ddr_pctl *pctl,
203403e9cbcSPhilipp Tomsich u32 rank, u32 mr_num, u32 mr_data)
204403e9cbcSPhilipp Tomsich {
205403e9cbcSPhilipp Tomsich u32 mcmd = START_CMD | MRS_CMD | rank | (mr_num << 17) | (mr_data << 4);
206403e9cbcSPhilipp Tomsich
207403e9cbcSPhilipp Tomsich debug("%s: writing %x to MCMD\n", __func__, mcmd);
208403e9cbcSPhilipp Tomsich writel(mcmd, &pctl->mcmd);
209403e9cbcSPhilipp Tomsich while (readl(&pctl->mcmd) & START_CMD)
210403e9cbcSPhilipp Tomsich /* spin */;
211403e9cbcSPhilipp Tomsich }
212403e9cbcSPhilipp Tomsich
memory_init(struct rk3368_ddr_pctl * pctl,struct rk3368_sdram_params * params)213403e9cbcSPhilipp Tomsich static int memory_init(struct rk3368_ddr_pctl *pctl,
214403e9cbcSPhilipp Tomsich struct rk3368_sdram_params *params)
215403e9cbcSPhilipp Tomsich {
216403e9cbcSPhilipp Tomsich u32 mr[4];
217403e9cbcSPhilipp Tomsich const ulong timeout_ms = 500;
218403e9cbcSPhilipp Tomsich ulong tmp;
219403e9cbcSPhilipp Tomsich
220403e9cbcSPhilipp Tomsich /*
221403e9cbcSPhilipp Tomsich * Power up DRAM by DDR_PCTL_POWCTL[0] register of PCTL and
222403e9cbcSPhilipp Tomsich * wait power up DRAM finish with DDR_PCTL_POWSTAT[0] register
223403e9cbcSPhilipp Tomsich * of PCTL.
224403e9cbcSPhilipp Tomsich */
225403e9cbcSPhilipp Tomsich writel(POWER_UP_START, &pctl->powctl);
226403e9cbcSPhilipp Tomsich
227403e9cbcSPhilipp Tomsich tmp = get_timer(0);
228403e9cbcSPhilipp Tomsich do {
229403e9cbcSPhilipp Tomsich if (get_timer(tmp) > timeout_ms) {
2309b643e31SMasahiro Yamada pr_err("%s: POWER_UP_START did not complete in %ld ms\n",
231403e9cbcSPhilipp Tomsich __func__, timeout_ms);
232403e9cbcSPhilipp Tomsich return -ETIME;
233403e9cbcSPhilipp Tomsich }
234403e9cbcSPhilipp Tomsich } while (!(readl(&pctl->powstat) & POWER_UP_DONE));
235403e9cbcSPhilipp Tomsich
236403e9cbcSPhilipp Tomsich /* Configure MR0 through MR3 */
237403e9cbcSPhilipp Tomsich mr[0] = DDR3_MR0_WR(params->pctl_timing.twr) |
238403e9cbcSPhilipp Tomsich DDR3_MR0_CL(params->pctl_timing.tcl) |
239403e9cbcSPhilipp Tomsich DDR3_MR0_DLL_RESET;
240403e9cbcSPhilipp Tomsich mr[1] = DDR3_MR1_RTT120OHM;
241403e9cbcSPhilipp Tomsich mr[2] = DDR3_MR2_TWL(params->pctl_timing.tcwl);
242403e9cbcSPhilipp Tomsich mr[3] = 0;
243403e9cbcSPhilipp Tomsich
244403e9cbcSPhilipp Tomsich /*
245403e9cbcSPhilipp Tomsich * Also see RK3368 Technical Reference Manual:
246403e9cbcSPhilipp Tomsich * "16.6.2 Initialization (DDR3 Initialization Sequence)"
247403e9cbcSPhilipp Tomsich */
248403e9cbcSPhilipp Tomsich send_command(pctl, MCMD_RANK0 | MCMD_RANK1, DESELECT_CMD);
249403e9cbcSPhilipp Tomsich udelay(1);
250403e9cbcSPhilipp Tomsich send_command(pctl, MCMD_RANK0 | MCMD_RANK1, PREA_CMD);
251403e9cbcSPhilipp Tomsich send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 2, mr[2]);
252403e9cbcSPhilipp Tomsich send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 3, mr[3]);
253403e9cbcSPhilipp Tomsich send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 1, mr[1]);
254403e9cbcSPhilipp Tomsich send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 0, mr[0]);
255403e9cbcSPhilipp Tomsich send_command(pctl, MCMD_RANK0 | MCMD_RANK1, ZQCL_CMD);
256403e9cbcSPhilipp Tomsich
257403e9cbcSPhilipp Tomsich return 0;
258403e9cbcSPhilipp Tomsich }
259403e9cbcSPhilipp Tomsich
move_to_config_state(struct rk3368_ddr_pctl * pctl)260403e9cbcSPhilipp Tomsich static void move_to_config_state(struct rk3368_ddr_pctl *pctl)
261403e9cbcSPhilipp Tomsich {
262403e9cbcSPhilipp Tomsich /*
263403e9cbcSPhilipp Tomsich * Also see RK3368 Technical Reference Manual:
264403e9cbcSPhilipp Tomsich * "16.6.1 State transition of PCTL (Moving to Config State)"
265403e9cbcSPhilipp Tomsich */
266403e9cbcSPhilipp Tomsich u32 state = readl(&pctl->stat) & PCTL_STAT_MSK;
267403e9cbcSPhilipp Tomsich
268403e9cbcSPhilipp Tomsich switch (state) {
269403e9cbcSPhilipp Tomsich case LOW_POWER:
270403e9cbcSPhilipp Tomsich writel(WAKEUP_STATE, &pctl->sctl);
271403e9cbcSPhilipp Tomsich while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS)
272403e9cbcSPhilipp Tomsich /* spin */;
273403e9cbcSPhilipp Tomsich
274403e9cbcSPhilipp Tomsich /* fall-through */
275403e9cbcSPhilipp Tomsich case ACCESS:
276403e9cbcSPhilipp Tomsich case INIT_MEM:
277403e9cbcSPhilipp Tomsich writel(CFG_STATE, &pctl->sctl);
278403e9cbcSPhilipp Tomsich while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG)
279403e9cbcSPhilipp Tomsich /* spin */;
280403e9cbcSPhilipp Tomsich break;
281403e9cbcSPhilipp Tomsich
282403e9cbcSPhilipp Tomsich case CONFIG:
283403e9cbcSPhilipp Tomsich return;
284403e9cbcSPhilipp Tomsich
285403e9cbcSPhilipp Tomsich default:
286403e9cbcSPhilipp Tomsich break;
287403e9cbcSPhilipp Tomsich }
288403e9cbcSPhilipp Tomsich }
289403e9cbcSPhilipp Tomsich
move_to_access_state(struct rk3368_ddr_pctl * pctl)290403e9cbcSPhilipp Tomsich static void move_to_access_state(struct rk3368_ddr_pctl *pctl)
291403e9cbcSPhilipp Tomsich {
292403e9cbcSPhilipp Tomsich /*
293403e9cbcSPhilipp Tomsich * Also see RK3368 Technical Reference Manual:
294403e9cbcSPhilipp Tomsich * "16.6.1 State transition of PCTL (Moving to Access State)"
295403e9cbcSPhilipp Tomsich */
296403e9cbcSPhilipp Tomsich u32 state = readl(&pctl->stat) & PCTL_STAT_MSK;
297403e9cbcSPhilipp Tomsich
298403e9cbcSPhilipp Tomsich switch (state) {
299403e9cbcSPhilipp Tomsich case LOW_POWER:
300403e9cbcSPhilipp Tomsich if (((readl(&pctl->stat) >> LP_TRIG_SHIFT) &
301403e9cbcSPhilipp Tomsich LP_TRIG_MASK) == 1)
302403e9cbcSPhilipp Tomsich return;
303403e9cbcSPhilipp Tomsich
304403e9cbcSPhilipp Tomsich writel(WAKEUP_STATE, &pctl->sctl);
305403e9cbcSPhilipp Tomsich while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS)
306403e9cbcSPhilipp Tomsich /* spin */;
307403e9cbcSPhilipp Tomsich
308403e9cbcSPhilipp Tomsich /* fall-through */
309403e9cbcSPhilipp Tomsich case INIT_MEM:
310403e9cbcSPhilipp Tomsich writel(CFG_STATE, &pctl->sctl);
311403e9cbcSPhilipp Tomsich while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG)
312403e9cbcSPhilipp Tomsich /* spin */;
313403e9cbcSPhilipp Tomsich
314403e9cbcSPhilipp Tomsich /* fall-through */
315403e9cbcSPhilipp Tomsich case CONFIG:
316403e9cbcSPhilipp Tomsich writel(GO_STATE, &pctl->sctl);
317403e9cbcSPhilipp Tomsich while ((readl(&pctl->stat) & PCTL_STAT_MSK) == CONFIG)
318403e9cbcSPhilipp Tomsich /* spin */;
319403e9cbcSPhilipp Tomsich break;
320403e9cbcSPhilipp Tomsich
321403e9cbcSPhilipp Tomsich case ACCESS:
322403e9cbcSPhilipp Tomsich return;
323403e9cbcSPhilipp Tomsich
324403e9cbcSPhilipp Tomsich default:
325403e9cbcSPhilipp Tomsich break;
326403e9cbcSPhilipp Tomsich }
327403e9cbcSPhilipp Tomsich }
328403e9cbcSPhilipp Tomsich
ddrctl_reset(struct rk3368_cru * cru)329403e9cbcSPhilipp Tomsich static void ddrctl_reset(struct rk3368_cru *cru)
330403e9cbcSPhilipp Tomsich {
331403e9cbcSPhilipp Tomsich const u32 ctl_reset = BIT(3) | BIT(2);
332403e9cbcSPhilipp Tomsich const u32 phy_reset = BIT(1) | BIT(0);
333403e9cbcSPhilipp Tomsich
334403e9cbcSPhilipp Tomsich /*
335403e9cbcSPhilipp Tomsich * The PHY reset should be released before the PCTL reset.
336403e9cbcSPhilipp Tomsich *
337403e9cbcSPhilipp Tomsich * Note that the following sequence (including the number of
338403e9cbcSPhilipp Tomsich * us to delay between releasing the PHY and PCTL reset) has
339403e9cbcSPhilipp Tomsich * been adapted per feedback received from Rockchips, so do
340403e9cbcSPhilipp Tomsich * not try to optimise.
341403e9cbcSPhilipp Tomsich */
342403e9cbcSPhilipp Tomsich rk_setreg(&cru->softrst_con[10], ctl_reset | phy_reset);
343403e9cbcSPhilipp Tomsich udelay(1);
344403e9cbcSPhilipp Tomsich rk_clrreg(&cru->softrst_con[10], phy_reset);
345403e9cbcSPhilipp Tomsich udelay(5);
346403e9cbcSPhilipp Tomsich rk_clrreg(&cru->softrst_con[10], ctl_reset);
347403e9cbcSPhilipp Tomsich }
348403e9cbcSPhilipp Tomsich
ddrphy_reset(struct rk3368_ddrphy * ddrphy)349403e9cbcSPhilipp Tomsich static void ddrphy_reset(struct rk3368_ddrphy *ddrphy)
350403e9cbcSPhilipp Tomsich {
351403e9cbcSPhilipp Tomsich /*
352403e9cbcSPhilipp Tomsich * The analog part of the PHY should be release at least 1000
353403e9cbcSPhilipp Tomsich * DRAM cycles before the digital part of the PHY (waiting for
354403e9cbcSPhilipp Tomsich * 5us will ensure this for a DRAM clock as low as 200MHz).
355403e9cbcSPhilipp Tomsich */
356403e9cbcSPhilipp Tomsich clrbits_le32(&ddrphy->reg[0], BIT(3) | BIT(2));
357403e9cbcSPhilipp Tomsich udelay(1);
358403e9cbcSPhilipp Tomsich setbits_le32(&ddrphy->reg[0], BIT(2));
359403e9cbcSPhilipp Tomsich udelay(5);
360403e9cbcSPhilipp Tomsich setbits_le32(&ddrphy->reg[0], BIT(3));
361403e9cbcSPhilipp Tomsich }
362403e9cbcSPhilipp Tomsich
ddrphy_config_delays(struct rk3368_ddrphy * ddrphy,u32 freq)363403e9cbcSPhilipp Tomsich static void ddrphy_config_delays(struct rk3368_ddrphy *ddrphy, u32 freq)
364403e9cbcSPhilipp Tomsich {
365403e9cbcSPhilipp Tomsich u32 dqs_dll_delay;
366403e9cbcSPhilipp Tomsich
367403e9cbcSPhilipp Tomsich setbits_le32(&ddrphy->reg[0x13], BIT(4));
368403e9cbcSPhilipp Tomsich clrbits_le32(&ddrphy->reg[0x14], BIT(3));
369403e9cbcSPhilipp Tomsich
370403e9cbcSPhilipp Tomsich setbits_le32(&ddrphy->reg[0x26], BIT(4));
371403e9cbcSPhilipp Tomsich clrbits_le32(&ddrphy->reg[0x27], BIT(3));
372403e9cbcSPhilipp Tomsich
373403e9cbcSPhilipp Tomsich setbits_le32(&ddrphy->reg[0x36], BIT(4));
374403e9cbcSPhilipp Tomsich clrbits_le32(&ddrphy->reg[0x37], BIT(3));
375403e9cbcSPhilipp Tomsich
376403e9cbcSPhilipp Tomsich setbits_le32(&ddrphy->reg[0x46], BIT(4));
377403e9cbcSPhilipp Tomsich clrbits_le32(&ddrphy->reg[0x47], BIT(3));
378403e9cbcSPhilipp Tomsich
379403e9cbcSPhilipp Tomsich setbits_le32(&ddrphy->reg[0x56], BIT(4));
380403e9cbcSPhilipp Tomsich clrbits_le32(&ddrphy->reg[0x57], BIT(3));
381403e9cbcSPhilipp Tomsich
382403e9cbcSPhilipp Tomsich if (freq <= 400000000)
383403e9cbcSPhilipp Tomsich setbits_le32(&ddrphy->reg[0xa4], 0x1f);
384403e9cbcSPhilipp Tomsich else
385403e9cbcSPhilipp Tomsich clrbits_le32(&ddrphy->reg[0xa4], 0x1f);
386403e9cbcSPhilipp Tomsich
387403e9cbcSPhilipp Tomsich if (freq < 681000000)
388403e9cbcSPhilipp Tomsich dqs_dll_delay = 3; /* 67.5 degree delay */
389403e9cbcSPhilipp Tomsich else
390403e9cbcSPhilipp Tomsich dqs_dll_delay = 2; /* 45 degree delay */
391403e9cbcSPhilipp Tomsich
392403e9cbcSPhilipp Tomsich writel(dqs_dll_delay, &ddrphy->reg[0x28]);
393403e9cbcSPhilipp Tomsich writel(dqs_dll_delay, &ddrphy->reg[0x38]);
394403e9cbcSPhilipp Tomsich writel(dqs_dll_delay, &ddrphy->reg[0x48]);
395403e9cbcSPhilipp Tomsich writel(dqs_dll_delay, &ddrphy->reg[0x58]);
396403e9cbcSPhilipp Tomsich }
397403e9cbcSPhilipp Tomsich
dfi_cfg(struct rk3368_ddr_pctl * pctl)398403e9cbcSPhilipp Tomsich static int dfi_cfg(struct rk3368_ddr_pctl *pctl)
399403e9cbcSPhilipp Tomsich {
400403e9cbcSPhilipp Tomsich const ulong timeout_ms = 200;
401403e9cbcSPhilipp Tomsich ulong tmp;
402403e9cbcSPhilipp Tomsich
403403e9cbcSPhilipp Tomsich writel(DFI_DATA_BYTE_DISABLE_EN, &pctl->dfistcfg0);
404403e9cbcSPhilipp Tomsich
405403e9cbcSPhilipp Tomsich writel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN,
406403e9cbcSPhilipp Tomsich &pctl->dfistcfg1);
407403e9cbcSPhilipp Tomsich writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2);
408403e9cbcSPhilipp Tomsich writel(7 << TLP_RESP_TIME_SHIFT | LP_SR_EN | LP_PD_EN,
409403e9cbcSPhilipp Tomsich &pctl->dfilpcfg0);
410403e9cbcSPhilipp Tomsich
411403e9cbcSPhilipp Tomsich writel(1, &pctl->dfitphyupdtype0);
412403e9cbcSPhilipp Tomsich
413403e9cbcSPhilipp Tomsich writel(0x1f, &pctl->dfitphyrdlat);
414403e9cbcSPhilipp Tomsich writel(0, &pctl->dfitphywrdata);
415403e9cbcSPhilipp Tomsich writel(0, &pctl->dfiupdcfg); /* phyupd and ctrlupd disabled */
416403e9cbcSPhilipp Tomsich
417403e9cbcSPhilipp Tomsich setbits_le32(&pctl->dfistcfg0, DFI_INIT_START);
418403e9cbcSPhilipp Tomsich
419403e9cbcSPhilipp Tomsich tmp = get_timer(0);
420403e9cbcSPhilipp Tomsich do {
421403e9cbcSPhilipp Tomsich if (get_timer(tmp) > timeout_ms) {
4229b643e31SMasahiro Yamada pr_err("%s: DFI init did not complete within %ld ms\n",
423403e9cbcSPhilipp Tomsich __func__, timeout_ms);
424403e9cbcSPhilipp Tomsich return -ETIME;
425403e9cbcSPhilipp Tomsich }
426403e9cbcSPhilipp Tomsich } while ((readl(&pctl->dfiststat0) & 1) == 0);
427403e9cbcSPhilipp Tomsich
428403e9cbcSPhilipp Tomsich return 0;
429403e9cbcSPhilipp Tomsich }
430403e9cbcSPhilipp Tomsich
ps_to_tCK(const u32 ps,const ulong freq)431403e9cbcSPhilipp Tomsich static inline u32 ps_to_tCK(const u32 ps, const ulong freq)
432403e9cbcSPhilipp Tomsich {
433403e9cbcSPhilipp Tomsich const ulong MHz = 1000000;
434403e9cbcSPhilipp Tomsich return DIV_ROUND_UP(ps * freq, 1000000 * MHz);
435403e9cbcSPhilipp Tomsich }
436403e9cbcSPhilipp Tomsich
ns_to_tCK(const u32 ns,const ulong freq)437403e9cbcSPhilipp Tomsich static inline u32 ns_to_tCK(const u32 ns, const ulong freq)
438403e9cbcSPhilipp Tomsich {
439403e9cbcSPhilipp Tomsich return ps_to_tCK(ns * 1000, freq);
440403e9cbcSPhilipp Tomsich }
441403e9cbcSPhilipp Tomsich
tCK_to_ps(const ulong tCK,const ulong freq)442403e9cbcSPhilipp Tomsich static inline u32 tCK_to_ps(const ulong tCK, const ulong freq)
443403e9cbcSPhilipp Tomsich {
444403e9cbcSPhilipp Tomsich const ulong MHz = 1000000;
445403e9cbcSPhilipp Tomsich return DIV_ROUND_UP(tCK * 1000000 * MHz, freq);
446403e9cbcSPhilipp Tomsich }
447403e9cbcSPhilipp Tomsich
pctl_calc_timings(struct rk3368_sdram_params * params,ulong freq)448403e9cbcSPhilipp Tomsich static int pctl_calc_timings(struct rk3368_sdram_params *params,
449403e9cbcSPhilipp Tomsich ulong freq)
450403e9cbcSPhilipp Tomsich {
451403e9cbcSPhilipp Tomsich struct rk3288_sdram_pctl_timing *pctl_timing = ¶ms->pctl_timing;
452403e9cbcSPhilipp Tomsich const ulong MHz = 1000000;
453403e9cbcSPhilipp Tomsich u32 tccd;
454403e9cbcSPhilipp Tomsich u32 tfaw_as_ps;
455403e9cbcSPhilipp Tomsich
456403e9cbcSPhilipp Tomsich if (params->ddr_speed_bin != DDR3_1600K) {
4579b643e31SMasahiro Yamada pr_err("%s: unimplemented DDR3 speed bin %d\n",
458403e9cbcSPhilipp Tomsich __func__, params->ddr_speed_bin);
459403e9cbcSPhilipp Tomsich return -1;
460403e9cbcSPhilipp Tomsich }
461403e9cbcSPhilipp Tomsich
462403e9cbcSPhilipp Tomsich /* PCTL is clocked at 1/2 the DRAM clock; err on the side of caution */
463403e9cbcSPhilipp Tomsich pctl_timing->togcnt1u = DIV_ROUND_UP(freq, 2 * MHz);
464403e9cbcSPhilipp Tomsich pctl_timing->togcnt100n = DIV_ROUND_UP(freq / 10, 2 * MHz);
465403e9cbcSPhilipp Tomsich
466403e9cbcSPhilipp Tomsich pctl_timing->tinit = 200; /* 200 usec */
467403e9cbcSPhilipp Tomsich pctl_timing->trsth = 500; /* 500 usec */
468403e9cbcSPhilipp Tomsich pctl_timing->trefi = 78; /* 7.8usec = 78 * 100ns */
469403e9cbcSPhilipp Tomsich params->trefi_mem_ddr3 = ns_to_tCK(pctl_timing->trefi * 100, freq);
470403e9cbcSPhilipp Tomsich
471403e9cbcSPhilipp Tomsich if (freq <= (400 * MHz)) {
472403e9cbcSPhilipp Tomsich pctl_timing->tcl = 6;
473403e9cbcSPhilipp Tomsich pctl_timing->tcwl = 10;
474403e9cbcSPhilipp Tomsich } else if (freq <= (533 * MHz)) {
475403e9cbcSPhilipp Tomsich pctl_timing->tcl = 8;
476403e9cbcSPhilipp Tomsich pctl_timing->tcwl = 6;
477403e9cbcSPhilipp Tomsich } else if (freq <= (666 * MHz)) {
478403e9cbcSPhilipp Tomsich pctl_timing->tcl = 10;
479403e9cbcSPhilipp Tomsich pctl_timing->tcwl = 7;
480403e9cbcSPhilipp Tomsich } else {
481403e9cbcSPhilipp Tomsich pctl_timing->tcl = 11;
482403e9cbcSPhilipp Tomsich pctl_timing->tcwl = 8;
483403e9cbcSPhilipp Tomsich }
484403e9cbcSPhilipp Tomsich
485403e9cbcSPhilipp Tomsich pctl_timing->tmrd = 4; /* 4 tCK (all speed bins) */
486403e9cbcSPhilipp Tomsich pctl_timing->trfc = ns_to_tCK(350, freq); /* tRFC: 350 (max) @ 8GBit */
487403e9cbcSPhilipp Tomsich pctl_timing->trp = max(4u, ps_to_tCK(13750, freq));
488403e9cbcSPhilipp Tomsich /*
489403e9cbcSPhilipp Tomsich * JESD-79:
490403e9cbcSPhilipp Tomsich * READ to WRITE Command Delay = RL + tCCD / 2 + 2tCK - WL
491403e9cbcSPhilipp Tomsich */
492403e9cbcSPhilipp Tomsich tccd = 4;
493403e9cbcSPhilipp Tomsich pctl_timing->trtw = pctl_timing->tcl + tccd/2 + 2 - pctl_timing->tcwl;
494403e9cbcSPhilipp Tomsich pctl_timing->tal = 0;
495403e9cbcSPhilipp Tomsich pctl_timing->tras = ps_to_tCK(35000, freq);
496403e9cbcSPhilipp Tomsich pctl_timing->trc = ps_to_tCK(48750, freq);
497403e9cbcSPhilipp Tomsich pctl_timing->trcd = ps_to_tCK(13750, freq);
498403e9cbcSPhilipp Tomsich pctl_timing->trrd = max(4u, ps_to_tCK(7500, freq));
499403e9cbcSPhilipp Tomsich pctl_timing->trtp = max(4u, ps_to_tCK(7500, freq));
500403e9cbcSPhilipp Tomsich pctl_timing->twr = ps_to_tCK(15000, freq);
501403e9cbcSPhilipp Tomsich /* The DDR3 mode-register does only support even values for tWR > 8. */
502403e9cbcSPhilipp Tomsich if (pctl_timing->twr > 8)
503403e9cbcSPhilipp Tomsich pctl_timing->twr = (pctl_timing->twr + 1) & ~1;
504403e9cbcSPhilipp Tomsich pctl_timing->twtr = max(4u, ps_to_tCK(7500, freq));
505403e9cbcSPhilipp Tomsich pctl_timing->texsr = 512; /* tEXSR(max) is tDLLLK */
506403e9cbcSPhilipp Tomsich pctl_timing->txp = max(3u, ps_to_tCK(6000, freq));
507403e9cbcSPhilipp Tomsich pctl_timing->txpdll = max(10u, ps_to_tCK(24000, freq));
508403e9cbcSPhilipp Tomsich pctl_timing->tzqcs = max(64u, ps_to_tCK(80000, freq));
509403e9cbcSPhilipp Tomsich pctl_timing->tzqcsi = 10000; /* as used by Rockchip */
510403e9cbcSPhilipp Tomsich pctl_timing->tdqs = 1; /* fixed for DDR3 */
511403e9cbcSPhilipp Tomsich pctl_timing->tcksre = max(5u, ps_to_tCK(10000, freq));
512403e9cbcSPhilipp Tomsich pctl_timing->tcksrx = max(5u, ps_to_tCK(10000, freq));
513403e9cbcSPhilipp Tomsich pctl_timing->tcke = max(3u, ps_to_tCK(5000, freq));
514403e9cbcSPhilipp Tomsich pctl_timing->tmod = max(12u, ps_to_tCK(15000, freq));
515403e9cbcSPhilipp Tomsich pctl_timing->trstl = ns_to_tCK(100, freq);
516403e9cbcSPhilipp Tomsich pctl_timing->tzqcl = max(256u, ps_to_tCK(320000, freq)); /* tZQoper */
517403e9cbcSPhilipp Tomsich pctl_timing->tmrr = 0;
518403e9cbcSPhilipp Tomsich pctl_timing->tckesr = pctl_timing->tcke + 1; /* JESD-79: tCKE + 1tCK */
519403e9cbcSPhilipp Tomsich pctl_timing->tdpd = 0; /* RK3368 TRM: "allowed values for DDR3: 0" */
520403e9cbcSPhilipp Tomsich
521403e9cbcSPhilipp Tomsich
522403e9cbcSPhilipp Tomsich /*
523403e9cbcSPhilipp Tomsich * The controller can represent tFAW as 4x, 5x or 6x tRRD only.
524403e9cbcSPhilipp Tomsich * We want to use the smallest multiplier that satisfies the tFAW
525403e9cbcSPhilipp Tomsich * requirements of the given speed-bin. If necessary, we stretch out
526403e9cbcSPhilipp Tomsich * tRRD to allow us to operate on a 6x multiplier for tFAW.
527403e9cbcSPhilipp Tomsich */
528403e9cbcSPhilipp Tomsich tfaw_as_ps = 40000; /* 40ns: tFAW for DDR3-1600K, 2KB page-size */
529403e9cbcSPhilipp Tomsich if (tCK_to_ps(pctl_timing->trrd * 6, freq) < tfaw_as_ps) {
530403e9cbcSPhilipp Tomsich /* If tFAW is > 6 x tRRD, we need to stretch tRRD */
531403e9cbcSPhilipp Tomsich pctl_timing->trrd = ps_to_tCK(DIV_ROUND_UP(40000, 6), freq);
532403e9cbcSPhilipp Tomsich params->tfaw_mult = TFAW_TRRD_MULT6;
533403e9cbcSPhilipp Tomsich } else if (tCK_to_ps(pctl_timing->trrd * 5, freq) < tfaw_as_ps) {
534403e9cbcSPhilipp Tomsich params->tfaw_mult = TFAW_TRRD_MULT6;
535403e9cbcSPhilipp Tomsich } else if (tCK_to_ps(pctl_timing->trrd * 4, freq) < tfaw_as_ps) {
536403e9cbcSPhilipp Tomsich params->tfaw_mult = TFAW_TRRD_MULT5;
537403e9cbcSPhilipp Tomsich } else {
538403e9cbcSPhilipp Tomsich params->tfaw_mult = TFAW_TRRD_MULT4;
539403e9cbcSPhilipp Tomsich }
540403e9cbcSPhilipp Tomsich
541403e9cbcSPhilipp Tomsich return 0;
542403e9cbcSPhilipp Tomsich }
543403e9cbcSPhilipp Tomsich
pctl_cfg(struct rk3368_ddr_pctl * pctl,struct rk3368_sdram_params * params,struct rk3368_grf * grf)544403e9cbcSPhilipp Tomsich static void pctl_cfg(struct rk3368_ddr_pctl *pctl,
545403e9cbcSPhilipp Tomsich struct rk3368_sdram_params *params,
546403e9cbcSPhilipp Tomsich struct rk3368_grf *grf)
547403e9cbcSPhilipp Tomsich {
548403e9cbcSPhilipp Tomsich /* Configure PCTL timing registers */
549403e9cbcSPhilipp Tomsich params->pctl_timing.trefi |= BIT(31); /* see PCTL_TREFI */
550403e9cbcSPhilipp Tomsich copy_to_reg(&pctl->togcnt1u, ¶ms->pctl_timing.togcnt1u,
551403e9cbcSPhilipp Tomsich sizeof(params->pctl_timing));
552403e9cbcSPhilipp Tomsich writel(params->trefi_mem_ddr3, &pctl->trefi_mem_ddr3);
553403e9cbcSPhilipp Tomsich
554403e9cbcSPhilipp Tomsich /* Set up ODT write selector and ODT write length */
555403e9cbcSPhilipp Tomsich writel((RANK0_ODT_WRITE_SEL | RANK1_ODT_WRITE_SEL), &pctl->dfiodtcfg);
556403e9cbcSPhilipp Tomsich writel(7 << ODT_LEN_BL8_W_SHIFT, &pctl->dfiodtcfg1);
557403e9cbcSPhilipp Tomsich
558403e9cbcSPhilipp Tomsich /* Set up the CL/CWL-dependent timings of DFI */
559403e9cbcSPhilipp Tomsich writel((params->pctl_timing.tcl - 1) / 2 - 1, &pctl->dfitrddataen);
560403e9cbcSPhilipp Tomsich writel((params->pctl_timing.tcwl - 1) / 2 - 1, &pctl->dfitphywrlat);
561403e9cbcSPhilipp Tomsich
562403e9cbcSPhilipp Tomsich /* DDR3 */
563403e9cbcSPhilipp Tomsich writel(params->tfaw_mult | DDR3_EN | DDR2_DDR3_BL_8, &pctl->mcfg);
564403e9cbcSPhilipp Tomsich writel(0x001c0004, &grf->ddrc0_con0);
565403e9cbcSPhilipp Tomsich
566403e9cbcSPhilipp Tomsich setbits_le32(&pctl->scfg, HW_LOW_POWER_EN);
567403e9cbcSPhilipp Tomsich }
568403e9cbcSPhilipp Tomsich
ddrphy_data_training(struct rk3368_ddr_pctl * pctl,struct rk3368_ddrphy * ddrphy)569403e9cbcSPhilipp Tomsich static int ddrphy_data_training(struct rk3368_ddr_pctl *pctl,
570403e9cbcSPhilipp Tomsich struct rk3368_ddrphy *ddrphy)
571403e9cbcSPhilipp Tomsich {
572403e9cbcSPhilipp Tomsich const u32 trefi = readl(&pctl->trefi);
573403e9cbcSPhilipp Tomsich const ulong timeout_ms = 500;
574403e9cbcSPhilipp Tomsich ulong tmp;
575403e9cbcSPhilipp Tomsich
576403e9cbcSPhilipp Tomsich /* disable auto-refresh */
577403e9cbcSPhilipp Tomsich writel(0 | BIT(31), &pctl->trefi);
578403e9cbcSPhilipp Tomsich
579403e9cbcSPhilipp Tomsich clrsetbits_le32(&ddrphy->reg[2], 0x33, 0x20);
580403e9cbcSPhilipp Tomsich clrsetbits_le32(&ddrphy->reg[2], 0x33, 0x21);
581403e9cbcSPhilipp Tomsich
582403e9cbcSPhilipp Tomsich tmp = get_timer(0);
583403e9cbcSPhilipp Tomsich do {
584403e9cbcSPhilipp Tomsich if (get_timer(tmp) > timeout_ms) {
5859b643e31SMasahiro Yamada pr_err("%s: did not complete within %ld ms\n",
586403e9cbcSPhilipp Tomsich __func__, timeout_ms);
587403e9cbcSPhilipp Tomsich return -ETIME;
588403e9cbcSPhilipp Tomsich }
589403e9cbcSPhilipp Tomsich } while ((readl(&ddrphy->reg[0xff]) & 0xf) != 0xf);
590403e9cbcSPhilipp Tomsich
591403e9cbcSPhilipp Tomsich send_command(pctl, MCMD_RANK0 | MCMD_RANK1, PREA_CMD);
592403e9cbcSPhilipp Tomsich clrsetbits_le32(&ddrphy->reg[2], 0x33, 0x20);
593403e9cbcSPhilipp Tomsich /* resume auto-refresh */
594403e9cbcSPhilipp Tomsich writel(trefi | BIT(31), &pctl->trefi);
595403e9cbcSPhilipp Tomsich
596403e9cbcSPhilipp Tomsich return 0;
597403e9cbcSPhilipp Tomsich }
598403e9cbcSPhilipp Tomsich
sdram_col_row_detect(struct udevice * dev)599403e9cbcSPhilipp Tomsich static int sdram_col_row_detect(struct udevice *dev)
600403e9cbcSPhilipp Tomsich {
601403e9cbcSPhilipp Tomsich struct dram_info *priv = dev_get_priv(dev);
602403e9cbcSPhilipp Tomsich struct rk3368_sdram_params *params = dev_get_platdata(dev);
603403e9cbcSPhilipp Tomsich struct rk3368_ddr_pctl *pctl = priv->pctl;
604403e9cbcSPhilipp Tomsich struct rk3368_msch *msch = priv->msch;
605403e9cbcSPhilipp Tomsich const u32 test_pattern = 0x5aa5f00f;
606403e9cbcSPhilipp Tomsich int row, col;
607403e9cbcSPhilipp Tomsich uintptr_t addr;
608403e9cbcSPhilipp Tomsich
609403e9cbcSPhilipp Tomsich move_to_config_state(pctl);
610403e9cbcSPhilipp Tomsich writel(6, &msch->ddrconf);
611403e9cbcSPhilipp Tomsich move_to_access_state(pctl);
612403e9cbcSPhilipp Tomsich
613403e9cbcSPhilipp Tomsich /* Detect col */
614403e9cbcSPhilipp Tomsich for (col = 11; col >= 9; col--) {
615403e9cbcSPhilipp Tomsich writel(0, CONFIG_SYS_SDRAM_BASE);
616403e9cbcSPhilipp Tomsich addr = CONFIG_SYS_SDRAM_BASE +
617403e9cbcSPhilipp Tomsich (1 << (col + params->chan.bw - 1));
618403e9cbcSPhilipp Tomsich writel(test_pattern, addr);
619403e9cbcSPhilipp Tomsich if ((readl(addr) == test_pattern) &&
620403e9cbcSPhilipp Tomsich (readl(CONFIG_SYS_SDRAM_BASE) == 0))
621403e9cbcSPhilipp Tomsich break;
622403e9cbcSPhilipp Tomsich }
623403e9cbcSPhilipp Tomsich
624403e9cbcSPhilipp Tomsich if (col == 8) {
6259b643e31SMasahiro Yamada pr_err("%s: col detect error\n", __func__);
626403e9cbcSPhilipp Tomsich return -EINVAL;
627403e9cbcSPhilipp Tomsich }
628403e9cbcSPhilipp Tomsich
629403e9cbcSPhilipp Tomsich move_to_config_state(pctl);
630403e9cbcSPhilipp Tomsich writel(15, &msch->ddrconf);
631403e9cbcSPhilipp Tomsich move_to_access_state(pctl);
632403e9cbcSPhilipp Tomsich
633403e9cbcSPhilipp Tomsich /* Detect row*/
634403e9cbcSPhilipp Tomsich for (row = 16; row >= 12; row--) {
635403e9cbcSPhilipp Tomsich writel(0, CONFIG_SYS_SDRAM_BASE);
636403e9cbcSPhilipp Tomsich addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
637403e9cbcSPhilipp Tomsich writel(test_pattern, addr);
638403e9cbcSPhilipp Tomsich if ((readl(addr) == test_pattern) &&
639403e9cbcSPhilipp Tomsich (readl(CONFIG_SYS_SDRAM_BASE) == 0))
640403e9cbcSPhilipp Tomsich break;
641403e9cbcSPhilipp Tomsich }
642403e9cbcSPhilipp Tomsich
643403e9cbcSPhilipp Tomsich if (row == 11) {
6449b643e31SMasahiro Yamada pr_err("%s: row detect error\n", __func__);
645403e9cbcSPhilipp Tomsich return -EINVAL;
646403e9cbcSPhilipp Tomsich }
647403e9cbcSPhilipp Tomsich
648403e9cbcSPhilipp Tomsich /* Record results */
649403e9cbcSPhilipp Tomsich debug("%s: col %d, row %d\n", __func__, col, row);
650403e9cbcSPhilipp Tomsich params->chan.col = col;
651403e9cbcSPhilipp Tomsich params->chan.cs0_row = row;
652403e9cbcSPhilipp Tomsich params->chan.cs1_row = row;
653403e9cbcSPhilipp Tomsich params->chan.row_3_4 = 0;
654403e9cbcSPhilipp Tomsich
655403e9cbcSPhilipp Tomsich return 0;
656403e9cbcSPhilipp Tomsich }
657403e9cbcSPhilipp Tomsich
msch_niu_config(struct rk3368_msch * msch,struct rk3368_sdram_params * params)658403e9cbcSPhilipp Tomsich static int msch_niu_config(struct rk3368_msch *msch,
659403e9cbcSPhilipp Tomsich struct rk3368_sdram_params *params)
660403e9cbcSPhilipp Tomsich {
661403e9cbcSPhilipp Tomsich int i;
662403e9cbcSPhilipp Tomsich const u8 cols = params->chan.col - ((params->chan.bw == 2) ? 0 : 1);
663403e9cbcSPhilipp Tomsich const u8 rows = params->chan.cs0_row;
664403e9cbcSPhilipp Tomsich
665403e9cbcSPhilipp Tomsich /*
666403e9cbcSPhilipp Tomsich * The DDR address-translation table always assumes a 32bit
667403e9cbcSPhilipp Tomsich * bus and the comparison below takes care of adjusting for
668403e9cbcSPhilipp Tomsich * a 16bit bus (i.e. one column-address is consumed).
669403e9cbcSPhilipp Tomsich */
670403e9cbcSPhilipp Tomsich const struct {
671403e9cbcSPhilipp Tomsich u8 rows;
672403e9cbcSPhilipp Tomsich u8 columns;
673403e9cbcSPhilipp Tomsich u8 type;
674403e9cbcSPhilipp Tomsich } ddrconf_table[] = {
675403e9cbcSPhilipp Tomsich /*
676403e9cbcSPhilipp Tomsich * C-B-R-D patterns are first. For these we require an
677403e9cbcSPhilipp Tomsich * exact match for the columns and rows (as there's
678403e9cbcSPhilipp Tomsich * one entry per possible configuration).
679403e9cbcSPhilipp Tomsich */
680403e9cbcSPhilipp Tomsich [0] = { .rows = 13, .columns = 10, .type = DMC_MSCH_CBRD },
681403e9cbcSPhilipp Tomsich [1] = { .rows = 14, .columns = 10, .type = DMC_MSCH_CBRD },
682403e9cbcSPhilipp Tomsich [2] = { .rows = 15, .columns = 10, .type = DMC_MSCH_CBRD },
683403e9cbcSPhilipp Tomsich [3] = { .rows = 16, .columns = 10, .type = DMC_MSCH_CBRD },
684403e9cbcSPhilipp Tomsich [4] = { .rows = 14, .columns = 11, .type = DMC_MSCH_CBRD },
685403e9cbcSPhilipp Tomsich [5] = { .rows = 15, .columns = 11, .type = DMC_MSCH_CBRD },
686403e9cbcSPhilipp Tomsich [6] = { .rows = 16, .columns = 11, .type = DMC_MSCH_CBRD },
687403e9cbcSPhilipp Tomsich [7] = { .rows = 13, .columns = 9, .type = DMC_MSCH_CBRD },
688403e9cbcSPhilipp Tomsich [8] = { .rows = 14, .columns = 9, .type = DMC_MSCH_CBRD },
689403e9cbcSPhilipp Tomsich [9] = { .rows = 15, .columns = 9, .type = DMC_MSCH_CBRD },
690403e9cbcSPhilipp Tomsich [10] = { .rows = 16, .columns = 9, .type = DMC_MSCH_CBRD },
691403e9cbcSPhilipp Tomsich /*
692403e9cbcSPhilipp Tomsich * 11 through 13 are C-R-B-D patterns. These are
693403e9cbcSPhilipp Tomsich * matched for an exact number of columns and to
694403e9cbcSPhilipp Tomsich * ensure that the hardware uses at least as many rows
695403e9cbcSPhilipp Tomsich * as the pattern requires (i.e. we make sure that
696403e9cbcSPhilipp Tomsich * there's no gaps up until we hit the device/chip-select;
697403e9cbcSPhilipp Tomsich * however, these patterns can accept up to 16 rows,
698403e9cbcSPhilipp Tomsich * as the row-address continues right after the CS
699403e9cbcSPhilipp Tomsich * switching)
700403e9cbcSPhilipp Tomsich */
701403e9cbcSPhilipp Tomsich [11] = { .rows = 15, .columns = 10, .type = DMC_MSCH_CRBD },
702403e9cbcSPhilipp Tomsich [12] = { .rows = 14, .columns = 11, .type = DMC_MSCH_CRBD },
703403e9cbcSPhilipp Tomsich [13] = { .rows = 13, .columns = 10, .type = DMC_MSCH_CRBD },
704403e9cbcSPhilipp Tomsich /*
705403e9cbcSPhilipp Tomsich * 14 and 15 are catch-all variants using a C-B-D-R
706403e9cbcSPhilipp Tomsich * scheme (i.e. alternating the chip-select every time
707403e9cbcSPhilipp Tomsich * C-B overflows) and stuffing the remaining C-bits
708403e9cbcSPhilipp Tomsich * into the top. Matching needs to make sure that the
709403e9cbcSPhilipp Tomsich * number of columns is either an exact match (i.e. we
710403e9cbcSPhilipp Tomsich * can use less the the maximum number of rows) -or-
711403e9cbcSPhilipp Tomsich * that the columns exceed what is given in this table
712403e9cbcSPhilipp Tomsich * and the rows are an exact match (in which case the
713403e9cbcSPhilipp Tomsich * remaining C-bits will be stuffed onto the top after
714403e9cbcSPhilipp Tomsich * the device/chip-select switches).
715403e9cbcSPhilipp Tomsich */
716403e9cbcSPhilipp Tomsich [14] = { .rows = 16, .columns = 10, .type = DMC_MSCH_CBDR },
717403e9cbcSPhilipp Tomsich [15] = { .rows = 16, .columns = 9, .type = DMC_MSCH_CBDR },
718403e9cbcSPhilipp Tomsich };
719403e9cbcSPhilipp Tomsich
720403e9cbcSPhilipp Tomsich /*
721403e9cbcSPhilipp Tomsich * For C-B-R-D, we need an exact match (i.e. both for the number of
722403e9cbcSPhilipp Tomsich * columns and rows), while for C-B-D-R, only the the number of
723403e9cbcSPhilipp Tomsich * columns needs to match.
724403e9cbcSPhilipp Tomsich */
725403e9cbcSPhilipp Tomsich for (i = 0; i < ARRAY_SIZE(ddrconf_table); i++) {
726403e9cbcSPhilipp Tomsich bool match = false;
727403e9cbcSPhilipp Tomsich
728403e9cbcSPhilipp Tomsich /* If this entry if for a different matcher, then skip it */
729403e9cbcSPhilipp Tomsich if (ddrconf_table[i].type != params->memory_schedule)
730403e9cbcSPhilipp Tomsich continue;
731403e9cbcSPhilipp Tomsich
732403e9cbcSPhilipp Tomsich /*
733403e9cbcSPhilipp Tomsich * Match according to the rules (exact/inexact/at-least)
734403e9cbcSPhilipp Tomsich * documented in the ddrconf_table above.
735403e9cbcSPhilipp Tomsich */
736403e9cbcSPhilipp Tomsich switch (params->memory_schedule) {
737403e9cbcSPhilipp Tomsich case DMC_MSCH_CBRD:
738403e9cbcSPhilipp Tomsich match = (ddrconf_table[i].columns == cols) &&
739403e9cbcSPhilipp Tomsich (ddrconf_table[i].rows == rows);
740403e9cbcSPhilipp Tomsich break;
741403e9cbcSPhilipp Tomsich
742403e9cbcSPhilipp Tomsich case DMC_MSCH_CRBD:
743403e9cbcSPhilipp Tomsich match = (ddrconf_table[i].columns == cols) &&
744403e9cbcSPhilipp Tomsich (ddrconf_table[i].rows <= rows);
745403e9cbcSPhilipp Tomsich break;
746403e9cbcSPhilipp Tomsich
747403e9cbcSPhilipp Tomsich case DMC_MSCH_CBDR:
748403e9cbcSPhilipp Tomsich match = (ddrconf_table[i].columns == cols) ||
749403e9cbcSPhilipp Tomsich ((ddrconf_table[i].columns <= cols) &&
750403e9cbcSPhilipp Tomsich (ddrconf_table[i].rows == rows));
751403e9cbcSPhilipp Tomsich break;
752403e9cbcSPhilipp Tomsich
753403e9cbcSPhilipp Tomsich default:
754403e9cbcSPhilipp Tomsich break;
755403e9cbcSPhilipp Tomsich }
756403e9cbcSPhilipp Tomsich
757403e9cbcSPhilipp Tomsich if (match) {
758403e9cbcSPhilipp Tomsich debug("%s: setting ddrconf 0x%x\n", __func__, i);
759403e9cbcSPhilipp Tomsich writel(i, &msch->ddrconf);
760403e9cbcSPhilipp Tomsich return 0;
761403e9cbcSPhilipp Tomsich }
762403e9cbcSPhilipp Tomsich }
763403e9cbcSPhilipp Tomsich
7649b643e31SMasahiro Yamada pr_err("%s: ddrconf (NIU config) not found\n", __func__);
765403e9cbcSPhilipp Tomsich return -EINVAL;
766403e9cbcSPhilipp Tomsich }
767403e9cbcSPhilipp Tomsich
dram_all_config(struct udevice * dev)768403e9cbcSPhilipp Tomsich static void dram_all_config(struct udevice *dev)
769403e9cbcSPhilipp Tomsich {
770403e9cbcSPhilipp Tomsich struct dram_info *priv = dev_get_priv(dev);
771403e9cbcSPhilipp Tomsich struct rk3368_pmu_grf *pmugrf = priv->pmugrf;
772403e9cbcSPhilipp Tomsich struct rk3368_sdram_params *params = dev_get_platdata(dev);
773403e9cbcSPhilipp Tomsich const struct rk3288_sdram_channel *info = ¶ms->chan;
774403e9cbcSPhilipp Tomsich u32 sys_reg = 0;
775403e9cbcSPhilipp Tomsich const int chan = 0;
776403e9cbcSPhilipp Tomsich
777403e9cbcSPhilipp Tomsich sys_reg |= DDR3 << SYS_REG_DDRTYPE_SHIFT;
778403e9cbcSPhilipp Tomsich sys_reg |= 0 << SYS_REG_NUM_CH_SHIFT;
779403e9cbcSPhilipp Tomsich
780403e9cbcSPhilipp Tomsich sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan);
781403e9cbcSPhilipp Tomsich sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(chan);
782403e9cbcSPhilipp Tomsich sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan);
783403e9cbcSPhilipp Tomsich sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan);
784403e9cbcSPhilipp Tomsich sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(chan);
785403e9cbcSPhilipp Tomsich sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan);
786403e9cbcSPhilipp Tomsich sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan);
787403e9cbcSPhilipp Tomsich sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(chan);
788403e9cbcSPhilipp Tomsich sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(chan);
789403e9cbcSPhilipp Tomsich
790403e9cbcSPhilipp Tomsich writel(sys_reg, &pmugrf->os_reg[2]);
791403e9cbcSPhilipp Tomsich }
792403e9cbcSPhilipp Tomsich
setup_sdram(struct udevice * dev)793403e9cbcSPhilipp Tomsich static int setup_sdram(struct udevice *dev)
794403e9cbcSPhilipp Tomsich {
795403e9cbcSPhilipp Tomsich struct dram_info *priv = dev_get_priv(dev);
796403e9cbcSPhilipp Tomsich struct rk3368_sdram_params *params = dev_get_platdata(dev);
797403e9cbcSPhilipp Tomsich
798403e9cbcSPhilipp Tomsich struct rk3368_ddr_pctl *pctl = priv->pctl;
799403e9cbcSPhilipp Tomsich struct rk3368_ddrphy *ddrphy = priv->phy;
800403e9cbcSPhilipp Tomsich struct rk3368_cru *cru = priv->cru;
801403e9cbcSPhilipp Tomsich struct rk3368_grf *grf = priv->grf;
802403e9cbcSPhilipp Tomsich struct rk3368_msch *msch = priv->msch;
803403e9cbcSPhilipp Tomsich
804403e9cbcSPhilipp Tomsich int ret;
805403e9cbcSPhilipp Tomsich
806403e9cbcSPhilipp Tomsich /* The input clock (i.e. DPLL) needs to be 2x the DRAM frequency */
807403e9cbcSPhilipp Tomsich ret = clk_set_rate(&priv->ddr_clk, 2 * params->ddr_freq);
808403e9cbcSPhilipp Tomsich if (ret < 0) {
809403e9cbcSPhilipp Tomsich debug("%s: could not set DDR clock: %d\n", __func__, ret);
810403e9cbcSPhilipp Tomsich return ret;
811403e9cbcSPhilipp Tomsich }
812403e9cbcSPhilipp Tomsich
813403e9cbcSPhilipp Tomsich /* Update the read-latency for the RK3368 */
814403e9cbcSPhilipp Tomsich writel(0x32, &msch->readlatency);
815403e9cbcSPhilipp Tomsich
816403e9cbcSPhilipp Tomsich /* Initialise the DDR PCTL and DDR PHY */
817403e9cbcSPhilipp Tomsich ddrctl_reset(cru);
818403e9cbcSPhilipp Tomsich ddrphy_reset(ddrphy);
819403e9cbcSPhilipp Tomsich ddrphy_config_delays(ddrphy, params->ddr_freq);
820403e9cbcSPhilipp Tomsich dfi_cfg(pctl);
821403e9cbcSPhilipp Tomsich /* Configure relative system information of grf_ddrc0_con0 register */
822403e9cbcSPhilipp Tomsich ddr_set_ddr3_mode(grf, true);
823403e9cbcSPhilipp Tomsich ddr_set_noc_spr_err_stall(grf, true);
824403e9cbcSPhilipp Tomsich /* Calculate timings */
825403e9cbcSPhilipp Tomsich pctl_calc_timings(params, params->ddr_freq);
826403e9cbcSPhilipp Tomsich /* Initialise the device timings in protocol controller */
827403e9cbcSPhilipp Tomsich pctl_cfg(pctl, params, grf);
828403e9cbcSPhilipp Tomsich /* Configure AL, CL ... information of PHY registers */
829403e9cbcSPhilipp Tomsich ddrphy_config(ddrphy,
830403e9cbcSPhilipp Tomsich params->pctl_timing.tcl,
831403e9cbcSPhilipp Tomsich params->pctl_timing.tal,
832403e9cbcSPhilipp Tomsich params->pctl_timing.tcwl);
833403e9cbcSPhilipp Tomsich
834403e9cbcSPhilipp Tomsich /* Initialize DRAM and configure with mode-register values */
835403e9cbcSPhilipp Tomsich ret = memory_init(pctl, params);
836403e9cbcSPhilipp Tomsich if (ret)
837403e9cbcSPhilipp Tomsich goto error;
838403e9cbcSPhilipp Tomsich
839403e9cbcSPhilipp Tomsich move_to_config_state(pctl);
840403e9cbcSPhilipp Tomsich /* Perform data-training */
841403e9cbcSPhilipp Tomsich ddrphy_data_training(pctl, ddrphy);
842403e9cbcSPhilipp Tomsich move_to_access_state(pctl);
843403e9cbcSPhilipp Tomsich
844403e9cbcSPhilipp Tomsich /* TODO(prt): could detect rank in training... */
845403e9cbcSPhilipp Tomsich params->chan.rank = 2;
846403e9cbcSPhilipp Tomsich /* TODO(prt): bus width is not auto-detected (yet)... */
847403e9cbcSPhilipp Tomsich params->chan.bw = 2; /* 32bit wide bus */
848403e9cbcSPhilipp Tomsich params->chan.dbw = params->chan.dbw; /* 32bit wide bus */
849403e9cbcSPhilipp Tomsich
850403e9cbcSPhilipp Tomsich /* DDR3 is always 8 bank */
851403e9cbcSPhilipp Tomsich params->chan.bk = 3;
852403e9cbcSPhilipp Tomsich /* Detect col and row number */
853403e9cbcSPhilipp Tomsich ret = sdram_col_row_detect(dev);
854403e9cbcSPhilipp Tomsich if (ret)
855403e9cbcSPhilipp Tomsich goto error;
856403e9cbcSPhilipp Tomsich
857403e9cbcSPhilipp Tomsich /* Configure NIU DDR configuration */
858403e9cbcSPhilipp Tomsich ret = msch_niu_config(msch, params);
859403e9cbcSPhilipp Tomsich if (ret)
860403e9cbcSPhilipp Tomsich goto error;
861403e9cbcSPhilipp Tomsich
862403e9cbcSPhilipp Tomsich /* set up OS_REG to communicate w/ next stage and OS */
863403e9cbcSPhilipp Tomsich dram_all_config(dev);
864403e9cbcSPhilipp Tomsich
865403e9cbcSPhilipp Tomsich return 0;
866403e9cbcSPhilipp Tomsich
867403e9cbcSPhilipp Tomsich error:
868403e9cbcSPhilipp Tomsich printf("DRAM init failed!\n");
869403e9cbcSPhilipp Tomsich hang();
870403e9cbcSPhilipp Tomsich }
871403e9cbcSPhilipp Tomsich #endif
872403e9cbcSPhilipp Tomsich
rk3368_dmc_ofdata_to_platdata(struct udevice * dev)873403e9cbcSPhilipp Tomsich static int rk3368_dmc_ofdata_to_platdata(struct udevice *dev)
874403e9cbcSPhilipp Tomsich {
875403e9cbcSPhilipp Tomsich int ret = 0;
876403e9cbcSPhilipp Tomsich
877403e9cbcSPhilipp Tomsich #if !CONFIG_IS_ENABLED(OF_PLATDATA)
878403e9cbcSPhilipp Tomsich struct rk3368_sdram_params *plat = dev_get_platdata(dev);
879403e9cbcSPhilipp Tomsich
880*d3581236SMasahiro Yamada ret = regmap_init_mem(dev_ofnode(dev), &plat->map);
881403e9cbcSPhilipp Tomsich if (ret)
882403e9cbcSPhilipp Tomsich return ret;
883403e9cbcSPhilipp Tomsich #endif
884403e9cbcSPhilipp Tomsich
885403e9cbcSPhilipp Tomsich return ret;
886403e9cbcSPhilipp Tomsich }
887403e9cbcSPhilipp Tomsich
888403e9cbcSPhilipp Tomsich #if CONFIG_IS_ENABLED(OF_PLATDATA)
conv_of_platdata(struct udevice * dev)889403e9cbcSPhilipp Tomsich static int conv_of_platdata(struct udevice *dev)
890403e9cbcSPhilipp Tomsich {
891403e9cbcSPhilipp Tomsich struct rk3368_sdram_params *plat = dev_get_platdata(dev);
892403e9cbcSPhilipp Tomsich struct dtd_rockchip_rk3368_dmc *of_plat = &plat->of_plat;
893403e9cbcSPhilipp Tomsich
894403e9cbcSPhilipp Tomsich plat->ddr_freq = of_plat->rockchip_ddr_frequency;
895403e9cbcSPhilipp Tomsich plat->ddr_speed_bin = of_plat->rockchip_ddr_speed_bin;
896403e9cbcSPhilipp Tomsich plat->memory_schedule = of_plat->rockchip_memory_schedule;
897403e9cbcSPhilipp Tomsich
898403e9cbcSPhilipp Tomsich return 0;
899403e9cbcSPhilipp Tomsich }
900403e9cbcSPhilipp Tomsich #endif
901403e9cbcSPhilipp Tomsich
rk3368_dmc_probe(struct udevice * dev)902403e9cbcSPhilipp Tomsich static int rk3368_dmc_probe(struct udevice *dev)
903403e9cbcSPhilipp Tomsich {
904403e9cbcSPhilipp Tomsich #ifdef CONFIG_TPL_BUILD
905403e9cbcSPhilipp Tomsich struct rk3368_sdram_params *plat = dev_get_platdata(dev);
906403e9cbcSPhilipp Tomsich struct rk3368_ddr_pctl *pctl;
907403e9cbcSPhilipp Tomsich struct rk3368_ddrphy *ddrphy;
908403e9cbcSPhilipp Tomsich struct rk3368_cru *cru;
909403e9cbcSPhilipp Tomsich struct rk3368_grf *grf;
910403e9cbcSPhilipp Tomsich struct rk3368_msch *msch;
911403e9cbcSPhilipp Tomsich int ret;
912403e9cbcSPhilipp Tomsich struct udevice *dev_clk;
913403e9cbcSPhilipp Tomsich #endif
914403e9cbcSPhilipp Tomsich struct dram_info *priv = dev_get_priv(dev);
915403e9cbcSPhilipp Tomsich
916403e9cbcSPhilipp Tomsich #if CONFIG_IS_ENABLED(OF_PLATDATA)
917403e9cbcSPhilipp Tomsich ret = conv_of_platdata(dev);
918403e9cbcSPhilipp Tomsich if (ret)
919403e9cbcSPhilipp Tomsich return ret;
920403e9cbcSPhilipp Tomsich #endif
921403e9cbcSPhilipp Tomsich
922403e9cbcSPhilipp Tomsich priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
923403e9cbcSPhilipp Tomsich debug("%s: pmugrf=%p\n", __func__, priv->pmugrf);
924403e9cbcSPhilipp Tomsich
925403e9cbcSPhilipp Tomsich #ifdef CONFIG_TPL_BUILD
9261d70f0acSPhilipp Tomsich pctl = (struct rk3368_ddr_pctl *)plat->of_plat.reg[0];
9271d70f0acSPhilipp Tomsich ddrphy = (struct rk3368_ddrphy *)plat->of_plat.reg[2];
928403e9cbcSPhilipp Tomsich msch = syscon_get_first_range(ROCKCHIP_SYSCON_MSCH);
929403e9cbcSPhilipp Tomsich grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
930403e9cbcSPhilipp Tomsich
931403e9cbcSPhilipp Tomsich priv->pctl = pctl;
932403e9cbcSPhilipp Tomsich priv->phy = ddrphy;
933403e9cbcSPhilipp Tomsich priv->msch = msch;
934403e9cbcSPhilipp Tomsich priv->grf = grf;
935403e9cbcSPhilipp Tomsich
936403e9cbcSPhilipp Tomsich ret = rockchip_get_clk(&dev_clk);
937403e9cbcSPhilipp Tomsich if (ret)
938403e9cbcSPhilipp Tomsich return ret;
939403e9cbcSPhilipp Tomsich priv->ddr_clk.id = CLK_DDR;
940403e9cbcSPhilipp Tomsich ret = clk_request(dev_clk, &priv->ddr_clk);
941403e9cbcSPhilipp Tomsich if (ret)
942403e9cbcSPhilipp Tomsich return ret;
943403e9cbcSPhilipp Tomsich
944403e9cbcSPhilipp Tomsich cru = rockchip_get_cru();
945403e9cbcSPhilipp Tomsich priv->cru = cru;
946403e9cbcSPhilipp Tomsich if (IS_ERR(priv->cru))
947403e9cbcSPhilipp Tomsich return PTR_ERR(priv->cru);
948403e9cbcSPhilipp Tomsich
949403e9cbcSPhilipp Tomsich ret = setup_sdram(dev);
950403e9cbcSPhilipp Tomsich if (ret)
951403e9cbcSPhilipp Tomsich return ret;
952403e9cbcSPhilipp Tomsich #endif
953403e9cbcSPhilipp Tomsich
954403e9cbcSPhilipp Tomsich priv->info.base = 0;
955403e9cbcSPhilipp Tomsich priv->info.size =
956403e9cbcSPhilipp Tomsich rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg[2]);
957403e9cbcSPhilipp Tomsich
958403e9cbcSPhilipp Tomsich /*
959403e9cbcSPhilipp Tomsich * we use the 0x00000000~0xfdffffff space since 0xff000000~0xffffffff
960403e9cbcSPhilipp Tomsich * is SoC register space (i.e. reserved), and 0xfe000000~0xfeffffff is
961403e9cbcSPhilipp Tomsich * inaccessible for some IP controller.
962403e9cbcSPhilipp Tomsich */
963403e9cbcSPhilipp Tomsich priv->info.size = min(priv->info.size, (size_t)0xfe000000);
964403e9cbcSPhilipp Tomsich
965403e9cbcSPhilipp Tomsich return 0;
966403e9cbcSPhilipp Tomsich }
967403e9cbcSPhilipp Tomsich
rk3368_dmc_get_info(struct udevice * dev,struct ram_info * info)968403e9cbcSPhilipp Tomsich static int rk3368_dmc_get_info(struct udevice *dev, struct ram_info *info)
969403e9cbcSPhilipp Tomsich {
970403e9cbcSPhilipp Tomsich struct dram_info *priv = dev_get_priv(dev);
971403e9cbcSPhilipp Tomsich
972403e9cbcSPhilipp Tomsich *info = priv->info;
973403e9cbcSPhilipp Tomsich return 0;
974403e9cbcSPhilipp Tomsich }
975403e9cbcSPhilipp Tomsich
976403e9cbcSPhilipp Tomsich static struct ram_ops rk3368_dmc_ops = {
977403e9cbcSPhilipp Tomsich .get_info = rk3368_dmc_get_info,
978403e9cbcSPhilipp Tomsich };
979403e9cbcSPhilipp Tomsich
980403e9cbcSPhilipp Tomsich
981403e9cbcSPhilipp Tomsich static const struct udevice_id rk3368_dmc_ids[] = {
982403e9cbcSPhilipp Tomsich { .compatible = "rockchip,rk3368-dmc" },
983403e9cbcSPhilipp Tomsich { }
984403e9cbcSPhilipp Tomsich };
985403e9cbcSPhilipp Tomsich
986403e9cbcSPhilipp Tomsich U_BOOT_DRIVER(dmc_rk3368) = {
987403e9cbcSPhilipp Tomsich .name = "rockchip_rk3368_dmc",
988403e9cbcSPhilipp Tomsich .id = UCLASS_RAM,
989403e9cbcSPhilipp Tomsich .of_match = rk3368_dmc_ids,
990403e9cbcSPhilipp Tomsich .ops = &rk3368_dmc_ops,
991403e9cbcSPhilipp Tomsich .probe = rk3368_dmc_probe,
992403e9cbcSPhilipp Tomsich .priv_auto_alloc_size = sizeof(struct dram_info),
993403e9cbcSPhilipp Tomsich .ofdata_to_platdata = rk3368_dmc_ofdata_to_platdata,
994403e9cbcSPhilipp Tomsich .probe = rk3368_dmc_probe,
995403e9cbcSPhilipp Tomsich .priv_auto_alloc_size = sizeof(struct dram_info),
996403e9cbcSPhilipp Tomsich .platdata_auto_alloc_size = sizeof(struct rk3368_sdram_params),
997403e9cbcSPhilipp Tomsich };
998