Lines Matching +full:pctl +full:- +full:regmap
1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
8 #include <dt-structs.h>
11 #include <regmap.h>
27 struct rk322x_ddr_pctl *pctl; member
49 struct regmap *map;
93 rk_clrsetreg(&cru->cru_softrst_con[5], 1 << DDRCTRL_PSRST_SHIFT | in phy_pctrl_reset()
101 rk_clrreg(&cru->cru_softrst_con[5], 1 << DDRPHY_PSRST_SHIFT | in phy_pctrl_reset()
105 rk_clrreg(&cru->cru_softrst_con[5], 1 << DDRCTRL_PSRST_SHIFT | in phy_pctrl_reset()
109 clrbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
112 setbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
115 setbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
125 setbits_le32(&ddr_phy->ddrphy_reg[0x13], 0x10); in phy_dll_bypass_set()
126 setbits_le32(&ddr_phy->ddrphy_reg[0x26], 0x10); in phy_dll_bypass_set()
127 setbits_le32(&ddr_phy->ddrphy_reg[0x36], 0x10); in phy_dll_bypass_set()
128 setbits_le32(&ddr_phy->ddrphy_reg[0x46], 0x10); in phy_dll_bypass_set()
129 setbits_le32(&ddr_phy->ddrphy_reg[0x56], 0x10); in phy_dll_bypass_set()
131 clrbits_le32(&ddr_phy->ddrphy_reg[0x14], 0x8); in phy_dll_bypass_set()
132 clrbits_le32(&ddr_phy->ddrphy_reg[0x27], 0x8); in phy_dll_bypass_set()
133 clrbits_le32(&ddr_phy->ddrphy_reg[0x37], 0x8); in phy_dll_bypass_set()
134 clrbits_le32(&ddr_phy->ddrphy_reg[0x47], 0x8); in phy_dll_bypass_set()
135 clrbits_le32(&ddr_phy->ddrphy_reg[0x57], 0x8); in phy_dll_bypass_set()
138 setbits_le32(&ddr_phy->ddrphy_reg[0xa4], 0x1f); in phy_dll_bypass_set()
140 clrbits_le32(&ddr_phy->ddrphy_reg[0xa4], 0x1f); in phy_dll_bypass_set()
147 writel(tmp, &ddr_phy->ddrphy_reg[0x28]); in phy_dll_bypass_set()
148 writel(tmp, &ddr_phy->ddrphy_reg[0x38]); in phy_dll_bypass_set()
149 writel(tmp, &ddr_phy->ddrphy_reg[0x48]); in phy_dll_bypass_set()
150 writel(tmp, &ddr_phy->ddrphy_reg[0x58]); in phy_dll_bypass_set()
153 static void send_command(struct rk322x_ddr_pctl *pctl, in send_command() argument
156 writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd); in send_command()
158 while (readl(&pctl->mcmd) & START_CMD) in send_command()
165 struct rk322x_ddr_pctl *pctl = chan->pctl; in memory_init() local
166 u32 dramtype = sdram_params->base.dramtype; in memory_init()
169 send_command(pctl, 3, DESELECT_CMD, 0); in memory_init()
171 send_command(pctl, 3, PREA_CMD, 0); in memory_init()
172 send_command(pctl, 3, MRS_CMD, in memory_init()
174 (sdram_params->phy_timing.mr[2] & CMD_ADDR_MASK) << in memory_init()
177 send_command(pctl, 3, MRS_CMD, in memory_init()
179 (sdram_params->phy_timing.mr[3] & CMD_ADDR_MASK) << in memory_init()
182 send_command(pctl, 3, MRS_CMD, in memory_init()
184 (sdram_params->phy_timing.mr[1] & CMD_ADDR_MASK) << in memory_init()
187 send_command(pctl, 3, MRS_CMD, in memory_init()
189 ((sdram_params->phy_timing.mr[0] | in memory_init()
193 send_command(pctl, 3, ZQCL_CMD, 0); in memory_init()
195 send_command(pctl, 3, MRS_CMD, in memory_init()
200 send_command(pctl, 3, MRS_CMD, in memory_init()
205 send_command(pctl, 3, MRS_CMD, in memory_init()
210 send_command(pctl, 3, MRS_CMD, in memory_init()
212 (sdram_params->phy_timing.mr[1] & in memory_init()
214 send_command(pctl, 3, MRS_CMD, in memory_init()
216 (sdram_params->phy_timing.mr[2] & in memory_init()
218 send_command(pctl, 3, MRS_CMD, in memory_init()
220 (sdram_params->phy_timing.mr[3] & in memory_init()
223 send_command(pctl, 3, MRS_CMD, (11 & LPDDR23_MA_MASK) << in memory_init()
225 (sdram_params->phy_timing.mr11 & in memory_init()
232 struct rk322x_ddr_phy *ddr_phy = chan->phy; in data_training()
233 struct rk322x_ddr_pctl *pctl = chan->pctl; in data_training() local
235 u32 bw = (readl(&ddr_phy->ddrphy_reg[0]) >> 4) & 0xf; in data_training()
239 value = readl(&pctl->trefi) | (1 << 31); in data_training()
240 writel(1 << 31, &pctl->trefi); in data_training()
242 clrsetbits_le32(&ddr_phy->ddrphy_reg[2], 0x30, in data_training()
244 setbits_le32(&ddr_phy->ddrphy_reg[2], DQS_SQU_CAL_START); in data_training()
247 ret = readl(&ddr_phy->ddrphy_reg[0xff]); in data_training()
249 clrbits_le32(&ddr_phy->ddrphy_reg[2], in data_training()
256 send_command(pctl, 3, PREA_CMD, 0); in data_training()
257 send_command(pctl, 3, REF_CMD, 0); in data_training()
259 writel(value, &pctl->trefi); in data_training()
262 ret = -1; in data_training()
265 ret = (ret == 0) ? 0 : -1; in data_training()
270 static void move_to_config_state(struct rk322x_ddr_pctl *pctl) in move_to_config_state() argument
275 state = readl(&pctl->stat) & PCTL_STAT_MASK; in move_to_config_state()
278 writel(WAKEUP_STATE, &pctl->sctl); in move_to_config_state()
279 while ((readl(&pctl->stat) & PCTL_STAT_MASK) in move_to_config_state()
289 writel(CFG_STATE, &pctl->sctl); in move_to_config_state()
290 while ((readl(&pctl->stat) & PCTL_STAT_MASK) != CONFIG) in move_to_config_state()
301 static void move_to_access_state(struct rk322x_ddr_pctl *pctl) in move_to_access_state() argument
306 state = readl(&pctl->stat) & PCTL_STAT_MASK; in move_to_access_state()
309 writel(WAKEUP_STATE, &pctl->sctl); in move_to_access_state()
310 while ((readl(&pctl->stat) & PCTL_STAT_MASK) != ACCESS) in move_to_access_state()
314 writel(CFG_STATE, &pctl->sctl); in move_to_access_state()
315 while ((readl(&pctl->stat) & PCTL_STAT_MASK) != CONFIG) in move_to_access_state()
319 writel(GO_STATE, &pctl->sctl); in move_to_access_state()
320 while ((readl(&pctl->stat) & PCTL_STAT_MASK) != ACCESS) in move_to_access_state()
331 static void move_to_lowpower_state(struct rk322x_ddr_pctl *pctl) in move_to_lowpower_state() argument
336 state = readl(&pctl->stat) & PCTL_STAT_MASK; in move_to_lowpower_state()
339 writel(CFG_STATE, &pctl->sctl); in move_to_lowpower_state()
340 while ((readl(&pctl->stat) & PCTL_STAT_MASK) != CONFIG) in move_to_lowpower_state()
344 writel(GO_STATE, &pctl->sctl); in move_to_lowpower_state()
345 while ((readl(&pctl->stat) & PCTL_STAT_MASK) != ACCESS) in move_to_lowpower_state()
349 writel(SLEEP_STATE, &pctl->sctl); in move_to_lowpower_state()
350 while ((readl(&pctl->stat) & PCTL_STAT_MASK) != in move_to_lowpower_state()
362 /* pctl should in low power mode when call this function */
365 struct rk322x_ddr_phy *ddr_phy = dram->chan[0].phy; in phy_softreset()
366 struct rk322x_grf *grf = dram->grf; in phy_softreset()
368 writel(GRF_DDRPHY_BUFFEREN_CORE_EN, &grf->soc_con[0]); in phy_softreset()
369 clrbits_le32(&ddr_phy->ddrphy_reg[0], 0x3 << 2); in phy_softreset()
371 setbits_le32(&ddr_phy->ddrphy_reg[0], 1 << 2); in phy_softreset()
373 setbits_le32(&ddr_phy->ddrphy_reg[0], 1 << 3); in phy_softreset()
374 writel(GRF_DDRPHY_BUFFEREN_CORE_DIS, &grf->soc_con[0]); in phy_softreset()
380 struct rk322x_ddr_pctl *pctl = dram->chan[0].pctl; in set_bw() local
381 struct rk322x_ddr_phy *ddr_phy = dram->chan[0].phy; in set_bw()
382 struct rk322x_grf *grf = dram->grf; in set_bw()
385 setbits_le32(&pctl->ppcfg, 1); in set_bw()
386 clrbits_le32(&ddr_phy->ddrphy_reg[0], 0xc << 4); in set_bw()
387 writel(GRF_MSCH_NOC_16BIT_EN, &grf->soc_con[0]); in set_bw()
388 clrbits_le32(&ddr_phy->ddrphy_reg[0x46], 0x8); in set_bw()
389 clrbits_le32(&ddr_phy->ddrphy_reg[0x56], 0x8); in set_bw()
391 clrbits_le32(&pctl->ppcfg, 1); in set_bw()
392 setbits_le32(&ddr_phy->ddrphy_reg[0], 0xf << 4); in set_bw()
394 &grf->soc_con[0]); in set_bw()
395 setbits_le32(&ddr_phy->ddrphy_reg[0x46], 0x8); in set_bw()
396 setbits_le32(&ddr_phy->ddrphy_reg[0x56], 0x8); in set_bw()
400 static void pctl_cfg(struct rk322x_ddr_pctl *pctl, in pctl_cfg() argument
406 u32 dramtype = sdram_params->base.dramtype; in pctl_cfg()
408 if (sdram_params->ch[0].bw == 2) in pctl_cfg()
413 writel(DFI_INIT_START | DFI_DATA_BYTE_DISABLE_EN, &pctl->dfistcfg0); in pctl_cfg()
414 writel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN, &pctl->dfistcfg1); in pctl_cfg()
415 writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2); in pctl_cfg()
416 writel(0x51010, &pctl->dfilpcfg0); in pctl_cfg()
418 writel(1, &pctl->dfitphyupdtype0); in pctl_cfg()
419 writel(0x0d, &pctl->dfitphyrdlat); in pctl_cfg()
420 writel(0, &pctl->dfitphywrdata); in pctl_cfg()
422 writel(0, &pctl->dfiupdcfg); in pctl_cfg()
423 copy_to_reg(&pctl->togcnt1u, &sdram_params->pctl_timing.togcnt1u, in pctl_cfg()
427 &pctl->dfiodtcfg); in pctl_cfg()
428 writel(7 << 16, &pctl->dfiodtcfg1); in pctl_cfg()
429 writel((readl(&pctl->tcl) - 1) / 2 - 1, &pctl->dfitrddataen); in pctl_cfg()
430 writel((readl(&pctl->tcwl) - 1) / 2 - 1, &pctl->dfitphywrlat); in pctl_cfg()
431 writel(500, &pctl->trsth); in pctl_cfg()
433 DDR2_DDR3_BL_8 | (6 - 4) << TFAW_SHIFT | PD_EXIT_SLOW | in pctl_cfg()
435 &pctl->mcfg); in pctl_cfg()
436 writel(bw | GRF_DDR3_EN, &grf->soc_con[0]); in pctl_cfg()
438 if (sdram_params->phy_timing.bl & PHT_BL_8) in pctl_cfg()
443 writel(readl(&pctl->tcl) / 2 - 1, &pctl->dfitrddataen); in pctl_cfg()
444 writel(readl(&pctl->tcwl) / 2 - 1, &pctl->dfitphywrlat); in pctl_cfg()
445 writel(0, &pctl->trsth); in pctl_cfg()
449 (6 - 4) << TFAW_SHIFT | PD_EXIT_FAST | in pctl_cfg()
451 &pctl->mcfg); in pctl_cfg()
452 writel(0, &pctl->dfiodtcfg); in pctl_cfg()
453 writel(0, &pctl->dfiodtcfg1); in pctl_cfg()
457 (6 - 4) << TFAW_SHIFT | PD_EXIT_FAST | in pctl_cfg()
459 &pctl->mcfg); in pctl_cfg()
460 writel((1 << 3) | (1 << 2), &pctl->dfiodtcfg); in pctl_cfg()
461 writel((7 << 16) | 4, &pctl->dfiodtcfg1); in pctl_cfg()
463 writel(bw | GRF_LPDDR2_3_EN, &grf->soc_con[0]); in pctl_cfg()
465 setbits_le32(&pctl->scfg, 1); in pctl_cfg()
471 struct rk322x_ddr_phy *ddr_phy = chan->phy; in phy_cfg()
472 struct rk322x_service_sys *axi_bus = chan->msch; in phy_cfg()
473 struct rk322x_msch_timings *noc_timing = &sdram_params->base.noc_timing; in phy_cfg()
474 struct rk322x_phy_timing *phy_timing = &sdram_params->phy_timing; in phy_cfg()
475 struct rk322x_pctl_timing *pctl_timing = &sdram_params->pctl_timing; in phy_cfg()
478 writel(noc_timing->ddrtiming, &axi_bus->ddrtiming); in phy_cfg()
479 writel(noc_timing->ddrmode, &axi_bus->ddrmode); in phy_cfg()
480 writel(noc_timing->readlatency, &axi_bus->readlatency); in phy_cfg()
481 writel(noc_timing->activate, &axi_bus->activate); in phy_cfg()
482 writel(noc_timing->devtodev, &axi_bus->devtodev); in phy_cfg()
484 switch (sdram_params->base.dramtype) { in phy_cfg()
486 writel(PHY_DDR3 | phy_timing->bl, &ddr_phy->ddrphy_reg[1]); in phy_cfg()
489 writel(PHY_LPDDR2 | phy_timing->bl, &ddr_phy->ddrphy_reg[1]); in phy_cfg()
492 writel(PHY_LPDDR2 | phy_timing->bl, &ddr_phy->ddrphy_reg[1]); in phy_cfg()
496 writel(phy_timing->cl_al, &ddr_phy->ddrphy_reg[0xb]); in phy_cfg()
497 writel(pctl_timing->tcwl, &ddr_phy->ddrphy_reg[0xc]); in phy_cfg()
502 if (sdram_params->base.dramtype == LPDDR2) in phy_cfg()
507 writel(cmd_drv, &ddr_phy->ddrphy_reg[0x11]); in phy_cfg()
508 clrsetbits_le32(&ddr_phy->ddrphy_reg[0x12], (0x1f << 3), cmd_drv << 3); in phy_cfg()
509 writel(clk_drv, &ddr_phy->ddrphy_reg[0x16]); in phy_cfg()
510 writel(clk_drv, &ddr_phy->ddrphy_reg[0x18]); in phy_cfg()
512 writel(dqs_drv, &ddr_phy->ddrphy_reg[0x20]); in phy_cfg()
513 writel(dqs_drv, &ddr_phy->ddrphy_reg[0x2f]); in phy_cfg()
514 writel(dqs_drv, &ddr_phy->ddrphy_reg[0x30]); in phy_cfg()
515 writel(dqs_drv, &ddr_phy->ddrphy_reg[0x3f]); in phy_cfg()
516 writel(dqs_drv, &ddr_phy->ddrphy_reg[0x40]); in phy_cfg()
517 writel(dqs_drv, &ddr_phy->ddrphy_reg[0x4f]); in phy_cfg()
518 writel(dqs_drv, &ddr_phy->ddrphy_reg[0x50]); in phy_cfg()
519 writel(dqs_drv, &ddr_phy->ddrphy_reg[0x5f]); in phy_cfg()
521 writel(dqs_odt, &ddr_phy->ddrphy_reg[0x21]); in phy_cfg()
522 writel(dqs_odt, &ddr_phy->ddrphy_reg[0x2e]); in phy_cfg()
523 writel(dqs_odt, &ddr_phy->ddrphy_reg[0x31]); in phy_cfg()
524 writel(dqs_odt, &ddr_phy->ddrphy_reg[0x3e]); in phy_cfg()
525 writel(dqs_odt, &ddr_phy->ddrphy_reg[0x41]); in phy_cfg()
526 writel(dqs_odt, &ddr_phy->ddrphy_reg[0x4e]); in phy_cfg()
527 writel(dqs_odt, &ddr_phy->ddrphy_reg[0x51]); in phy_cfg()
528 writel(dqs_odt, &ddr_phy->ddrphy_reg[0x5e]); in phy_cfg()
536 struct rk322x_sdram_channel *config = &sdram_params->ch[0]; in dram_cfg_rbc()
537 struct rk322x_service_sys *axi_bus = chan->msch; in dram_cfg_rbc()
539 move_to_config_state(chan->pctl); in dram_cfg_rbc()
541 if ((config->rank == 2) && (config->cs1_row == config->cs0_row)) { in dram_cfg_rbc()
542 if ((config->col + config->bw) == 12) { in dram_cfg_rbc()
545 } else if ((config->col + config->bw) == 11) { in dram_cfg_rbc()
550 noc_config = ((config->cs0_row - 13) << 4) | ((config->bk - 2) << 2) | in dram_cfg_rbc()
551 (config->col + config->bw - 11); in dram_cfg_rbc()
560 noc_config = ((config->bk - 2) << 6) | ((config->cs0_row - 13) << 4) | in dram_cfg_rbc()
561 (config->col + config->bw - 11); in dram_cfg_rbc()
573 writel(i, &axi_bus->ddrconf); in dram_cfg_rbc()
574 move_to_access_state(chan->pctl); in dram_cfg_rbc()
580 struct rk322x_sdram_channel *info = &sdram_params->ch[0]; in dram_all_config()
583 sys_reg |= sdram_params->base.dramtype << SYS_REG_DDRTYPE_SHIFT; in dram_all_config()
584 sys_reg |= (1 - 1) << SYS_REG_NUM_CH_SHIFT; in dram_all_config()
585 sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(0); in dram_all_config()
587 sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(0); in dram_all_config()
588 sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(0); in dram_all_config()
589 sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(0); in dram_all_config()
590 sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(0); in dram_all_config()
591 sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(0); in dram_all_config()
592 sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(0); in dram_all_config()
593 sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(0); in dram_all_config()
595 writel(sys_reg, &dram->grf->os_reg[2]); in dram_all_config()
605 struct rk322x_service_sys *axi_bus = dram->chan[0].msch; in dram_cap_detect()
607 if (sdram_params->base.dramtype == DDR3) in dram_cap_detect()
608 sdram_params->ch[0].dbw = 1; in dram_cap_detect()
610 sdram_params->ch[0].dbw = 2; in dram_cap_detect()
612 move_to_config_state(dram->chan[0].pctl); in dram_cap_detect()
615 if (data_training(&dram->chan[0]) == 0) { in dram_cap_detect()
620 move_to_lowpower_state(dram->chan[0].pctl); in dram_cap_detect()
622 move_to_config_state(dram->chan[0].pctl); in dram_cap_detect()
623 if (data_training(&dram->chan[0])) { in dram_cap_detect()
625 ret = -EINVAL; in dram_cap_detect()
628 sdram_params->ch[0].bw = bw; in dram_cap_detect()
629 sdram_params->ch[0].bk = 3; in dram_cap_detect()
632 writel(6, &axi_bus->ddrconf); in dram_cap_detect()
634 writel(3, &axi_bus->ddrconf); in dram_cap_detect()
635 move_to_access_state(dram->chan[0].pctl); in dram_cap_detect()
636 for (col = 11; col >= 9; col--) { in dram_cap_detect()
639 (1 << (col + bw - 1)); in dram_cap_detect()
647 ret = -EINVAL; in dram_cap_detect()
650 sdram_params->ch[0].col = col; in dram_cap_detect()
653 writel(10, &axi_bus->ddrconf); in dram_cap_detect()
656 for (row = 16; row >= 12; row--) { in dram_cap_detect()
658 addr = CONFIG_SYS_SDRAM_BASE + (1u << (row + 11 + 3 - 1)); in dram_cap_detect()
666 ret = -EINVAL; in dram_cap_detect()
668 sdram_params->ch[0].cs1_row = row; in dram_cap_detect()
669 sdram_params->ch[0].row_3_4 = 0; in dram_cap_detect()
670 sdram_params->ch[0].cs0_row = row; in dram_cap_detect()
678 sdram_params->ch[0].rank = 2; in dram_cap_detect()
680 sdram_params->ch[0].rank = 1; in dram_cap_detect()
690 ret = clk_set_rate(&dram->ddr_clk, in sdram_init()
691 sdram_params->base.ddr_freq * MHz * 2); in sdram_init()
697 phy_pctrl_reset(dram->cru, dram->chan[0].phy); in sdram_init()
698 phy_dll_bypass_set(dram->chan[0].phy, sdram_params->base.ddr_freq); in sdram_init()
699 pctl_cfg(dram->chan[0].pctl, sdram_params, dram->grf); in sdram_init()
700 phy_cfg(&dram->chan[0], sdram_params); in sdram_init()
701 writel(POWER_UP_START, &dram->chan[0].pctl->powctl); in sdram_init()
702 while (!(readl(&dram->chan[0].pctl->powstat) & POWER_UP_DONE)) in sdram_init()
704 memory_init(&dram->chan[0], sdram_params); in sdram_init()
705 move_to_access_state(dram->chan[0].pctl); in sdram_init()
709 dram_cfg_rbc(&dram->chan[0], sdram_params); in sdram_init()
719 const void *blob = gd->fdt_blob; in rk322x_dmc_ofdata_to_platdata()
723 params->num_channels = 1; in rk322x_dmc_ofdata_to_platdata()
725 ret = fdtdec_get_int_array(blob, node, "rockchip,pctl-timing", in rk322x_dmc_ofdata_to_platdata()
726 (u32 *)¶ms->pctl_timing, in rk322x_dmc_ofdata_to_platdata()
727 sizeof(params->pctl_timing) / sizeof(u32)); in rk322x_dmc_ofdata_to_platdata()
729 printf("%s: Cannot read rockchip,pctl-timing\n", __func__); in rk322x_dmc_ofdata_to_platdata()
730 return -EINVAL; in rk322x_dmc_ofdata_to_platdata()
732 ret = fdtdec_get_int_array(blob, node, "rockchip,phy-timing", in rk322x_dmc_ofdata_to_platdata()
733 (u32 *)¶ms->phy_timing, in rk322x_dmc_ofdata_to_platdata()
734 sizeof(params->phy_timing) / sizeof(u32)); in rk322x_dmc_ofdata_to_platdata()
736 printf("%s: Cannot read rockchip,phy-timing\n", __func__); in rk322x_dmc_ofdata_to_platdata()
737 return -EINVAL; in rk322x_dmc_ofdata_to_platdata()
739 ret = fdtdec_get_int_array(blob, node, "rockchip,sdram-params", in rk322x_dmc_ofdata_to_platdata()
740 (u32 *)¶ms->base, in rk322x_dmc_ofdata_to_platdata()
741 sizeof(params->base) / sizeof(u32)); in rk322x_dmc_ofdata_to_platdata()
743 printf("%s: Cannot read rockchip,sdram-params\n", __func__); in rk322x_dmc_ofdata_to_platdata()
744 return -EINVAL; in rk322x_dmc_ofdata_to_platdata()
746 ret = regmap_init_mem(dev_ofnode(dev), ¶ms->map); in rk322x_dmc_ofdata_to_platdata()
759 struct dtd_rockchip_rk322x_dmc *of_plat = &plat->of_plat; in conv_of_platdata()
762 memcpy(&plat->pctl_timing, of_plat->rockchip_pctl_timing, in conv_of_platdata()
763 sizeof(plat->pctl_timing)); in conv_of_platdata()
764 memcpy(&plat->phy_timing, of_plat->rockchip_phy_timing, in conv_of_platdata()
765 sizeof(plat->phy_timing)); in conv_of_platdata()
766 memcpy(&plat->base, of_plat->rockchip_sdram_params, sizeof(plat->base)); in conv_of_platdata()
768 plat->num_channels = 1; in conv_of_platdata()
769 ret = regmap_init_mem_platdata(dev, of_plat->reg, in conv_of_platdata()
770 ARRAY_SIZE(of_plat->reg) / 2, in conv_of_platdata()
771 &plat->map); in conv_of_platdata()
788 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); in rk322x_dmc_probe()
796 priv->chan[0].msch = syscon_get_first_range(ROCKCHIP_SYSCON_MSCH); in rk322x_dmc_probe()
797 priv->chan[0].pctl = regmap_get_range(plat->map, 0); in rk322x_dmc_probe()
798 priv->chan[0].phy = regmap_get_range(plat->map, 1); in rk322x_dmc_probe()
802 priv->ddr_clk.id = CLK_DDR; in rk322x_dmc_probe()
803 ret = clk_request(dev_clk, &priv->ddr_clk); in rk322x_dmc_probe()
807 priv->cru = rockchip_get_cru(); in rk322x_dmc_probe()
808 if (IS_ERR(priv->cru)) in rk322x_dmc_probe()
809 return PTR_ERR(priv->cru); in rk322x_dmc_probe()
814 priv->info.base = CONFIG_SYS_SDRAM_BASE; in rk322x_dmc_probe()
815 priv->info.size = rockchip_sdram_size( in rk322x_dmc_probe()
816 (phys_addr_t)&priv->grf->os_reg[2]); in rk322x_dmc_probe()
826 *info = priv->info; in rk322x_dmc_get_info()
836 { .compatible = "rockchip,rk3228-dmc" },