1deda8287SViresh Kumar /*
2deda8287SViresh Kumar * Driver header file for the ST Microelectronics SPEAr pinmux
3deda8287SViresh Kumar *
4deda8287SViresh Kumar * Copyright (C) 2012 ST Microelectronics
5da89947bSViresh Kumar * Viresh Kumar <vireshk@kernel.org>
6deda8287SViresh Kumar *
7deda8287SViresh Kumar * This file is licensed under the terms of the GNU General Public
8deda8287SViresh Kumar * License version 2. This program is licensed "as is" without any
9deda8287SViresh Kumar * warranty of any kind, whether express or implied.
10deda8287SViresh Kumar */
11deda8287SViresh Kumar
12deda8287SViresh Kumar #ifndef __PINMUX_SPEAR_H__
13deda8287SViresh Kumar #define __PINMUX_SPEAR_H__
14deda8287SViresh Kumar
151c5fb66aSLinus Walleij #include <linux/gpio/driver.h>
16826d6ca8SShiraz Hashim #include <linux/io.h>
17deda8287SViresh Kumar #include <linux/pinctrl/pinctrl.h>
18*d11db044SHerve Codina #include <linux/regmap.h>
19deda8287SViresh Kumar #include <linux/types.h>
20deda8287SViresh Kumar
21deda8287SViresh Kumar struct platform_device;
22deda8287SViresh Kumar struct device;
23826d6ca8SShiraz Hashim struct spear_pmx;
24deda8287SViresh Kumar
25deda8287SViresh Kumar /**
26deda8287SViresh Kumar * struct spear_pmx_mode - SPEAr pmx mode
27deda8287SViresh Kumar * @name: name of pmx mode
28deda8287SViresh Kumar * @mode: mode id
29deda8287SViresh Kumar * @reg: register for configuring this mode
30deda8287SViresh Kumar * @mask: mask of this mode in reg
31deda8287SViresh Kumar * @val: val to be configured at reg after doing (val & mask)
32deda8287SViresh Kumar */
33deda8287SViresh Kumar struct spear_pmx_mode {
34deda8287SViresh Kumar const char *const name;
35deda8287SViresh Kumar u16 mode;
36deda8287SViresh Kumar u16 reg;
37deda8287SViresh Kumar u16 mask;
38deda8287SViresh Kumar u32 val;
39deda8287SViresh Kumar };
40deda8287SViresh Kumar
41deda8287SViresh Kumar /**
42deda8287SViresh Kumar * struct spear_muxreg - SPEAr mux reg configuration
43deda8287SViresh Kumar * @reg: register offset
44deda8287SViresh Kumar * @mask: mask bits
45deda8287SViresh Kumar * @val: val to be written on mask bits
46deda8287SViresh Kumar */
47deda8287SViresh Kumar struct spear_muxreg {
48deda8287SViresh Kumar u16 reg;
49deda8287SViresh Kumar u32 mask;
50deda8287SViresh Kumar u32 val;
51deda8287SViresh Kumar };
52deda8287SViresh Kumar
53f4f8e563SViresh Kumar struct spear_gpio_pingroup {
54f4f8e563SViresh Kumar const unsigned *pins;
55f4f8e563SViresh Kumar unsigned npins;
56f4f8e563SViresh Kumar struct spear_muxreg *muxregs;
57f4f8e563SViresh Kumar u8 nmuxregs;
58f4f8e563SViresh Kumar };
59f4f8e563SViresh Kumar
60f4f8e563SViresh Kumar /* ste: set to enable */
61f4f8e563SViresh Kumar #define DEFINE_MUXREG(__pins, __muxreg, __mask, __ste) \
62f4f8e563SViresh Kumar static struct spear_muxreg __pins##_muxregs[] = { \
63f4f8e563SViresh Kumar { \
64f4f8e563SViresh Kumar .reg = __muxreg, \
65f4f8e563SViresh Kumar .mask = __mask, \
66f4f8e563SViresh Kumar .val = __ste ? __mask : 0, \
67f4f8e563SViresh Kumar }, \
68f4f8e563SViresh Kumar }
69f4f8e563SViresh Kumar
70f4f8e563SViresh Kumar #define DEFINE_2_MUXREG(__pins, __muxreg1, __muxreg2, __mask, __ste1, __ste2) \
71f4f8e563SViresh Kumar static struct spear_muxreg __pins##_muxregs[] = { \
72f4f8e563SViresh Kumar { \
73f4f8e563SViresh Kumar .reg = __muxreg1, \
74f4f8e563SViresh Kumar .mask = __mask, \
75f4f8e563SViresh Kumar .val = __ste1 ? __mask : 0, \
76f4f8e563SViresh Kumar }, { \
77f4f8e563SViresh Kumar .reg = __muxreg2, \
78f4f8e563SViresh Kumar .mask = __mask, \
79f4f8e563SViresh Kumar .val = __ste2 ? __mask : 0, \
80f4f8e563SViresh Kumar }, \
81f4f8e563SViresh Kumar }
82f4f8e563SViresh Kumar
83f4f8e563SViresh Kumar #define GPIO_PINGROUP(__pins) \
84f4f8e563SViresh Kumar { \
85f4f8e563SViresh Kumar .pins = __pins, \
86f4f8e563SViresh Kumar .npins = ARRAY_SIZE(__pins), \
87f4f8e563SViresh Kumar .muxregs = __pins##_muxregs, \
88f4f8e563SViresh Kumar .nmuxregs = ARRAY_SIZE(__pins##_muxregs), \
89f4f8e563SViresh Kumar }
90f4f8e563SViresh Kumar
91deda8287SViresh Kumar /**
92deda8287SViresh Kumar * struct spear_modemux - SPEAr mode mux configuration
93deda8287SViresh Kumar * @modes: mode ids supported by this group of muxregs
94deda8287SViresh Kumar * @nmuxregs: number of muxreg configurations to be done for modes
95deda8287SViresh Kumar * @muxregs: array of muxreg configurations to be done for modes
96deda8287SViresh Kumar */
97deda8287SViresh Kumar struct spear_modemux {
98deda8287SViresh Kumar u16 modes;
99deda8287SViresh Kumar u8 nmuxregs;
100deda8287SViresh Kumar struct spear_muxreg *muxregs;
101deda8287SViresh Kumar };
102deda8287SViresh Kumar
103deda8287SViresh Kumar /**
104deda8287SViresh Kumar * struct spear_pingroup - SPEAr pin group configurations
105deda8287SViresh Kumar * @name: name of pin group
106deda8287SViresh Kumar * @pins: array containing pin numbers
107deda8287SViresh Kumar * @npins: size of pins array
108deda8287SViresh Kumar * @modemuxs: array of modemux configurations for this pin group
109deda8287SViresh Kumar * @nmodemuxs: size of array modemuxs
110deda8287SViresh Kumar *
111deda8287SViresh Kumar * A representation of a group of pins in the SPEAr pin controller. Each group
112deda8287SViresh Kumar * allows some parameter or parameters to be configured.
113deda8287SViresh Kumar */
114deda8287SViresh Kumar struct spear_pingroup {
115deda8287SViresh Kumar const char *name;
116deda8287SViresh Kumar const unsigned *pins;
117deda8287SViresh Kumar unsigned npins;
118deda8287SViresh Kumar struct spear_modemux *modemuxs;
119deda8287SViresh Kumar unsigned nmodemuxs;
120deda8287SViresh Kumar };
121deda8287SViresh Kumar
122deda8287SViresh Kumar /**
123deda8287SViresh Kumar * struct spear_function - SPEAr pinctrl mux function
124deda8287SViresh Kumar * @name: The name of the function, exported to pinctrl core.
125deda8287SViresh Kumar * @groups: An array of pin groups that may select this function.
126deda8287SViresh Kumar * @ngroups: The number of entries in @groups.
127deda8287SViresh Kumar */
128deda8287SViresh Kumar struct spear_function {
129deda8287SViresh Kumar const char *name;
130deda8287SViresh Kumar const char *const *groups;
131deda8287SViresh Kumar unsigned ngroups;
132deda8287SViresh Kumar };
133deda8287SViresh Kumar
134deda8287SViresh Kumar /**
135deda8287SViresh Kumar * struct spear_pinctrl_machdata - SPEAr pin controller machine driver
136deda8287SViresh Kumar * configuration
137deda8287SViresh Kumar * @pins: An array describing all pins the pin controller affects.
138deda8287SViresh Kumar * All pins which are also GPIOs must be listed first within the *array,
139deda8287SViresh Kumar * and be numbered identically to the GPIO controller's *numbering.
140deda8287SViresh Kumar * @npins: The numbmer of entries in @pins.
141deda8287SViresh Kumar * @functions: An array describing all mux functions the SoC supports.
142deda8287SViresh Kumar * @nfunctions: The numbmer of entries in @functions.
143deda8287SViresh Kumar * @groups: An array describing all pin groups the pin SoC supports.
144deda8287SViresh Kumar * @ngroups: The numbmer of entries in @groups.
145f4f8e563SViresh Kumar * @gpio_pingroups: gpio pingroups
146f4f8e563SViresh Kumar * @ngpio_pingroups: gpio pingroups count
147deda8287SViresh Kumar *
148deda8287SViresh Kumar * @modes_supported: Does SoC support modes
149deda8287SViresh Kumar * @mode: mode configured from probe
150deda8287SViresh Kumar * @pmx_modes: array of modes supported by SoC
151deda8287SViresh Kumar * @npmx_modes: number of entries in pmx_modes.
152deda8287SViresh Kumar */
153deda8287SViresh Kumar struct spear_pinctrl_machdata {
154deda8287SViresh Kumar const struct pinctrl_pin_desc *pins;
155deda8287SViresh Kumar unsigned npins;
156deda8287SViresh Kumar struct spear_function **functions;
157deda8287SViresh Kumar unsigned nfunctions;
158deda8287SViresh Kumar struct spear_pingroup **groups;
159deda8287SViresh Kumar unsigned ngroups;
160f4f8e563SViresh Kumar struct spear_gpio_pingroup *gpio_pingroups;
161826d6ca8SShiraz Hashim void (*gpio_request_endisable)(struct spear_pmx *pmx, int offset,
162826d6ca8SShiraz Hashim bool enable);
163f4f8e563SViresh Kumar unsigned ngpio_pingroups;
164deda8287SViresh Kumar
165deda8287SViresh Kumar bool modes_supported;
166deda8287SViresh Kumar u16 mode;
167deda8287SViresh Kumar struct spear_pmx_mode **pmx_modes;
168deda8287SViresh Kumar unsigned npmx_modes;
169deda8287SViresh Kumar };
170deda8287SViresh Kumar
171deda8287SViresh Kumar /**
172deda8287SViresh Kumar * struct spear_pmx - SPEAr pinctrl mux
173deda8287SViresh Kumar * @dev: pointer to struct dev of platform_device registered
174deda8287SViresh Kumar * @pctl: pointer to struct pinctrl_dev
175deda8287SViresh Kumar * @machdata: pointer to SoC or machine specific structure
176*d11db044SHerve Codina * @regmap: regmap of pinmux controller
177deda8287SViresh Kumar */
178deda8287SViresh Kumar struct spear_pmx {
179deda8287SViresh Kumar struct device *dev;
180deda8287SViresh Kumar struct pinctrl_dev *pctl;
181deda8287SViresh Kumar struct spear_pinctrl_machdata *machdata;
182*d11db044SHerve Codina struct regmap *regmap;
183deda8287SViresh Kumar };
184deda8287SViresh Kumar
185deda8287SViresh Kumar /* exported routines */
pmx_readl(struct spear_pmx * pmx,u32 reg)186826d6ca8SShiraz Hashim static inline u32 pmx_readl(struct spear_pmx *pmx, u32 reg)
187826d6ca8SShiraz Hashim {
188*d11db044SHerve Codina u32 val;
189*d11db044SHerve Codina
190*d11db044SHerve Codina regmap_read(pmx->regmap, reg, &val);
191*d11db044SHerve Codina return val;
192826d6ca8SShiraz Hashim }
193826d6ca8SShiraz Hashim
pmx_writel(struct spear_pmx * pmx,u32 val,u32 reg)194826d6ca8SShiraz Hashim static inline void pmx_writel(struct spear_pmx *pmx, u32 val, u32 reg)
195826d6ca8SShiraz Hashim {
196*d11db044SHerve Codina regmap_write(pmx->regmap, reg, val);
197826d6ca8SShiraz Hashim }
198826d6ca8SShiraz Hashim
199150632b0SGreg Kroah-Hartman void pmx_init_addr(struct spear_pinctrl_machdata *machdata, u16 reg);
200150632b0SGreg Kroah-Hartman void pmx_init_gpio_pingroup_addr(struct spear_gpio_pingroup *gpio_pingroup,
201f4f8e563SViresh Kumar unsigned count, u16 reg);
202150632b0SGreg Kroah-Hartman int spear_pinctrl_probe(struct platform_device *pdev,
203deda8287SViresh Kumar struct spear_pinctrl_machdata *machdata);
204d1e77afeSViresh Kumar
205d1e77afeSViresh Kumar #define SPEAR_PIN_0_TO_101 \
206d1e77afeSViresh Kumar PINCTRL_PIN(0, "PLGPIO0"), \
207d1e77afeSViresh Kumar PINCTRL_PIN(1, "PLGPIO1"), \
208d1e77afeSViresh Kumar PINCTRL_PIN(2, "PLGPIO2"), \
209d1e77afeSViresh Kumar PINCTRL_PIN(3, "PLGPIO3"), \
210d1e77afeSViresh Kumar PINCTRL_PIN(4, "PLGPIO4"), \
211d1e77afeSViresh Kumar PINCTRL_PIN(5, "PLGPIO5"), \
212d1e77afeSViresh Kumar PINCTRL_PIN(6, "PLGPIO6"), \
213d1e77afeSViresh Kumar PINCTRL_PIN(7, "PLGPIO7"), \
214d1e77afeSViresh Kumar PINCTRL_PIN(8, "PLGPIO8"), \
215d1e77afeSViresh Kumar PINCTRL_PIN(9, "PLGPIO9"), \
216d1e77afeSViresh Kumar PINCTRL_PIN(10, "PLGPIO10"), \
217d1e77afeSViresh Kumar PINCTRL_PIN(11, "PLGPIO11"), \
218d1e77afeSViresh Kumar PINCTRL_PIN(12, "PLGPIO12"), \
219d1e77afeSViresh Kumar PINCTRL_PIN(13, "PLGPIO13"), \
220d1e77afeSViresh Kumar PINCTRL_PIN(14, "PLGPIO14"), \
221d1e77afeSViresh Kumar PINCTRL_PIN(15, "PLGPIO15"), \
222d1e77afeSViresh Kumar PINCTRL_PIN(16, "PLGPIO16"), \
223d1e77afeSViresh Kumar PINCTRL_PIN(17, "PLGPIO17"), \
224d1e77afeSViresh Kumar PINCTRL_PIN(18, "PLGPIO18"), \
225d1e77afeSViresh Kumar PINCTRL_PIN(19, "PLGPIO19"), \
226d1e77afeSViresh Kumar PINCTRL_PIN(20, "PLGPIO20"), \
227d1e77afeSViresh Kumar PINCTRL_PIN(21, "PLGPIO21"), \
228d1e77afeSViresh Kumar PINCTRL_PIN(22, "PLGPIO22"), \
229d1e77afeSViresh Kumar PINCTRL_PIN(23, "PLGPIO23"), \
230d1e77afeSViresh Kumar PINCTRL_PIN(24, "PLGPIO24"), \
231d1e77afeSViresh Kumar PINCTRL_PIN(25, "PLGPIO25"), \
232d1e77afeSViresh Kumar PINCTRL_PIN(26, "PLGPIO26"), \
233d1e77afeSViresh Kumar PINCTRL_PIN(27, "PLGPIO27"), \
234d1e77afeSViresh Kumar PINCTRL_PIN(28, "PLGPIO28"), \
235d1e77afeSViresh Kumar PINCTRL_PIN(29, "PLGPIO29"), \
236d1e77afeSViresh Kumar PINCTRL_PIN(30, "PLGPIO30"), \
237d1e77afeSViresh Kumar PINCTRL_PIN(31, "PLGPIO31"), \
238d1e77afeSViresh Kumar PINCTRL_PIN(32, "PLGPIO32"), \
239d1e77afeSViresh Kumar PINCTRL_PIN(33, "PLGPIO33"), \
240d1e77afeSViresh Kumar PINCTRL_PIN(34, "PLGPIO34"), \
241d1e77afeSViresh Kumar PINCTRL_PIN(35, "PLGPIO35"), \
242d1e77afeSViresh Kumar PINCTRL_PIN(36, "PLGPIO36"), \
243d1e77afeSViresh Kumar PINCTRL_PIN(37, "PLGPIO37"), \
244d1e77afeSViresh Kumar PINCTRL_PIN(38, "PLGPIO38"), \
245d1e77afeSViresh Kumar PINCTRL_PIN(39, "PLGPIO39"), \
246d1e77afeSViresh Kumar PINCTRL_PIN(40, "PLGPIO40"), \
247d1e77afeSViresh Kumar PINCTRL_PIN(41, "PLGPIO41"), \
248d1e77afeSViresh Kumar PINCTRL_PIN(42, "PLGPIO42"), \
249d1e77afeSViresh Kumar PINCTRL_PIN(43, "PLGPIO43"), \
250d1e77afeSViresh Kumar PINCTRL_PIN(44, "PLGPIO44"), \
251d1e77afeSViresh Kumar PINCTRL_PIN(45, "PLGPIO45"), \
252d1e77afeSViresh Kumar PINCTRL_PIN(46, "PLGPIO46"), \
253d1e77afeSViresh Kumar PINCTRL_PIN(47, "PLGPIO47"), \
254d1e77afeSViresh Kumar PINCTRL_PIN(48, "PLGPIO48"), \
255d1e77afeSViresh Kumar PINCTRL_PIN(49, "PLGPIO49"), \
256d1e77afeSViresh Kumar PINCTRL_PIN(50, "PLGPIO50"), \
257d1e77afeSViresh Kumar PINCTRL_PIN(51, "PLGPIO51"), \
258d1e77afeSViresh Kumar PINCTRL_PIN(52, "PLGPIO52"), \
259d1e77afeSViresh Kumar PINCTRL_PIN(53, "PLGPIO53"), \
260d1e77afeSViresh Kumar PINCTRL_PIN(54, "PLGPIO54"), \
261d1e77afeSViresh Kumar PINCTRL_PIN(55, "PLGPIO55"), \
262d1e77afeSViresh Kumar PINCTRL_PIN(56, "PLGPIO56"), \
263d1e77afeSViresh Kumar PINCTRL_PIN(57, "PLGPIO57"), \
264d1e77afeSViresh Kumar PINCTRL_PIN(58, "PLGPIO58"), \
265d1e77afeSViresh Kumar PINCTRL_PIN(59, "PLGPIO59"), \
266d1e77afeSViresh Kumar PINCTRL_PIN(60, "PLGPIO60"), \
267d1e77afeSViresh Kumar PINCTRL_PIN(61, "PLGPIO61"), \
268d1e77afeSViresh Kumar PINCTRL_PIN(62, "PLGPIO62"), \
269d1e77afeSViresh Kumar PINCTRL_PIN(63, "PLGPIO63"), \
270d1e77afeSViresh Kumar PINCTRL_PIN(64, "PLGPIO64"), \
271d1e77afeSViresh Kumar PINCTRL_PIN(65, "PLGPIO65"), \
272d1e77afeSViresh Kumar PINCTRL_PIN(66, "PLGPIO66"), \
273d1e77afeSViresh Kumar PINCTRL_PIN(67, "PLGPIO67"), \
274d1e77afeSViresh Kumar PINCTRL_PIN(68, "PLGPIO68"), \
275d1e77afeSViresh Kumar PINCTRL_PIN(69, "PLGPIO69"), \
276d1e77afeSViresh Kumar PINCTRL_PIN(70, "PLGPIO70"), \
277d1e77afeSViresh Kumar PINCTRL_PIN(71, "PLGPIO71"), \
278d1e77afeSViresh Kumar PINCTRL_PIN(72, "PLGPIO72"), \
279d1e77afeSViresh Kumar PINCTRL_PIN(73, "PLGPIO73"), \
280d1e77afeSViresh Kumar PINCTRL_PIN(74, "PLGPIO74"), \
281d1e77afeSViresh Kumar PINCTRL_PIN(75, "PLGPIO75"), \
282d1e77afeSViresh Kumar PINCTRL_PIN(76, "PLGPIO76"), \
283d1e77afeSViresh Kumar PINCTRL_PIN(77, "PLGPIO77"), \
284d1e77afeSViresh Kumar PINCTRL_PIN(78, "PLGPIO78"), \
285d1e77afeSViresh Kumar PINCTRL_PIN(79, "PLGPIO79"), \
286d1e77afeSViresh Kumar PINCTRL_PIN(80, "PLGPIO80"), \
287d1e77afeSViresh Kumar PINCTRL_PIN(81, "PLGPIO81"), \
288d1e77afeSViresh Kumar PINCTRL_PIN(82, "PLGPIO82"), \
289d1e77afeSViresh Kumar PINCTRL_PIN(83, "PLGPIO83"), \
290d1e77afeSViresh Kumar PINCTRL_PIN(84, "PLGPIO84"), \
291d1e77afeSViresh Kumar PINCTRL_PIN(85, "PLGPIO85"), \
292d1e77afeSViresh Kumar PINCTRL_PIN(86, "PLGPIO86"), \
293d1e77afeSViresh Kumar PINCTRL_PIN(87, "PLGPIO87"), \
294d1e77afeSViresh Kumar PINCTRL_PIN(88, "PLGPIO88"), \
295d1e77afeSViresh Kumar PINCTRL_PIN(89, "PLGPIO89"), \
296d1e77afeSViresh Kumar PINCTRL_PIN(90, "PLGPIO90"), \
297d1e77afeSViresh Kumar PINCTRL_PIN(91, "PLGPIO91"), \
298d1e77afeSViresh Kumar PINCTRL_PIN(92, "PLGPIO92"), \
299d1e77afeSViresh Kumar PINCTRL_PIN(93, "PLGPIO93"), \
300d1e77afeSViresh Kumar PINCTRL_PIN(94, "PLGPIO94"), \
301d1e77afeSViresh Kumar PINCTRL_PIN(95, "PLGPIO95"), \
302d1e77afeSViresh Kumar PINCTRL_PIN(96, "PLGPIO96"), \
303d1e77afeSViresh Kumar PINCTRL_PIN(97, "PLGPIO97"), \
304d1e77afeSViresh Kumar PINCTRL_PIN(98, "PLGPIO98"), \
305d1e77afeSViresh Kumar PINCTRL_PIN(99, "PLGPIO99"), \
306d1e77afeSViresh Kumar PINCTRL_PIN(100, "PLGPIO100"), \
307d1e77afeSViresh Kumar PINCTRL_PIN(101, "PLGPIO101")
308d1e77afeSViresh Kumar
30985ed41a7SViresh Kumar #define SPEAR_PIN_102_TO_245 \
31085ed41a7SViresh Kumar PINCTRL_PIN(102, "PLGPIO102"), \
31185ed41a7SViresh Kumar PINCTRL_PIN(103, "PLGPIO103"), \
31285ed41a7SViresh Kumar PINCTRL_PIN(104, "PLGPIO104"), \
31385ed41a7SViresh Kumar PINCTRL_PIN(105, "PLGPIO105"), \
31485ed41a7SViresh Kumar PINCTRL_PIN(106, "PLGPIO106"), \
31585ed41a7SViresh Kumar PINCTRL_PIN(107, "PLGPIO107"), \
31685ed41a7SViresh Kumar PINCTRL_PIN(108, "PLGPIO108"), \
31785ed41a7SViresh Kumar PINCTRL_PIN(109, "PLGPIO109"), \
31885ed41a7SViresh Kumar PINCTRL_PIN(110, "PLGPIO110"), \
31985ed41a7SViresh Kumar PINCTRL_PIN(111, "PLGPIO111"), \
32085ed41a7SViresh Kumar PINCTRL_PIN(112, "PLGPIO112"), \
32185ed41a7SViresh Kumar PINCTRL_PIN(113, "PLGPIO113"), \
32285ed41a7SViresh Kumar PINCTRL_PIN(114, "PLGPIO114"), \
32385ed41a7SViresh Kumar PINCTRL_PIN(115, "PLGPIO115"), \
32485ed41a7SViresh Kumar PINCTRL_PIN(116, "PLGPIO116"), \
32585ed41a7SViresh Kumar PINCTRL_PIN(117, "PLGPIO117"), \
32685ed41a7SViresh Kumar PINCTRL_PIN(118, "PLGPIO118"), \
32785ed41a7SViresh Kumar PINCTRL_PIN(119, "PLGPIO119"), \
32885ed41a7SViresh Kumar PINCTRL_PIN(120, "PLGPIO120"), \
32985ed41a7SViresh Kumar PINCTRL_PIN(121, "PLGPIO121"), \
33085ed41a7SViresh Kumar PINCTRL_PIN(122, "PLGPIO122"), \
33185ed41a7SViresh Kumar PINCTRL_PIN(123, "PLGPIO123"), \
33285ed41a7SViresh Kumar PINCTRL_PIN(124, "PLGPIO124"), \
33385ed41a7SViresh Kumar PINCTRL_PIN(125, "PLGPIO125"), \
33485ed41a7SViresh Kumar PINCTRL_PIN(126, "PLGPIO126"), \
33585ed41a7SViresh Kumar PINCTRL_PIN(127, "PLGPIO127"), \
33685ed41a7SViresh Kumar PINCTRL_PIN(128, "PLGPIO128"), \
33785ed41a7SViresh Kumar PINCTRL_PIN(129, "PLGPIO129"), \
33885ed41a7SViresh Kumar PINCTRL_PIN(130, "PLGPIO130"), \
33985ed41a7SViresh Kumar PINCTRL_PIN(131, "PLGPIO131"), \
34085ed41a7SViresh Kumar PINCTRL_PIN(132, "PLGPIO132"), \
34185ed41a7SViresh Kumar PINCTRL_PIN(133, "PLGPIO133"), \
34285ed41a7SViresh Kumar PINCTRL_PIN(134, "PLGPIO134"), \
34385ed41a7SViresh Kumar PINCTRL_PIN(135, "PLGPIO135"), \
34485ed41a7SViresh Kumar PINCTRL_PIN(136, "PLGPIO136"), \
34585ed41a7SViresh Kumar PINCTRL_PIN(137, "PLGPIO137"), \
34685ed41a7SViresh Kumar PINCTRL_PIN(138, "PLGPIO138"), \
34785ed41a7SViresh Kumar PINCTRL_PIN(139, "PLGPIO139"), \
34885ed41a7SViresh Kumar PINCTRL_PIN(140, "PLGPIO140"), \
34985ed41a7SViresh Kumar PINCTRL_PIN(141, "PLGPIO141"), \
35085ed41a7SViresh Kumar PINCTRL_PIN(142, "PLGPIO142"), \
35185ed41a7SViresh Kumar PINCTRL_PIN(143, "PLGPIO143"), \
35285ed41a7SViresh Kumar PINCTRL_PIN(144, "PLGPIO144"), \
35385ed41a7SViresh Kumar PINCTRL_PIN(145, "PLGPIO145"), \
35485ed41a7SViresh Kumar PINCTRL_PIN(146, "PLGPIO146"), \
35585ed41a7SViresh Kumar PINCTRL_PIN(147, "PLGPIO147"), \
35685ed41a7SViresh Kumar PINCTRL_PIN(148, "PLGPIO148"), \
35785ed41a7SViresh Kumar PINCTRL_PIN(149, "PLGPIO149"), \
35885ed41a7SViresh Kumar PINCTRL_PIN(150, "PLGPIO150"), \
35985ed41a7SViresh Kumar PINCTRL_PIN(151, "PLGPIO151"), \
36085ed41a7SViresh Kumar PINCTRL_PIN(152, "PLGPIO152"), \
36185ed41a7SViresh Kumar PINCTRL_PIN(153, "PLGPIO153"), \
36285ed41a7SViresh Kumar PINCTRL_PIN(154, "PLGPIO154"), \
36385ed41a7SViresh Kumar PINCTRL_PIN(155, "PLGPIO155"), \
36485ed41a7SViresh Kumar PINCTRL_PIN(156, "PLGPIO156"), \
36585ed41a7SViresh Kumar PINCTRL_PIN(157, "PLGPIO157"), \
36685ed41a7SViresh Kumar PINCTRL_PIN(158, "PLGPIO158"), \
36785ed41a7SViresh Kumar PINCTRL_PIN(159, "PLGPIO159"), \
36885ed41a7SViresh Kumar PINCTRL_PIN(160, "PLGPIO160"), \
36985ed41a7SViresh Kumar PINCTRL_PIN(161, "PLGPIO161"), \
37085ed41a7SViresh Kumar PINCTRL_PIN(162, "PLGPIO162"), \
37185ed41a7SViresh Kumar PINCTRL_PIN(163, "PLGPIO163"), \
37285ed41a7SViresh Kumar PINCTRL_PIN(164, "PLGPIO164"), \
37385ed41a7SViresh Kumar PINCTRL_PIN(165, "PLGPIO165"), \
37485ed41a7SViresh Kumar PINCTRL_PIN(166, "PLGPIO166"), \
37585ed41a7SViresh Kumar PINCTRL_PIN(167, "PLGPIO167"), \
37685ed41a7SViresh Kumar PINCTRL_PIN(168, "PLGPIO168"), \
37785ed41a7SViresh Kumar PINCTRL_PIN(169, "PLGPIO169"), \
37885ed41a7SViresh Kumar PINCTRL_PIN(170, "PLGPIO170"), \
37985ed41a7SViresh Kumar PINCTRL_PIN(171, "PLGPIO171"), \
38085ed41a7SViresh Kumar PINCTRL_PIN(172, "PLGPIO172"), \
38185ed41a7SViresh Kumar PINCTRL_PIN(173, "PLGPIO173"), \
38285ed41a7SViresh Kumar PINCTRL_PIN(174, "PLGPIO174"), \
38385ed41a7SViresh Kumar PINCTRL_PIN(175, "PLGPIO175"), \
38485ed41a7SViresh Kumar PINCTRL_PIN(176, "PLGPIO176"), \
38585ed41a7SViresh Kumar PINCTRL_PIN(177, "PLGPIO177"), \
38685ed41a7SViresh Kumar PINCTRL_PIN(178, "PLGPIO178"), \
38785ed41a7SViresh Kumar PINCTRL_PIN(179, "PLGPIO179"), \
38885ed41a7SViresh Kumar PINCTRL_PIN(180, "PLGPIO180"), \
38985ed41a7SViresh Kumar PINCTRL_PIN(181, "PLGPIO181"), \
39085ed41a7SViresh Kumar PINCTRL_PIN(182, "PLGPIO182"), \
39185ed41a7SViresh Kumar PINCTRL_PIN(183, "PLGPIO183"), \
39285ed41a7SViresh Kumar PINCTRL_PIN(184, "PLGPIO184"), \
39385ed41a7SViresh Kumar PINCTRL_PIN(185, "PLGPIO185"), \
39485ed41a7SViresh Kumar PINCTRL_PIN(186, "PLGPIO186"), \
39585ed41a7SViresh Kumar PINCTRL_PIN(187, "PLGPIO187"), \
39685ed41a7SViresh Kumar PINCTRL_PIN(188, "PLGPIO188"), \
39785ed41a7SViresh Kumar PINCTRL_PIN(189, "PLGPIO189"), \
39885ed41a7SViresh Kumar PINCTRL_PIN(190, "PLGPIO190"), \
39985ed41a7SViresh Kumar PINCTRL_PIN(191, "PLGPIO191"), \
40085ed41a7SViresh Kumar PINCTRL_PIN(192, "PLGPIO192"), \
40185ed41a7SViresh Kumar PINCTRL_PIN(193, "PLGPIO193"), \
40285ed41a7SViresh Kumar PINCTRL_PIN(194, "PLGPIO194"), \
40385ed41a7SViresh Kumar PINCTRL_PIN(195, "PLGPIO195"), \
40485ed41a7SViresh Kumar PINCTRL_PIN(196, "PLGPIO196"), \
40585ed41a7SViresh Kumar PINCTRL_PIN(197, "PLGPIO197"), \
40685ed41a7SViresh Kumar PINCTRL_PIN(198, "PLGPIO198"), \
40785ed41a7SViresh Kumar PINCTRL_PIN(199, "PLGPIO199"), \
40885ed41a7SViresh Kumar PINCTRL_PIN(200, "PLGPIO200"), \
40985ed41a7SViresh Kumar PINCTRL_PIN(201, "PLGPIO201"), \
41085ed41a7SViresh Kumar PINCTRL_PIN(202, "PLGPIO202"), \
41185ed41a7SViresh Kumar PINCTRL_PIN(203, "PLGPIO203"), \
41285ed41a7SViresh Kumar PINCTRL_PIN(204, "PLGPIO204"), \
41385ed41a7SViresh Kumar PINCTRL_PIN(205, "PLGPIO205"), \
41485ed41a7SViresh Kumar PINCTRL_PIN(206, "PLGPIO206"), \
41585ed41a7SViresh Kumar PINCTRL_PIN(207, "PLGPIO207"), \
41685ed41a7SViresh Kumar PINCTRL_PIN(208, "PLGPIO208"), \
41785ed41a7SViresh Kumar PINCTRL_PIN(209, "PLGPIO209"), \
41885ed41a7SViresh Kumar PINCTRL_PIN(210, "PLGPIO210"), \
41985ed41a7SViresh Kumar PINCTRL_PIN(211, "PLGPIO211"), \
42085ed41a7SViresh Kumar PINCTRL_PIN(212, "PLGPIO212"), \
42185ed41a7SViresh Kumar PINCTRL_PIN(213, "PLGPIO213"), \
42285ed41a7SViresh Kumar PINCTRL_PIN(214, "PLGPIO214"), \
42385ed41a7SViresh Kumar PINCTRL_PIN(215, "PLGPIO215"), \
42485ed41a7SViresh Kumar PINCTRL_PIN(216, "PLGPIO216"), \
42585ed41a7SViresh Kumar PINCTRL_PIN(217, "PLGPIO217"), \
42685ed41a7SViresh Kumar PINCTRL_PIN(218, "PLGPIO218"), \
42785ed41a7SViresh Kumar PINCTRL_PIN(219, "PLGPIO219"), \
42885ed41a7SViresh Kumar PINCTRL_PIN(220, "PLGPIO220"), \
42985ed41a7SViresh Kumar PINCTRL_PIN(221, "PLGPIO221"), \
43085ed41a7SViresh Kumar PINCTRL_PIN(222, "PLGPIO222"), \
43185ed41a7SViresh Kumar PINCTRL_PIN(223, "PLGPIO223"), \
43285ed41a7SViresh Kumar PINCTRL_PIN(224, "PLGPIO224"), \
43385ed41a7SViresh Kumar PINCTRL_PIN(225, "PLGPIO225"), \
43485ed41a7SViresh Kumar PINCTRL_PIN(226, "PLGPIO226"), \
43585ed41a7SViresh Kumar PINCTRL_PIN(227, "PLGPIO227"), \
43685ed41a7SViresh Kumar PINCTRL_PIN(228, "PLGPIO228"), \
43785ed41a7SViresh Kumar PINCTRL_PIN(229, "PLGPIO229"), \
43885ed41a7SViresh Kumar PINCTRL_PIN(230, "PLGPIO230"), \
43985ed41a7SViresh Kumar PINCTRL_PIN(231, "PLGPIO231"), \
44085ed41a7SViresh Kumar PINCTRL_PIN(232, "PLGPIO232"), \
44185ed41a7SViresh Kumar PINCTRL_PIN(233, "PLGPIO233"), \
44285ed41a7SViresh Kumar PINCTRL_PIN(234, "PLGPIO234"), \
44385ed41a7SViresh Kumar PINCTRL_PIN(235, "PLGPIO235"), \
44485ed41a7SViresh Kumar PINCTRL_PIN(236, "PLGPIO236"), \
44585ed41a7SViresh Kumar PINCTRL_PIN(237, "PLGPIO237"), \
44685ed41a7SViresh Kumar PINCTRL_PIN(238, "PLGPIO238"), \
44785ed41a7SViresh Kumar PINCTRL_PIN(239, "PLGPIO239"), \
44885ed41a7SViresh Kumar PINCTRL_PIN(240, "PLGPIO240"), \
44985ed41a7SViresh Kumar PINCTRL_PIN(241, "PLGPIO241"), \
45085ed41a7SViresh Kumar PINCTRL_PIN(242, "PLGPIO242"), \
45185ed41a7SViresh Kumar PINCTRL_PIN(243, "PLGPIO243"), \
45285ed41a7SViresh Kumar PINCTRL_PIN(244, "PLGPIO244"), \
45385ed41a7SViresh Kumar PINCTRL_PIN(245, "PLGPIO245")
45485ed41a7SViresh Kumar
455deda8287SViresh Kumar #endif /* __PINMUX_SPEAR_H__ */
456