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/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dmediatek-pcie-gen3.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/mediatek-pcie-gen3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Gen3 PCIe controller on MediaTek SoCs
10 - Jianjun Wang <jianjun.wang@mediatek.com>
13 PCIe Gen3 MAC controller for MediaTek SoCs, it supports Gen3 speed
16 This PCIe controller supports up to 256 MSI vectors, the MSI hardware
19 +-----+
21 +-----+
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dmediatek,net.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Bianconi <lorenzo@kernel.org>
11 - Felix Fietkau <nbd@nbd.name>
20 - mediatek,mt2701-eth
21 - mediatek,mt7623-eth
22 - mediatek,mt7621-eth
23 - mediatek,mt7622-eth
24 - mediatek,mt7629-eth
[all …]
/openbmc/u-boot/board/freescale/mpc8569mds/
H A DREADME2 --------
3 MPC8569MDS is composed of two boards - PB (Processor Board) and PIB (Platform
6 Building U-Boot
7 -----------
12 ----------
14 0xa000_0000 0xbfff_ffff PCIe MEM 512MB
16 0xe280_0000 0xe2ff_ffff PCIe I/O 8M
25 Flashing U-Boot Images
26 ---------------
28 Use the following commands to program U-Boot image into flash:
[all …]
/openbmc/linux/drivers/bcma/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
16 # Support for Block-I/O. SELECT this from the driver that needs it.
26 bool "Support for BCMA on PCI-host bus"
46 BCMA bus may have many versions of PCIe core. This driver
48 1) PCIe core working in clientmode
49 2) PCIe Gen 2 clientmode core
51 In general PCIe (Gen 2) clientmode core is required on PCIe
54 This driver is also prerequisite for a hostmode PCIe core
78 bool "ChipCommon-attached serial flash support"
95 bool "BCMA Broadcom GBIT MAC COMMON core driver"
[all …]
/openbmc/linux/drivers/net/ethernet/intel/fm10k/
H A Dfm10k_common.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2013 - 2018 Intel Corporation. */
7 * fm10k_get_bus_info_generic - Generic set PCI bus info
17 /* Get the maximum link width and speed from PCIe config space */ in fm10k_get_bus_info_generic()
22 hw->bus_caps.width = fm10k_bus_width_pcie_x1; in fm10k_get_bus_info_generic()
25 hw->bus_caps.width = fm10k_bus_width_pcie_x2; in fm10k_get_bus_info_generic()
28 hw->bus_caps.width = fm10k_bus_width_pcie_x4; in fm10k_get_bus_info_generic()
31 hw->bus_caps.width = fm10k_bus_width_pcie_x8; in fm10k_get_bus_info_generic()
34 hw->bus_caps.width = fm10k_bus_width_unknown; in fm10k_get_bus_info_generic()
40 hw->bus_caps.speed = fm10k_bus_speed_2500; in fm10k_get_bus_info_generic()
[all …]
H A Dfm10k_pci.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2013 - 2019 Intel Corporation. */
15 * fm10k_pci_tbl - PCI Device ID Table
35 struct fm10k_intfc *interface = hw->back; in fm10k_read_pci_cfg_word()
38 if (FM10K_REMOVED(hw->hw_addr)) in fm10k_read_pci_cfg_word()
41 pci_read_config_word(interface->pdev, reg, &value); in fm10k_read_pci_cfg_word()
50 u32 __iomem *hw_addr = READ_ONCE(hw->hw_addr); in fm10k_read_reg()
58 struct fm10k_intfc *interface = hw->back; in fm10k_read_reg()
59 struct net_device *netdev = interface->netdev; in fm10k_read_reg()
61 hw->hw_addr = NULL; in fm10k_read_reg()
[all …]
/openbmc/linux/arch/mips/boot/dts/ralink/
H A Dmt7621.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 #include <dt-bindings/interrupt-controller/mips-gic.h>
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/clock/mt7621-clk.h>
5 #include <dt-bindings/reset/mt7621-reset.h>
8 #address-cells = <1>;
9 #size-cells = <1>;
10 compatible = "mediatek,mt7621-soc";
13 #address-cells = <1>;
14 #size-cells = <0>;
[all …]
/openbmc/qemu/tests/qtest/
H A Dvirtio-net-failover.c2 * QTest testcase for virtio-net failover
4 * See docs/system/virtio-net-failover.rst
8 * SPDX-License-Identifier: GPL-2.0-or-later
13 #include "libqos/pci-pc.h"
14 #include "migration-helpers.h"
18 #include "libqos/malloc-pc.h"
19 #include "libqos/virtio-pci.h"
28 #define BASE_MACHINE "-M q35 -nodefaults " \
29 "-device pcie-root-port,id=root0,addr=0x1,bus=pcie.0,chassis=1 " \
30 "-device pcie-root-port,id=root1,addr=0x2,bus=pcie.0,chassis=2 "
[all …]
/openbmc/qemu/docs/system/
H A Dvirtio-net-failover.rst2 QEMU virtio-net standby (net_failover)
5 This document explains the setup and usage of virtio-net standby feature which
8 The general idea is that we have a pair of devices, a (vfio-)pci and a
9 virtio-net device. Before migration the vfio device is unplugged and data flows
10 through the virtio-net device, on the target side another vfio-pci device is
11 plugged in to take over the data-path. In the guest the net_failover kernel
12 module will pair net devices with the same MAC address.
15 networking device is called the primary device and the virtio-net device is the
19 ------------
21 Currently only PCIe devices are allowed as primary devices, this restriction
[all …]
/openbmc/linux/Documentation/networking/
H A Drepresentors.rst1 .. SPDX-License-Identifier: GPL-2.0
8 used to control internal switching on SmartNICs. For the closely-related port
9 representors on physical (multi-port) switches, see
13 ----------
15 Since the mid-2010s, network cards have started offering more complex
16 virtualisation capabilities than the legacy SR-IOV approach (with its simple
17 MAC/VLAN-based switching model) can support. This led to a desire to offload
18 software-defined networks (such as OpenVSwitch) to these NICs to specify the
23 virtual switches and IOV devices. Just as each physical port of a Linux-
41 -----------
[all …]
/openbmc/qemu/docs/system/ppc/
H A Dpowernv.rst4 PowerNV (as Non-Virtualized) is the "bare metal" platform using the
16 -----------------
23 * POWER8 PHB3 PCIe Host bridge and POWER9 PHB4 PCIe Host bridge.
24 * Simple OCC is an on-chip micro-controller used for power management tasks.
30 ---------------
36 * EEH support for PCIe Host bridge controllers.
44 --------
49 GitHub <https://github.com/open-power>`_.
52 `OpenPOWER <https://github.com/open-power/op-build/releases/>`__ site.
58 ---------------------------
[all …]
/openbmc/openbmc/meta-ibm/recipes-bsp/u-boot/u-boot-aspeed-sdk/p10bmc/
H A Dibm.json65 "Disable Auto Boot from VUART2 over PCIE": true,
84 "MAC 1 RMII mode": { "value": "RMII/NCSI" },
85 "MAC 2 RMII mode": { "value": "RMII/NCSI" },
94 "Enable PCIe EHCI": { "value": false },
97 "Enable dedicate PCIe RC reset": { "value": false },
101 "MAC 3 RMII mode": { "value": "RMII/NCSI" },
102 "MAC 4 RMII mode": { "value": "RMII/NCSI" },
110 "Enable boot SPI 3B address mode auto-clear": { "value": false },
H A Dips.json72 "Disable Auto Boot from VUART2 over PCIE": true,
91 "MAC 1 RMII mode": { "value": "RMII/NCSI" },
92 "MAC 2 RMII mode": { "value": "RMII/NCSI" },
101 "Enable PCIe EHCI": { "value": false },
104 "Enable dedicate PCIe RC reset": { "value": false },
108 "MAC 3 RMII mode": { "value": "RMII/NCSI" },
109 "MAC 4 RMII mode": { "value": "RMII/NCSI" },
117 "Enable boot SPI 3B address mode auto-clear": { "value": false },
/openbmc/linux/drivers/pci/controller/
H A Dpcie-mediatek-gen3.c1 // SPDX-License-Identifier: GPL-2.0
3 * MediaTek PCIe host controller driver.
61 #define PCIE_MSI_ENABLE GENMASK(PCIE_MSI_SET_NUM + 8 - 1, 8)
65 GENMASK(PCIE_INTX_SHIFT + PCI_NUM_INTX - 1, PCIE_INTX_SHIFT)
69 #define PCIE_MSI_SET_ENABLE GENMASK(PCIE_MSI_SET_NUM - 1, 0)
95 (((((size) - 1) << 1) & GENMASK(6, 1)) | PCIE_ATR_EN)
104 * struct mtk_msi_set - MSI information for each set
116 * struct mtk_gen3_pcie - PCIe port information
117 * @dev: pointer to PCIe device
120 * @mac_reset: MAC reset control
[all …]
/openbmc/u-boot/cmd/
H A Dotp_info.h7 #define OTP_REG_RESERVED -1
8 #define OTP_REG_VALUE -2
9 #define OTP_REG_VALID_BIT -3
43 { 5, 1, 0, "MAC 1 : RMII/NCSI" },
44 { 5, 1, 1, "MAC 1 : RGMII" },
45 { 6, 1, 0, "MAC 2 : RMII/NCSI" },
46 { 6, 1, 1, "MAC 2 : RGMII" },
69 { 20, 1, 0, "Disable Pcie EHCI device" },
70 { 20, 1, 1, "Enable Pcie EHCI device" },
74 { 22, 1, 1, "Disable dedicated BMC functions for non-BMC application" },
[all …]
/openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/
H A DREADME.soc13 ---------
14 The LS1043A integrated multicore processor combines four ARM Cortex-A53
20 - Four 64-bit ARM Cortex-A53 CPUs
21 - 1 MB unified L2 Cache
22 - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
24 - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
26 - Packet parsing, classification, and distribution (FMan)
27 - Queue management for scheduling, packet sequencing, and congestion
29 - Hardware buffer management for buffer allocation and de-allocation (BMan)
30 - Cryptography acceleration (SEC)
[all …]
/openbmc/linux/drivers/net/wireless/broadcom/brcm80211/brcmfmac/
H A Dfirmware.c1 // SPDX-License-Identifier: ISC
21 #define BRCMF_FW_NVRAM_DEVPATH_LEN 19 /* devpath0=pcie/1/4/ */
22 #define BRCMF_FW_NVRAM_PCIEDEV_LEN 10 /* pcie/1/4/ + \0 */
36 * struct nvram_parser - internal info for parser.
46 * @multi_dev_v1: detect pcie multi device v1 (compressed).
47 * @multi_dev_v2: detect pcie multi device v2.
49 * @strip_mac: strip the MAC address.
67 * is_nvram_char() - check if char is a valid one for NVRAM entry
91 c = nvp->data[nvp->pos]; in brcmf_nvram_handle_idle()
99 nvp->entry = nvp->pos; in brcmf_nvram_handle_idle()
[all …]
/openbmc/u-boot/board/freescale/t208xqds/
H A DREADME1 The T2080QDS is a high-performance computing evaluation, development and
5 ------------------
6 The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power
7 Architecture processor cores with high-performance datapath acceleration
12 - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz
13 - 2MB L2 cache and 512KB CoreNet platform cache (CPC)
14 - Hierarchical interconnect fabric
15 - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
16 - Data Path Acceleration Architecture (DPAA) incorporating acceleration
17 - 16 SerDes lanes up to 10.3125 GHz
[all …]
/openbmc/linux/arch/arm/boot/dts/mediatek/
H A Dmt7629-rfb.dts1 // SPDX-License-Identifier: GPL-2.0
7 /dts-v1/;
8 #include <dt-bindings/input/input.h>
13 compatible = "mediatek,mt7629-rfb", "mediatek,mt7629";
20 stdout-path = "serial0:115200n8";
23 gpio-keys {
24 compatible = "gpio-keys";
26 button-reset {
32 button-wps {
44 reg_3p3v: regulator-3p3v {
[all …]
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,sdx75-gcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sdx75-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Imran Shaik <quic_imrashai@quicinc.com>
11 - Taniya Das <quic_tdas@quicinc.com>
17 See also:: include/dt-bindings/clock/qcom,sdx75-gcc.h
21 const: qcom,sdx75-gcc
25 - description: Board XO source
26 - description: Sleep clock source
[all …]
H A Dmvebu-gated-clock.txt12 -----------------------------------
14 1 pex0_en PCIe 0 Clock out
15 2 pex1_en PCIe 1 Clock out
18 5 pex0 PCIe Cntrl 0
19 9 pex1 PCIe Cntrl 1
29 -----------------------------------
33 5 pex0 PCIe 0 Clock out
34 6 pex1 PCIe 1 Clock out
42 19 gop Gigabit Ethernet MAC
56 -----------------------------------
[all …]
/openbmc/linux/drivers/staging/rtl8712/
H A Dusb_halinit.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved.
29 struct registry_priv *registrypriv = &adapter->registrypriv; in r8712_usb_hal_bus_init()
31 if (registrypriv->chip_version == RTL8712_FPGA) { in r8712_usb_hal_bus_init()
57 /* isolate PCIe Analog 1.2V to PCIe 3.3V and PCIE Digital */ in r8712_usb_hal_bus_init()
61 /* attach AFE PLL to MACTOP/BB/PCIe Digital */ in r8712_usb_hal_bus_init()
76 /* enable MAC clock */ in r8712_usb_hal_bus_init()
96 /* consideration of power consumption - init */ in r8712_usb_hal_bus_init()
99 } else if (registrypriv->chip_version == RTL8712_1stCUT) { in r8712_usb_hal_bus_init()
132 /* Attach AFE PLL to MACTOP/BB/PCIe Digital */ in r8712_usb_hal_bus_init()
[all …]
/openbmc/linux/arch/arm64/boot/dts/apm/
H A Dapm-storm.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dts file for AppliedMicro (APM) X-Gene Storm SOC
9 compatible = "apm,xgene-storm";
10 interrupt-parent = <&gic>;
11 #address-cells = <2>;
12 #size-cells = <2>;
15 #address-cells = <2>;
16 #size-cells = <0>;
22 enable-method = "spin-table";
23 cpu-release-addr = <0x1 0x0000fff8>;
[all …]
/openbmc/linux/drivers/net/ethernet/atheros/atl1e/
H A Datl1e_hw.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
36 * 00-0B-6A-F6-00-DC in atl1e_hw_set_mac_addr()
40 value = (((u32)hw->mac_addr[2]) << 24) | in atl1e_hw_set_mac_addr()
41 (((u32)hw->mac_addr[3]) << 16) | in atl1e_hw_set_mac_addr()
42 (((u32)hw->mac_addr[4]) << 8) | in atl1e_hw_set_mac_addr()
43 (((u32)hw->mac_addr[5])) ; in atl1e_hw_set_mac_addr()
46 value = (((u32)hw->mac_addr[0]) << 8) | in atl1e_hw_set_mac_addr()
47 (((u32)hw->mac_addr[1])) ; in atl1e_hw_set_mac_addr()
53 * return 0 if get valid mac address,
[all …]
/openbmc/linux/drivers/net/ethernet/cavium/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
26 standalone PCIe NIC chip.
36 tristate "Thunder MAC interface driver (BGX)"
42 This driver supports programming and controlling of MAC
46 tristate "Thunder MAC interface driver (RGX)"
105 will be called liquidio_vf. MSI-X interrupt support is required

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