12874c5fdSThomas Gleixner// SPDX-License-Identifier: GPL-2.0-or-later 2ca5b3410SRobert Richter/* 3ca5b3410SRobert Richter * dts file for AppliedMicro (APM) X-Gene Storm SOC 4ca5b3410SRobert Richter * 5ca5b3410SRobert Richter * Copyright (C) 2013, Applied Micro Circuits Corporation 6ca5b3410SRobert Richter */ 7ca5b3410SRobert Richter 8ca5b3410SRobert Richter/ { 9ca5b3410SRobert Richter compatible = "apm,xgene-storm"; 10ca5b3410SRobert Richter interrupt-parent = <&gic>; 11ca5b3410SRobert Richter #address-cells = <2>; 12ca5b3410SRobert Richter #size-cells = <2>; 13ca5b3410SRobert Richter 14ca5b3410SRobert Richter cpus { 15ca5b3410SRobert Richter #address-cells = <2>; 16ca5b3410SRobert Richter #size-cells = <0>; 17ca5b3410SRobert Richter 18d8bcaabeSRob Herring cpu@0 { 19ca5b3410SRobert Richter device_type = "cpu"; 2031af04cdSRob Herring compatible = "apm,potenza"; 21ca5b3410SRobert Richter reg = <0x0 0x000>; 22ca5b3410SRobert Richter enable-method = "spin-table"; 23ca5b3410SRobert Richter cpu-release-addr = <0x1 0x0000fff8>; 248000bc3fSDuc Dang next-level-cache = <&xgene_L2_0>; 25ca5b3410SRobert Richter }; 26d8bcaabeSRob Herring cpu@1 { 27ca5b3410SRobert Richter device_type = "cpu"; 2831af04cdSRob Herring compatible = "apm,potenza"; 29ca5b3410SRobert Richter reg = <0x0 0x001>; 30ca5b3410SRobert Richter enable-method = "spin-table"; 31ca5b3410SRobert Richter cpu-release-addr = <0x1 0x0000fff8>; 328000bc3fSDuc Dang next-level-cache = <&xgene_L2_0>; 33ca5b3410SRobert Richter }; 34ca5b3410SRobert Richter cpu@100 { 35ca5b3410SRobert Richter device_type = "cpu"; 3631af04cdSRob Herring compatible = "apm,potenza"; 37ca5b3410SRobert Richter reg = <0x0 0x100>; 38ca5b3410SRobert Richter enable-method = "spin-table"; 39ca5b3410SRobert Richter cpu-release-addr = <0x1 0x0000fff8>; 408000bc3fSDuc Dang next-level-cache = <&xgene_L2_1>; 41ca5b3410SRobert Richter }; 42ca5b3410SRobert Richter cpu@101 { 43ca5b3410SRobert Richter device_type = "cpu"; 4431af04cdSRob Herring compatible = "apm,potenza"; 45ca5b3410SRobert Richter reg = <0x0 0x101>; 46ca5b3410SRobert Richter enable-method = "spin-table"; 47ca5b3410SRobert Richter cpu-release-addr = <0x1 0x0000fff8>; 488000bc3fSDuc Dang next-level-cache = <&xgene_L2_1>; 49ca5b3410SRobert Richter }; 50ca5b3410SRobert Richter cpu@200 { 51ca5b3410SRobert Richter device_type = "cpu"; 5231af04cdSRob Herring compatible = "apm,potenza"; 53ca5b3410SRobert Richter reg = <0x0 0x200>; 54ca5b3410SRobert Richter enable-method = "spin-table"; 55ca5b3410SRobert Richter cpu-release-addr = <0x1 0x0000fff8>; 568000bc3fSDuc Dang next-level-cache = <&xgene_L2_2>; 57ca5b3410SRobert Richter }; 58ca5b3410SRobert Richter cpu@201 { 59ca5b3410SRobert Richter device_type = "cpu"; 6031af04cdSRob Herring compatible = "apm,potenza"; 61ca5b3410SRobert Richter reg = <0x0 0x201>; 62ca5b3410SRobert Richter enable-method = "spin-table"; 63ca5b3410SRobert Richter cpu-release-addr = <0x1 0x0000fff8>; 648000bc3fSDuc Dang next-level-cache = <&xgene_L2_2>; 65ca5b3410SRobert Richter }; 66ca5b3410SRobert Richter cpu@300 { 67ca5b3410SRobert Richter device_type = "cpu"; 6831af04cdSRob Herring compatible = "apm,potenza"; 69ca5b3410SRobert Richter reg = <0x0 0x300>; 70ca5b3410SRobert Richter enable-method = "spin-table"; 71ca5b3410SRobert Richter cpu-release-addr = <0x1 0x0000fff8>; 728000bc3fSDuc Dang next-level-cache = <&xgene_L2_3>; 73ca5b3410SRobert Richter }; 74ca5b3410SRobert Richter cpu@301 { 75ca5b3410SRobert Richter device_type = "cpu"; 7631af04cdSRob Herring compatible = "apm,potenza"; 77ca5b3410SRobert Richter reg = <0x0 0x301>; 78ca5b3410SRobert Richter enable-method = "spin-table"; 79ca5b3410SRobert Richter cpu-release-addr = <0x1 0x0000fff8>; 808000bc3fSDuc Dang next-level-cache = <&xgene_L2_3>; 818000bc3fSDuc Dang }; 828000bc3fSDuc Dang xgene_L2_0: l2-cache-0 { 838000bc3fSDuc Dang compatible = "cache"; 84*0022cec7SKrzysztof Kozlowski cache-level = <2>; 85*0022cec7SKrzysztof Kozlowski cache-unified; 868000bc3fSDuc Dang }; 878000bc3fSDuc Dang xgene_L2_1: l2-cache-1 { 888000bc3fSDuc Dang compatible = "cache"; 89*0022cec7SKrzysztof Kozlowski cache-level = <2>; 90*0022cec7SKrzysztof Kozlowski cache-unified; 918000bc3fSDuc Dang }; 928000bc3fSDuc Dang xgene_L2_2: l2-cache-2 { 938000bc3fSDuc Dang compatible = "cache"; 94*0022cec7SKrzysztof Kozlowski cache-level = <2>; 95*0022cec7SKrzysztof Kozlowski cache-unified; 968000bc3fSDuc Dang }; 978000bc3fSDuc Dang xgene_L2_3: l2-cache-3 { 988000bc3fSDuc Dang compatible = "cache"; 99*0022cec7SKrzysztof Kozlowski cache-level = <2>; 100*0022cec7SKrzysztof Kozlowski cache-unified; 101ca5b3410SRobert Richter }; 102ca5b3410SRobert Richter }; 103ca5b3410SRobert Richter 104ca5b3410SRobert Richter gic: interrupt-controller@78010000 { 105ca5b3410SRobert Richter compatible = "arm,cortex-a15-gic"; 106ca5b3410SRobert Richter #interrupt-cells = <3>; 107ca5b3410SRobert Richter interrupt-controller; 108ca5b3410SRobert Richter reg = <0x0 0x78010000 0x0 0x1000>, /* GIC Dist */ 109ca5b3410SRobert Richter <0x0 0x78020000 0x0 0x1000>, /* GIC CPU */ 110ca5b3410SRobert Richter <0x0 0x78040000 0x0 0x2000>, /* GIC VCPU Control */ 111ca5b3410SRobert Richter <0x0 0x78060000 0x0 0x2000>; /* GIC VCPU */ 112ca5b3410SRobert Richter interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */ 113ca5b3410SRobert Richter }; 114ca5b3410SRobert Richter 115ca5b3410SRobert Richter timer { 116ca5b3410SRobert Richter compatible = "arm,armv8-timer"; 117f2a89d3bSMarc Zyngier interrupts = <1 0 0xff08>, /* Secure Phys IRQ */ 118f2a89d3bSMarc Zyngier <1 13 0xff08>, /* Non-secure Phys IRQ */ 119f2a89d3bSMarc Zyngier <1 14 0xff08>, /* Virt IRQ */ 120f2a89d3bSMarc Zyngier <1 15 0xff08>; /* Hyp IRQ */ 121ca5b3410SRobert Richter clock-frequency = <50000000>; 122ca5b3410SRobert Richter }; 123ca5b3410SRobert Richter 1247434f42bSFeng Kan pmu { 1257434f42bSFeng Kan compatible = "apm,potenza-pmu", "arm,armv8-pmuv3"; 1267434f42bSFeng Kan interrupts = <1 12 0xff04>; 1277434f42bSFeng Kan }; 1287434f42bSFeng Kan 129ca5b3410SRobert Richter soc { 130ca5b3410SRobert Richter compatible = "simple-bus"; 131ca5b3410SRobert Richter #address-cells = <2>; 132ca5b3410SRobert Richter #size-cells = <2>; 133ca5b3410SRobert Richter ranges; 13474e353e1SRameshwar Prasad Sahu dma-ranges = <0x0 0x0 0x0 0x0 0x400 0x0>; 135ca5b3410SRobert Richter 136ca5b3410SRobert Richter clocks { 137ca5b3410SRobert Richter #address-cells = <2>; 138ca5b3410SRobert Richter #size-cells = <2>; 139ca5b3410SRobert Richter ranges; 140ca5b3410SRobert Richter refclk: refclk { 141ca5b3410SRobert Richter compatible = "fixed-clock"; 142ca5b3410SRobert Richter #clock-cells = <1>; 143ca5b3410SRobert Richter clock-frequency = <100000000>; 144ca5b3410SRobert Richter clock-output-names = "refclk"; 145ca5b3410SRobert Richter }; 146ca5b3410SRobert Richter 147ca5b3410SRobert Richter pcppll: pcppll@17000100 { 148ca5b3410SRobert Richter compatible = "apm,xgene-pcppll-clock"; 149ca5b3410SRobert Richter #clock-cells = <1>; 150ca5b3410SRobert Richter clocks = <&refclk 0>; 151ca5b3410SRobert Richter clock-names = "pcppll"; 152ca5b3410SRobert Richter reg = <0x0 0x17000100 0x0 0x1000>; 153ca5b3410SRobert Richter clock-output-names = "pcppll"; 154ca5b3410SRobert Richter type = <0>; 155ca5b3410SRobert Richter }; 156ca5b3410SRobert Richter 157ca5b3410SRobert Richter socpll: socpll@17000120 { 158ca5b3410SRobert Richter compatible = "apm,xgene-socpll-clock"; 159ca5b3410SRobert Richter #clock-cells = <1>; 160ca5b3410SRobert Richter clocks = <&refclk 0>; 161ca5b3410SRobert Richter clock-names = "socpll"; 162ca5b3410SRobert Richter reg = <0x0 0x17000120 0x0 0x1000>; 163ca5b3410SRobert Richter clock-output-names = "socpll"; 164ca5b3410SRobert Richter type = <1>; 165ca5b3410SRobert Richter }; 166ca5b3410SRobert Richter 167ca5b3410SRobert Richter socplldiv2: socplldiv2 { 168ca5b3410SRobert Richter compatible = "fixed-factor-clock"; 169ca5b3410SRobert Richter #clock-cells = <1>; 170ca5b3410SRobert Richter clocks = <&socpll 0>; 171ca5b3410SRobert Richter clock-names = "socplldiv2"; 172ca5b3410SRobert Richter clock-mult = <1>; 173ca5b3410SRobert Richter clock-div = <2>; 174ca5b3410SRobert Richter clock-output-names = "socplldiv2"; 175ca5b3410SRobert Richter }; 176ca5b3410SRobert Richter 177b0e7a85aSDuc Dang ahbclk: ahbclk@17000000 { 1788f74e861SSuman Tripathi compatible = "apm,xgene-device-clock"; 1798f74e861SSuman Tripathi #clock-cells = <1>; 1808f74e861SSuman Tripathi clocks = <&socplldiv2 0>; 181b0e7a85aSDuc Dang reg = <0x0 0x17000000 0x0 0x2000>; 182b0e7a85aSDuc Dang reg-names = "div-reg"; 1838f74e861SSuman Tripathi divider-offset = <0x164>; 1848f74e861SSuman Tripathi divider-width = <0x5>; 1858f74e861SSuman Tripathi divider-shift = <0x0>; 1868f74e861SSuman Tripathi clock-output-names = "ahbclk"; 1878f74e861SSuman Tripathi }; 1888f74e861SSuman Tripathi 1898f74e861SSuman Tripathi sdioclk: sdioclk@1f2ac000 { 1908f74e861SSuman Tripathi compatible = "apm,xgene-device-clock"; 1918f74e861SSuman Tripathi #clock-cells = <1>; 1928f74e861SSuman Tripathi clocks = <&socplldiv2 0>; 1938f74e861SSuman Tripathi reg = <0x0 0x1f2ac000 0x0 0x1000 1948f74e861SSuman Tripathi 0x0 0x17000000 0x0 0x2000>; 1958f74e861SSuman Tripathi reg-names = "csr-reg", "div-reg"; 1968f74e861SSuman Tripathi csr-offset = <0x0>; 1978f74e861SSuman Tripathi csr-mask = <0x2>; 1988f74e861SSuman Tripathi enable-offset = <0x8>; 1998f74e861SSuman Tripathi enable-mask = <0x2>; 2008f74e861SSuman Tripathi divider-offset = <0x178>; 2018f74e861SSuman Tripathi divider-width = <0x8>; 2028f74e861SSuman Tripathi divider-shift = <0x0>; 2038f74e861SSuman Tripathi clock-output-names = "sdioclk"; 2048f74e861SSuman Tripathi }; 2058f74e861SSuman Tripathi 206ca5b3410SRobert Richter ethclk: ethclk { 207ca5b3410SRobert Richter compatible = "apm,xgene-device-clock"; 208ca5b3410SRobert Richter #clock-cells = <1>; 209ca5b3410SRobert Richter clocks = <&socplldiv2 0>; 210ca5b3410SRobert Richter clock-names = "ethclk"; 211ca5b3410SRobert Richter reg = <0x0 0x17000000 0x0 0x1000>; 212ca5b3410SRobert Richter reg-names = "div-reg"; 213ca5b3410SRobert Richter divider-offset = <0x238>; 214ca5b3410SRobert Richter divider-width = <0x9>; 215ca5b3410SRobert Richter divider-shift = <0x0>; 216ca5b3410SRobert Richter clock-output-names = "ethclk"; 217ca5b3410SRobert Richter }; 218ca5b3410SRobert Richter 219ca5b3410SRobert Richter menetclk: menetclk { 220ca5b3410SRobert Richter compatible = "apm,xgene-device-clock"; 221ca5b3410SRobert Richter #clock-cells = <1>; 222ca5b3410SRobert Richter clocks = <ðclk 0>; 223cafc4cd0SBjorn Helgaas reg = <0x0 0x1702c000 0x0 0x1000>; 224ca5b3410SRobert Richter reg-names = "csr-reg"; 225ca5b3410SRobert Richter clock-output-names = "menetclk"; 226ca5b3410SRobert Richter }; 227ca5b3410SRobert Richter 228ca5b3410SRobert Richter sge0clk: sge0clk@1f21c000 { 229ca5b3410SRobert Richter compatible = "apm,xgene-device-clock"; 230ca5b3410SRobert Richter #clock-cells = <1>; 231ca5b3410SRobert Richter clocks = <&socplldiv2 0>; 232ca5b3410SRobert Richter reg = <0x0 0x1f21c000 0x0 0x1000>; 233ca5b3410SRobert Richter reg-names = "csr-reg"; 2348e694cd2SIyappan Subramanian csr-mask = <0xa>; 2358e694cd2SIyappan Subramanian enable-mask = <0xf>; 236ca5b3410SRobert Richter clock-output-names = "sge0clk"; 237ca5b3410SRobert Richter }; 238ca5b3410SRobert Richter 239ca5b3410SRobert Richter xge0clk: xge0clk@1f61c000 { 240ca5b3410SRobert Richter compatible = "apm,xgene-device-clock"; 241ca5b3410SRobert Richter #clock-cells = <1>; 242ca5b3410SRobert Richter clocks = <&socplldiv2 0>; 243ca5b3410SRobert Richter reg = <0x0 0x1f61c000 0x0 0x1000>; 244ca5b3410SRobert Richter reg-names = "csr-reg"; 245ca5b3410SRobert Richter csr-mask = <0x3>; 246ca5b3410SRobert Richter clock-output-names = "xge0clk"; 247ca5b3410SRobert Richter }; 248ca5b3410SRobert Richter 249e63c7a09SIyappan Subramanian xge1clk: xge1clk@1f62c000 { 250e63c7a09SIyappan Subramanian compatible = "apm,xgene-device-clock"; 251e63c7a09SIyappan Subramanian status = "disabled"; 252e63c7a09SIyappan Subramanian #clock-cells = <1>; 253e63c7a09SIyappan Subramanian clocks = <&socplldiv2 0>; 254e63c7a09SIyappan Subramanian reg = <0x0 0x1f62c000 0x0 0x1000>; 255e63c7a09SIyappan Subramanian reg-names = "csr-reg"; 256e63c7a09SIyappan Subramanian csr-mask = <0x3>; 257e63c7a09SIyappan Subramanian clock-output-names = "xge1clk"; 258e63c7a09SIyappan Subramanian }; 259e63c7a09SIyappan Subramanian 260ca5b3410SRobert Richter sataphy1clk: sataphy1clk@1f21c000 { 261ca5b3410SRobert Richter compatible = "apm,xgene-device-clock"; 262ca5b3410SRobert Richter #clock-cells = <1>; 263ca5b3410SRobert Richter clocks = <&socplldiv2 0>; 264ca5b3410SRobert Richter reg = <0x0 0x1f21c000 0x0 0x1000>; 265ca5b3410SRobert Richter reg-names = "csr-reg"; 266ca5b3410SRobert Richter clock-output-names = "sataphy1clk"; 267ca5b3410SRobert Richter status = "disabled"; 268ca5b3410SRobert Richter csr-offset = <0x4>; 269ca5b3410SRobert Richter csr-mask = <0x00>; 270ca5b3410SRobert Richter enable-offset = <0x0>; 271ca5b3410SRobert Richter enable-mask = <0x06>; 272ca5b3410SRobert Richter }; 273ca5b3410SRobert Richter 274ca5b3410SRobert Richter sataphy2clk: sataphy1clk@1f22c000 { 275ca5b3410SRobert Richter compatible = "apm,xgene-device-clock"; 276ca5b3410SRobert Richter #clock-cells = <1>; 277ca5b3410SRobert Richter clocks = <&socplldiv2 0>; 278ca5b3410SRobert Richter reg = <0x0 0x1f22c000 0x0 0x1000>; 279ca5b3410SRobert Richter reg-names = "csr-reg"; 280ca5b3410SRobert Richter clock-output-names = "sataphy2clk"; 2812f308657SKrzysztof Kozlowski status = "okay"; 282ca5b3410SRobert Richter csr-offset = <0x4>; 283ca5b3410SRobert Richter csr-mask = <0x3a>; 284ca5b3410SRobert Richter enable-offset = <0x0>; 285ca5b3410SRobert Richter enable-mask = <0x06>; 286ca5b3410SRobert Richter }; 287ca5b3410SRobert Richter 288ca5b3410SRobert Richter sataphy3clk: sataphy1clk@1f23c000 { 289ca5b3410SRobert Richter compatible = "apm,xgene-device-clock"; 290ca5b3410SRobert Richter #clock-cells = <1>; 291ca5b3410SRobert Richter clocks = <&socplldiv2 0>; 292ca5b3410SRobert Richter reg = <0x0 0x1f23c000 0x0 0x1000>; 293ca5b3410SRobert Richter reg-names = "csr-reg"; 294ca5b3410SRobert Richter clock-output-names = "sataphy3clk"; 2952f308657SKrzysztof Kozlowski status = "okay"; 296ca5b3410SRobert Richter csr-offset = <0x4>; 297ca5b3410SRobert Richter csr-mask = <0x3a>; 298ca5b3410SRobert Richter enable-offset = <0x0>; 299ca5b3410SRobert Richter enable-mask = <0x06>; 300ca5b3410SRobert Richter }; 301ca5b3410SRobert Richter 302ca5b3410SRobert Richter sata01clk: sata01clk@1f21c000 { 303ca5b3410SRobert Richter compatible = "apm,xgene-device-clock"; 304ca5b3410SRobert Richter #clock-cells = <1>; 305ca5b3410SRobert Richter clocks = <&socplldiv2 0>; 306ca5b3410SRobert Richter reg = <0x0 0x1f21c000 0x0 0x1000>; 307ca5b3410SRobert Richter reg-names = "csr-reg"; 308ca5b3410SRobert Richter clock-output-names = "sata01clk"; 309ca5b3410SRobert Richter csr-offset = <0x4>; 310ca5b3410SRobert Richter csr-mask = <0x05>; 311ca5b3410SRobert Richter enable-offset = <0x0>; 312ca5b3410SRobert Richter enable-mask = <0x39>; 313ca5b3410SRobert Richter }; 314ca5b3410SRobert Richter 315ca5b3410SRobert Richter sata23clk: sata23clk@1f22c000 { 316ca5b3410SRobert Richter compatible = "apm,xgene-device-clock"; 317ca5b3410SRobert Richter #clock-cells = <1>; 318ca5b3410SRobert Richter clocks = <&socplldiv2 0>; 319ca5b3410SRobert Richter reg = <0x0 0x1f22c000 0x0 0x1000>; 320ca5b3410SRobert Richter reg-names = "csr-reg"; 321ca5b3410SRobert Richter clock-output-names = "sata23clk"; 322ca5b3410SRobert Richter csr-offset = <0x4>; 323ca5b3410SRobert Richter csr-mask = <0x05>; 324ca5b3410SRobert Richter enable-offset = <0x0>; 325ca5b3410SRobert Richter enable-mask = <0x39>; 326ca5b3410SRobert Richter }; 327ca5b3410SRobert Richter 328ca5b3410SRobert Richter sata45clk: sata45clk@1f23c000 { 329ca5b3410SRobert Richter compatible = "apm,xgene-device-clock"; 330ca5b3410SRobert Richter #clock-cells = <1>; 331ca5b3410SRobert Richter clocks = <&socplldiv2 0>; 332ca5b3410SRobert Richter reg = <0x0 0x1f23c000 0x0 0x1000>; 333ca5b3410SRobert Richter reg-names = "csr-reg"; 334ca5b3410SRobert Richter clock-output-names = "sata45clk"; 335ca5b3410SRobert Richter csr-offset = <0x4>; 336ca5b3410SRobert Richter csr-mask = <0x05>; 337ca5b3410SRobert Richter enable-offset = <0x0>; 338ca5b3410SRobert Richter enable-mask = <0x39>; 339ca5b3410SRobert Richter }; 340ca5b3410SRobert Richter 341ca5b3410SRobert Richter rtcclk: rtcclk@17000000 { 342ca5b3410SRobert Richter compatible = "apm,xgene-device-clock"; 343ca5b3410SRobert Richter #clock-cells = <1>; 344ca5b3410SRobert Richter clocks = <&socplldiv2 0>; 345ca5b3410SRobert Richter reg = <0x0 0x17000000 0x0 0x2000>; 346ca5b3410SRobert Richter reg-names = "csr-reg"; 347ca5b3410SRobert Richter csr-offset = <0xc>; 348ca5b3410SRobert Richter csr-mask = <0x2>; 349ca5b3410SRobert Richter enable-offset = <0x10>; 350ca5b3410SRobert Richter enable-mask = <0x2>; 351ca5b3410SRobert Richter clock-output-names = "rtcclk"; 352ca5b3410SRobert Richter }; 353ca5b3410SRobert Richter 354ca5b3410SRobert Richter rngpkaclk: rngpkaclk@17000000 { 355ca5b3410SRobert Richter compatible = "apm,xgene-device-clock"; 356ca5b3410SRobert Richter #clock-cells = <1>; 357ca5b3410SRobert Richter clocks = <&socplldiv2 0>; 358ca5b3410SRobert Richter reg = <0x0 0x17000000 0x0 0x2000>; 359ca5b3410SRobert Richter reg-names = "csr-reg"; 360ca5b3410SRobert Richter csr-offset = <0xc>; 361ca5b3410SRobert Richter csr-mask = <0x10>; 362ca5b3410SRobert Richter enable-offset = <0x10>; 363ca5b3410SRobert Richter enable-mask = <0x10>; 364ca5b3410SRobert Richter clock-output-names = "rngpkaclk"; 365ca5b3410SRobert Richter }; 366ca5b3410SRobert Richter 367ca5b3410SRobert Richter pcie0clk: pcie0clk@1f2bc000 { 368ca5b3410SRobert Richter status = "disabled"; 369ca5b3410SRobert Richter compatible = "apm,xgene-device-clock"; 370ca5b3410SRobert Richter #clock-cells = <1>; 371ca5b3410SRobert Richter clocks = <&socplldiv2 0>; 372ca5b3410SRobert Richter reg = <0x0 0x1f2bc000 0x0 0x1000>; 373ca5b3410SRobert Richter reg-names = "csr-reg"; 374ca5b3410SRobert Richter clock-output-names = "pcie0clk"; 375ca5b3410SRobert Richter }; 376ca5b3410SRobert Richter 377ca5b3410SRobert Richter pcie1clk: pcie1clk@1f2cc000 { 378ca5b3410SRobert Richter status = "disabled"; 379ca5b3410SRobert Richter compatible = "apm,xgene-device-clock"; 380ca5b3410SRobert Richter #clock-cells = <1>; 381ca5b3410SRobert Richter clocks = <&socplldiv2 0>; 382ca5b3410SRobert Richter reg = <0x0 0x1f2cc000 0x0 0x1000>; 383ca5b3410SRobert Richter reg-names = "csr-reg"; 384ca5b3410SRobert Richter clock-output-names = "pcie1clk"; 385ca5b3410SRobert Richter }; 386ca5b3410SRobert Richter 387ca5b3410SRobert Richter pcie2clk: pcie2clk@1f2dc000 { 388ca5b3410SRobert Richter status = "disabled"; 389ca5b3410SRobert Richter compatible = "apm,xgene-device-clock"; 390ca5b3410SRobert Richter #clock-cells = <1>; 391ca5b3410SRobert Richter clocks = <&socplldiv2 0>; 392ca5b3410SRobert Richter reg = <0x0 0x1f2dc000 0x0 0x1000>; 393ca5b3410SRobert Richter reg-names = "csr-reg"; 394ca5b3410SRobert Richter clock-output-names = "pcie2clk"; 395ca5b3410SRobert Richter }; 396ca5b3410SRobert Richter 397ca5b3410SRobert Richter pcie3clk: pcie3clk@1f50c000 { 398ca5b3410SRobert Richter status = "disabled"; 399ca5b3410SRobert Richter compatible = "apm,xgene-device-clock"; 400ca5b3410SRobert Richter #clock-cells = <1>; 401ca5b3410SRobert Richter clocks = <&socplldiv2 0>; 402ca5b3410SRobert Richter reg = <0x0 0x1f50c000 0x0 0x1000>; 403ca5b3410SRobert Richter reg-names = "csr-reg"; 404ca5b3410SRobert Richter clock-output-names = "pcie3clk"; 405ca5b3410SRobert Richter }; 406ca5b3410SRobert Richter 407ca5b3410SRobert Richter pcie4clk: pcie4clk@1f51c000 { 408ca5b3410SRobert Richter status = "disabled"; 409ca5b3410SRobert Richter compatible = "apm,xgene-device-clock"; 410ca5b3410SRobert Richter #clock-cells = <1>; 411ca5b3410SRobert Richter clocks = <&socplldiv2 0>; 412ca5b3410SRobert Richter reg = <0x0 0x1f51c000 0x0 0x1000>; 413ca5b3410SRobert Richter reg-names = "csr-reg"; 414ca5b3410SRobert Richter clock-output-names = "pcie4clk"; 415ca5b3410SRobert Richter }; 41674e353e1SRameshwar Prasad Sahu 41774e353e1SRameshwar Prasad Sahu dmaclk: dmaclk@1f27c000 { 41874e353e1SRameshwar Prasad Sahu compatible = "apm,xgene-device-clock"; 41974e353e1SRameshwar Prasad Sahu #clock-cells = <1>; 42074e353e1SRameshwar Prasad Sahu clocks = <&socplldiv2 0>; 42174e353e1SRameshwar Prasad Sahu reg = <0x0 0x1f27c000 0x0 0x1000>; 42274e353e1SRameshwar Prasad Sahu reg-names = "csr-reg"; 42374e353e1SRameshwar Prasad Sahu clock-output-names = "dmaclk"; 42474e353e1SRameshwar Prasad Sahu }; 425ca5b3410SRobert Richter }; 426ca5b3410SRobert Richter 427e1e6e5c4SDuc Dang msi: msi@79000000 { 428e1e6e5c4SDuc Dang compatible = "apm,xgene1-msi"; 429e1e6e5c4SDuc Dang msi-controller; 430e1e6e5c4SDuc Dang reg = <0x00 0x79000000 0x0 0x900000>; 431e1e6e5c4SDuc Dang interrupts = < 0x0 0x10 0x4 432e1e6e5c4SDuc Dang 0x0 0x11 0x4 433e1e6e5c4SDuc Dang 0x0 0x12 0x4 434e1e6e5c4SDuc Dang 0x0 0x13 0x4 435e1e6e5c4SDuc Dang 0x0 0x14 0x4 436e1e6e5c4SDuc Dang 0x0 0x15 0x4 437e1e6e5c4SDuc Dang 0x0 0x16 0x4 438e1e6e5c4SDuc Dang 0x0 0x17 0x4 439e1e6e5c4SDuc Dang 0x0 0x18 0x4 440e1e6e5c4SDuc Dang 0x0 0x19 0x4 441e1e6e5c4SDuc Dang 0x0 0x1a 0x4 442e1e6e5c4SDuc Dang 0x0 0x1b 0x4 443e1e6e5c4SDuc Dang 0x0 0x1c 0x4 444e1e6e5c4SDuc Dang 0x0 0x1d 0x4 445e1e6e5c4SDuc Dang 0x0 0x1e 0x4 446e1e6e5c4SDuc Dang 0x0 0x1f 0x4>; 447e1e6e5c4SDuc Dang }; 448e1e6e5c4SDuc Dang 4495c3a87e3SFeng Kan scu: system-clk-controller@17000000 { 4505c3a87e3SFeng Kan compatible = "apm,xgene-scu","syscon"; 4515c3a87e3SFeng Kan reg = <0x0 0x17000000 0x0 0x400>; 4525c3a87e3SFeng Kan }; 4535c3a87e3SFeng Kan 4545c3a87e3SFeng Kan reboot: reboot@17000014 { 4555c3a87e3SFeng Kan compatible = "syscon-reboot"; 4565c3a87e3SFeng Kan regmap = <&scu>; 4575c3a87e3SFeng Kan offset = <0x14>; 4585c3a87e3SFeng Kan mask = <0x1>; 4595c3a87e3SFeng Kan }; 4605c3a87e3SFeng Kan 4618f2ae6f3SLoc Ho csw: csw@7e200000 { 4628f2ae6f3SLoc Ho compatible = "apm,xgene-csw", "syscon"; 4638f2ae6f3SLoc Ho reg = <0x0 0x7e200000 0x0 0x1000>; 4648f2ae6f3SLoc Ho }; 4658f2ae6f3SLoc Ho 4668f2ae6f3SLoc Ho mcba: mcba@7e700000 { 4678f2ae6f3SLoc Ho compatible = "apm,xgene-mcb", "syscon"; 4688f2ae6f3SLoc Ho reg = <0x0 0x7e700000 0x0 0x1000>; 4698f2ae6f3SLoc Ho }; 4708f2ae6f3SLoc Ho 4718f2ae6f3SLoc Ho mcbb: mcbb@7e720000 { 4728f2ae6f3SLoc Ho compatible = "apm,xgene-mcb", "syscon"; 4738f2ae6f3SLoc Ho reg = <0x0 0x7e720000 0x0 0x1000>; 4748f2ae6f3SLoc Ho }; 4758f2ae6f3SLoc Ho 4768f2ae6f3SLoc Ho efuse: efuse@1054a000 { 4778f2ae6f3SLoc Ho compatible = "apm,xgene-efuse", "syscon"; 4788f2ae6f3SLoc Ho reg = <0x0 0x1054a000 0x0 0x20>; 4798f2ae6f3SLoc Ho }; 4808f2ae6f3SLoc Ho 481f5793c97SLoc Ho rb: rb@7e000000 { 482f5793c97SLoc Ho compatible = "apm,xgene-rb", "syscon"; 483f5793c97SLoc Ho reg = <0x0 0x7e000000 0x0 0x10>; 484f5793c97SLoc Ho }; 485f5793c97SLoc Ho 4868f2ae6f3SLoc Ho edac@78800000 { 4878f2ae6f3SLoc Ho compatible = "apm,xgene-edac"; 4888f2ae6f3SLoc Ho #address-cells = <2>; 4898f2ae6f3SLoc Ho #size-cells = <2>; 4908f2ae6f3SLoc Ho ranges; 4918f2ae6f3SLoc Ho regmap-csw = <&csw>; 4928f2ae6f3SLoc Ho regmap-mcba = <&mcba>; 4938f2ae6f3SLoc Ho regmap-mcbb = <&mcbb>; 4948f2ae6f3SLoc Ho regmap-efuse = <&efuse>; 495f5793c97SLoc Ho regmap-rb = <&rb>; 4968f2ae6f3SLoc Ho reg = <0x0 0x78800000 0x0 0x100>; 4978f2ae6f3SLoc Ho interrupts = <0x0 0x20 0x4>, 4988f2ae6f3SLoc Ho <0x0 0x21 0x4>, 4998f2ae6f3SLoc Ho <0x0 0x27 0x4>; 5008f2ae6f3SLoc Ho 5018f2ae6f3SLoc Ho edacmc@7e800000 { 5028f2ae6f3SLoc Ho compatible = "apm,xgene-edac-mc"; 5038f2ae6f3SLoc Ho reg = <0x0 0x7e800000 0x0 0x1000>; 5048f2ae6f3SLoc Ho memory-controller = <0>; 5058f2ae6f3SLoc Ho }; 5068f2ae6f3SLoc Ho 5078f2ae6f3SLoc Ho edacmc@7e840000 { 5088f2ae6f3SLoc Ho compatible = "apm,xgene-edac-mc"; 5098f2ae6f3SLoc Ho reg = <0x0 0x7e840000 0x0 0x1000>; 5108f2ae6f3SLoc Ho memory-controller = <1>; 5118f2ae6f3SLoc Ho }; 5128f2ae6f3SLoc Ho 5138f2ae6f3SLoc Ho edacmc@7e880000 { 5148f2ae6f3SLoc Ho compatible = "apm,xgene-edac-mc"; 5158f2ae6f3SLoc Ho reg = <0x0 0x7e880000 0x0 0x1000>; 5168f2ae6f3SLoc Ho memory-controller = <2>; 5178f2ae6f3SLoc Ho }; 5188f2ae6f3SLoc Ho 5198f2ae6f3SLoc Ho edacmc@7e8c0000 { 5208f2ae6f3SLoc Ho compatible = "apm,xgene-edac-mc"; 5218f2ae6f3SLoc Ho reg = <0x0 0x7e8c0000 0x0 0x1000>; 5228f2ae6f3SLoc Ho memory-controller = <3>; 5238f2ae6f3SLoc Ho }; 5248f2ae6f3SLoc Ho 5258f2ae6f3SLoc Ho edacpmd@7c000000 { 5268f2ae6f3SLoc Ho compatible = "apm,xgene-edac-pmd"; 5278f2ae6f3SLoc Ho reg = <0x0 0x7c000000 0x0 0x200000>; 5288f2ae6f3SLoc Ho pmd-controller = <0>; 5298f2ae6f3SLoc Ho }; 5308f2ae6f3SLoc Ho 5318f2ae6f3SLoc Ho edacpmd@7c200000 { 5328f2ae6f3SLoc Ho compatible = "apm,xgene-edac-pmd"; 5338f2ae6f3SLoc Ho reg = <0x0 0x7c200000 0x0 0x200000>; 5348f2ae6f3SLoc Ho pmd-controller = <1>; 5358f2ae6f3SLoc Ho }; 5368f2ae6f3SLoc Ho 5378f2ae6f3SLoc Ho edacpmd@7c400000 { 5388f2ae6f3SLoc Ho compatible = "apm,xgene-edac-pmd"; 5398f2ae6f3SLoc Ho reg = <0x0 0x7c400000 0x0 0x200000>; 5408f2ae6f3SLoc Ho pmd-controller = <2>; 5418f2ae6f3SLoc Ho }; 5428f2ae6f3SLoc Ho 5438f2ae6f3SLoc Ho edacpmd@7c600000 { 5448f2ae6f3SLoc Ho compatible = "apm,xgene-edac-pmd"; 5458f2ae6f3SLoc Ho reg = <0x0 0x7c600000 0x0 0x200000>; 5468f2ae6f3SLoc Ho pmd-controller = <3>; 5478f2ae6f3SLoc Ho }; 548043cba96SLoc Ho 549043cba96SLoc Ho edacl3@7e600000 { 550043cba96SLoc Ho compatible = "apm,xgene-edac-l3"; 551043cba96SLoc Ho reg = <0x0 0x7e600000 0x0 0x1000>; 552043cba96SLoc Ho }; 553043cba96SLoc Ho 554043cba96SLoc Ho edacsoc@7e930000 { 555043cba96SLoc Ho compatible = "apm,xgene-edac-soc-v1"; 556043cba96SLoc Ho reg = <0x0 0x7e930000 0x0 0x1000>; 557043cba96SLoc Ho }; 5588f2ae6f3SLoc Ho }; 5598f2ae6f3SLoc Ho 5600317cd52STai Nguyen pmu: pmu@78810000 { 5610317cd52STai Nguyen compatible = "apm,xgene-pmu-v2"; 5620317cd52STai Nguyen #address-cells = <2>; 5630317cd52STai Nguyen #size-cells = <2>; 5640317cd52STai Nguyen ranges; 5650317cd52STai Nguyen regmap-csw = <&csw>; 5660317cd52STai Nguyen regmap-mcba = <&mcba>; 5670317cd52STai Nguyen regmap-mcbb = <&mcbb>; 5680317cd52STai Nguyen reg = <0x0 0x78810000 0x0 0x1000>; 5690317cd52STai Nguyen interrupts = <0x0 0x22 0x4>; 5700317cd52STai Nguyen 5710317cd52STai Nguyen pmul3c@7e610000 { 5720317cd52STai Nguyen compatible = "apm,xgene-pmu-l3c"; 5730317cd52STai Nguyen reg = <0x0 0x7e610000 0x0 0x1000>; 5740317cd52STai Nguyen }; 5750317cd52STai Nguyen 5760317cd52STai Nguyen pmuiob@7e940000 { 5770317cd52STai Nguyen compatible = "apm,xgene-pmu-iob"; 5780317cd52STai Nguyen reg = <0x0 0x7e940000 0x0 0x1000>; 5790317cd52STai Nguyen }; 5800317cd52STai Nguyen 5810317cd52STai Nguyen pmucmcb@7e710000 { 5820317cd52STai Nguyen compatible = "apm,xgene-pmu-mcb"; 5830317cd52STai Nguyen reg = <0x0 0x7e710000 0x0 0x1000>; 5840317cd52STai Nguyen enable-bit-index = <0>; 5850317cd52STai Nguyen }; 5860317cd52STai Nguyen 5870317cd52STai Nguyen pmucmcb@7e730000 { 5880317cd52STai Nguyen compatible = "apm,xgene-pmu-mcb"; 5890317cd52STai Nguyen reg = <0x0 0x7e730000 0x0 0x1000>; 5900317cd52STai Nguyen enable-bit-index = <1>; 5910317cd52STai Nguyen }; 5920317cd52STai Nguyen 5930317cd52STai Nguyen pmucmc@7e810000 { 5940317cd52STai Nguyen compatible = "apm,xgene-pmu-mc"; 5950317cd52STai Nguyen reg = <0x0 0x7e810000 0x0 0x1000>; 5960317cd52STai Nguyen enable-bit-index = <0>; 5970317cd52STai Nguyen }; 5980317cd52STai Nguyen 5990317cd52STai Nguyen pmucmc@7e850000 { 6000317cd52STai Nguyen compatible = "apm,xgene-pmu-mc"; 6010317cd52STai Nguyen reg = <0x0 0x7e850000 0x0 0x1000>; 6020317cd52STai Nguyen enable-bit-index = <1>; 6030317cd52STai Nguyen }; 6040317cd52STai Nguyen 6050317cd52STai Nguyen pmucmc@7e890000 { 6060317cd52STai Nguyen compatible = "apm,xgene-pmu-mc"; 6070317cd52STai Nguyen reg = <0x0 0x7e890000 0x0 0x1000>; 6080317cd52STai Nguyen enable-bit-index = <2>; 6090317cd52STai Nguyen }; 6100317cd52STai Nguyen 6110317cd52STai Nguyen pmucmc@7e8d0000 { 6120317cd52STai Nguyen compatible = "apm,xgene-pmu-mc"; 6130317cd52STai Nguyen reg = <0x0 0x7e8d0000 0x0 0x1000>; 6140317cd52STai Nguyen enable-bit-index = <3>; 6150317cd52STai Nguyen }; 6160317cd52STai Nguyen }; 6170317cd52STai Nguyen 618ca5b3410SRobert Richter pcie0: pcie@1f2b0000 { 619ca5b3410SRobert Richter status = "disabled"; 620ca5b3410SRobert Richter device_type = "pci"; 621ca5b3410SRobert Richter compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; 622ca5b3410SRobert Richter #interrupt-cells = <1>; 623ca5b3410SRobert Richter #size-cells = <2>; 624ca5b3410SRobert Richter #address-cells = <3>; 625ca5b3410SRobert Richter reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */ 626ca5b3410SRobert Richter 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */ 627ca5b3410SRobert Richter reg-names = "csr", "cfg"; 628ca5b3410SRobert Richter ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */ 62980bb3edaSDuc Dang 0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000 /* mem */ 63080bb3edaSDuc Dang 0x43000000 0xf0 0x00000000 0xf0 0x00000000 0x10 0x00000000>; /* mem */ 631ca5b3410SRobert Richter dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 632ca5b3410SRobert Richter 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; 6336b5fc336SRob Herring bus-range = <0x00 0xff>; 634ca5b3410SRobert Richter interrupt-map-mask = <0x0 0x0 0x0 0x7>; 6357c7b08bfSDuc Dang interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x4 6367c7b08bfSDuc Dang 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x4 6377c7b08bfSDuc Dang 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x4 6387c7b08bfSDuc Dang 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x4>; 639ca5b3410SRobert Richter dma-coherent; 640ca5b3410SRobert Richter clocks = <&pcie0clk 0>; 641e1e6e5c4SDuc Dang msi-parent = <&msi>; 642ca5b3410SRobert Richter }; 643ca5b3410SRobert Richter 644ca5b3410SRobert Richter pcie1: pcie@1f2c0000 { 645ca5b3410SRobert Richter status = "disabled"; 646ca5b3410SRobert Richter device_type = "pci"; 647ca5b3410SRobert Richter compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; 648ca5b3410SRobert Richter #interrupt-cells = <1>; 649ca5b3410SRobert Richter #size-cells = <2>; 650ca5b3410SRobert Richter #address-cells = <3>; 651ca5b3410SRobert Richter reg = < 0x00 0x1f2c0000 0x0 0x00010000 /* Controller registers */ 652ca5b3410SRobert Richter 0xd0 0xd0000000 0x0 0x00040000>; /* PCI config space */ 653ca5b3410SRobert Richter reg-names = "csr", "cfg"; 65480bb3edaSDuc Dang ranges = <0x01000000 0x00 0x00000000 0xd0 0x10000000 0x00 0x00010000 /* io */ 65580bb3edaSDuc Dang 0x02000000 0x00 0x80000000 0xd1 0x80000000 0x00 0x80000000 /* mem */ 65680bb3edaSDuc Dang 0x43000000 0xd8 0x00000000 0xd8 0x00000000 0x08 0x00000000>; /* mem */ 657ca5b3410SRobert Richter dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 658ca5b3410SRobert Richter 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; 6596b5fc336SRob Herring bus-range = <0x00 0xff>; 660ca5b3410SRobert Richter interrupt-map-mask = <0x0 0x0 0x0 0x7>; 6617c7b08bfSDuc Dang interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x4 6627c7b08bfSDuc Dang 0x0 0x0 0x0 0x2 &gic 0x0 0xc9 0x4 6637c7b08bfSDuc Dang 0x0 0x0 0x0 0x3 &gic 0x0 0xca 0x4 6647c7b08bfSDuc Dang 0x0 0x0 0x0 0x4 &gic 0x0 0xcb 0x4>; 665ca5b3410SRobert Richter dma-coherent; 666ca5b3410SRobert Richter clocks = <&pcie1clk 0>; 667e1e6e5c4SDuc Dang msi-parent = <&msi>; 668ca5b3410SRobert Richter }; 669ca5b3410SRobert Richter 670ca5b3410SRobert Richter pcie2: pcie@1f2d0000 { 671ca5b3410SRobert Richter status = "disabled"; 672ca5b3410SRobert Richter device_type = "pci"; 673ca5b3410SRobert Richter compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; 674ca5b3410SRobert Richter #interrupt-cells = <1>; 675ca5b3410SRobert Richter #size-cells = <2>; 676ca5b3410SRobert Richter #address-cells = <3>; 677ca5b3410SRobert Richter reg = < 0x00 0x1f2d0000 0x0 0x00010000 /* Controller registers */ 678ca5b3410SRobert Richter 0x90 0xd0000000 0x0 0x00040000>; /* PCI config space */ 679ca5b3410SRobert Richter reg-names = "csr", "cfg"; 68080bb3edaSDuc Dang ranges = <0x01000000 0x00 0x00000000 0x90 0x10000000 0x00 0x00010000 /* io */ 68180bb3edaSDuc Dang 0x02000000 0x00 0x80000000 0x91 0x80000000 0x00 0x80000000 /* mem */ 68280bb3edaSDuc Dang 0x43000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>; /* mem */ 683ca5b3410SRobert Richter dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 684ca5b3410SRobert Richter 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; 6856b5fc336SRob Herring bus-range = <0x00 0xff>; 686ca5b3410SRobert Richter interrupt-map-mask = <0x0 0x0 0x0 0x7>; 6877c7b08bfSDuc Dang interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x4 6887c7b08bfSDuc Dang 0x0 0x0 0x0 0x2 &gic 0x0 0xcf 0x4 6897c7b08bfSDuc Dang 0x0 0x0 0x0 0x3 &gic 0x0 0xd0 0x4 6907c7b08bfSDuc Dang 0x0 0x0 0x0 0x4 &gic 0x0 0xd1 0x4>; 691ca5b3410SRobert Richter dma-coherent; 692ca5b3410SRobert Richter clocks = <&pcie2clk 0>; 693e1e6e5c4SDuc Dang msi-parent = <&msi>; 694ca5b3410SRobert Richter }; 695ca5b3410SRobert Richter 696ca5b3410SRobert Richter pcie3: pcie@1f500000 { 697ca5b3410SRobert Richter status = "disabled"; 698ca5b3410SRobert Richter device_type = "pci"; 699ca5b3410SRobert Richter compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; 700ca5b3410SRobert Richter #interrupt-cells = <1>; 701ca5b3410SRobert Richter #size-cells = <2>; 702ca5b3410SRobert Richter #address-cells = <3>; 703ca5b3410SRobert Richter reg = < 0x00 0x1f500000 0x0 0x00010000 /* Controller registers */ 704ca5b3410SRobert Richter 0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */ 705ca5b3410SRobert Richter reg-names = "csr", "cfg"; 70680bb3edaSDuc Dang ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000 /* io */ 70780bb3edaSDuc Dang 0x02000000 0x00 0x80000000 0xa1 0x80000000 0x00 0x80000000 /* mem */ 70880bb3edaSDuc Dang 0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */ 709ca5b3410SRobert Richter dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 710ca5b3410SRobert Richter 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; 7116b5fc336SRob Herring bus-range = <0x00 0xff>; 712ca5b3410SRobert Richter interrupt-map-mask = <0x0 0x0 0x0 0x7>; 7137c7b08bfSDuc Dang interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x4 7147c7b08bfSDuc Dang 0x0 0x0 0x0 0x2 &gic 0x0 0xd5 0x4 7157c7b08bfSDuc Dang 0x0 0x0 0x0 0x3 &gic 0x0 0xd6 0x4 7167c7b08bfSDuc Dang 0x0 0x0 0x0 0x4 &gic 0x0 0xd7 0x4>; 717ca5b3410SRobert Richter dma-coherent; 718ca5b3410SRobert Richter clocks = <&pcie3clk 0>; 719e1e6e5c4SDuc Dang msi-parent = <&msi>; 720ca5b3410SRobert Richter }; 721ca5b3410SRobert Richter 722ca5b3410SRobert Richter pcie4: pcie@1f510000 { 723ca5b3410SRobert Richter status = "disabled"; 724ca5b3410SRobert Richter device_type = "pci"; 725ca5b3410SRobert Richter compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; 726ca5b3410SRobert Richter #interrupt-cells = <1>; 727ca5b3410SRobert Richter #size-cells = <2>; 728ca5b3410SRobert Richter #address-cells = <3>; 729ca5b3410SRobert Richter reg = < 0x00 0x1f510000 0x0 0x00010000 /* Controller registers */ 730ca5b3410SRobert Richter 0xc0 0xd0000000 0x0 0x00200000>; /* PCI config space */ 731ca5b3410SRobert Richter reg-names = "csr", "cfg"; 73280bb3edaSDuc Dang ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000 /* io */ 73380bb3edaSDuc Dang 0x02000000 0x00 0x80000000 0xc1 0x80000000 0x00 0x80000000 /* mem */ 73480bb3edaSDuc Dang 0x43000000 0xc8 0x00000000 0xc8 0x00000000 0x08 0x00000000>; /* mem */ 735ca5b3410SRobert Richter dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 736ca5b3410SRobert Richter 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; 7376b5fc336SRob Herring bus-range = <0x00 0xff>; 738ca5b3410SRobert Richter interrupt-map-mask = <0x0 0x0 0x0 0x7>; 7397c7b08bfSDuc Dang interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x4 7407c7b08bfSDuc Dang 0x0 0x0 0x0 0x2 &gic 0x0 0xdb 0x4 7417c7b08bfSDuc Dang 0x0 0x0 0x0 0x3 &gic 0x0 0xdc 0x4 7427c7b08bfSDuc Dang 0x0 0x0 0x0 0x4 &gic 0x0 0xdd 0x4>; 743ca5b3410SRobert Richter dma-coherent; 744ca5b3410SRobert Richter clocks = <&pcie4clk 0>; 745e1e6e5c4SDuc Dang msi-parent = <&msi>; 746ca5b3410SRobert Richter }; 747ca5b3410SRobert Richter 748b0e4563cSDuc Dang mailbox: mailbox@10540000 { 749b0e4563cSDuc Dang compatible = "apm,xgene-slimpro-mbox"; 750b0e4563cSDuc Dang reg = <0x0 0x10540000 0x0 0xa000>; 751b0e4563cSDuc Dang #mbox-cells = <1>; 752b0e4563cSDuc Dang interrupts = <0x0 0x0 0x4>, 753b0e4563cSDuc Dang <0x0 0x1 0x4>, 754b0e4563cSDuc Dang <0x0 0x2 0x4>, 755b0e4563cSDuc Dang <0x0 0x3 0x4>, 756b0e4563cSDuc Dang <0x0 0x4 0x4>, 757b0e4563cSDuc Dang <0x0 0x5 0x4>, 758b0e4563cSDuc Dang <0x0 0x6 0x4>, 759b0e4563cSDuc Dang <0x0 0x7 0x4>; 760b0e4563cSDuc Dang }; 761b0e4563cSDuc Dang 762778b5cbcSDuc Dang i2cslimpro { 763778b5cbcSDuc Dang compatible = "apm,xgene-slimpro-i2c"; 764778b5cbcSDuc Dang mboxes = <&mailbox 0>; 765778b5cbcSDuc Dang }; 766778b5cbcSDuc Dang 767c6d62be5Shotran hwmonslimpro { 768c6d62be5Shotran compatible = "apm,xgene-slimpro-hwmon"; 769c6d62be5Shotran mboxes = <&mailbox 7>; 770c6d62be5Shotran }; 771c6d62be5Shotran 772ca5b3410SRobert Richter serial0: serial@1c020000 { 773ca5b3410SRobert Richter status = "disabled"; 774ca5b3410SRobert Richter compatible = "ns16550a"; 775ca5b3410SRobert Richter reg = <0 0x1c020000 0x0 0x1000>; 776ca5b3410SRobert Richter reg-shift = <2>; 777ca5b3410SRobert Richter clock-frequency = <10000000>; /* Updated by bootloader */ 778ca5b3410SRobert Richter interrupt-parent = <&gic>; 779ca5b3410SRobert Richter interrupts = <0x0 0x4c 0x4>; 780ca5b3410SRobert Richter }; 781ca5b3410SRobert Richter 782ca5b3410SRobert Richter serial1: serial@1c021000 { 783ca5b3410SRobert Richter status = "disabled"; 784ca5b3410SRobert Richter compatible = "ns16550a"; 785ca5b3410SRobert Richter reg = <0 0x1c021000 0x0 0x1000>; 786ca5b3410SRobert Richter reg-shift = <2>; 787ca5b3410SRobert Richter clock-frequency = <10000000>; /* Updated by bootloader */ 788ca5b3410SRobert Richter interrupt-parent = <&gic>; 789ca5b3410SRobert Richter interrupts = <0x0 0x4d 0x4>; 790ca5b3410SRobert Richter }; 791ca5b3410SRobert Richter 792ca5b3410SRobert Richter serial2: serial@1c022000 { 793ca5b3410SRobert Richter status = "disabled"; 794ca5b3410SRobert Richter compatible = "ns16550a"; 795ca5b3410SRobert Richter reg = <0 0x1c022000 0x0 0x1000>; 796ca5b3410SRobert Richter reg-shift = <2>; 797ca5b3410SRobert Richter clock-frequency = <10000000>; /* Updated by bootloader */ 798ca5b3410SRobert Richter interrupt-parent = <&gic>; 799ca5b3410SRobert Richter interrupts = <0x0 0x4e 0x4>; 800ca5b3410SRobert Richter }; 801ca5b3410SRobert Richter 802ca5b3410SRobert Richter serial3: serial@1c023000 { 803ca5b3410SRobert Richter status = "disabled"; 804ca5b3410SRobert Richter compatible = "ns16550a"; 805ca5b3410SRobert Richter reg = <0 0x1c023000 0x0 0x1000>; 806ca5b3410SRobert Richter reg-shift = <2>; 807ca5b3410SRobert Richter clock-frequency = <10000000>; /* Updated by bootloader */ 808ca5b3410SRobert Richter interrupt-parent = <&gic>; 809ca5b3410SRobert Richter interrupts = <0x0 0x4f 0x4>; 810ca5b3410SRobert Richter }; 811ca5b3410SRobert Richter 8128f74e861SSuman Tripathi mmc0: mmc@1c000000 { 8138f74e861SSuman Tripathi compatible = "arasan,sdhci-4.9a"; 8148f74e861SSuman Tripathi reg = <0x0 0x1c000000 0x0 0x100>; 8158f74e861SSuman Tripathi interrupts = <0x0 0x49 0x4>; 8168f74e861SSuman Tripathi dma-coherent; 8178f74e861SSuman Tripathi no-1-8-v; 8188f74e861SSuman Tripathi clock-names = "clk_xin", "clk_ahb"; 8198f74e861SSuman Tripathi clocks = <&sdioclk 0>, <&ahbclk 0>; 8208f74e861SSuman Tripathi }; 8218f74e861SSuman Tripathi 82293beff2cSDuc Dang gfcgpio: gpio0@1701c000 { 8230a09223fSDuc Dang compatible = "apm,xgene-gpio"; 8240a09223fSDuc Dang reg = <0x0 0x1701c000 0x0 0x40>; 8250a09223fSDuc Dang gpio-controller; 8260a09223fSDuc Dang #gpio-cells = <2>; 8270a09223fSDuc Dang }; 8280a09223fSDuc Dang 82993beff2cSDuc Dang dwgpio: gpio@1c024000 { 830e38ec5b9SDuc Dang compatible = "snps,dw-apb-gpio"; 831e38ec5b9SDuc Dang reg = <0x0 0x1c024000 0x0 0x1000>; 832e38ec5b9SDuc Dang #address-cells = <1>; 833e38ec5b9SDuc Dang #size-cells = <0>; 834e38ec5b9SDuc Dang 835e38ec5b9SDuc Dang porta: gpio-controller@0 { 836e38ec5b9SDuc Dang compatible = "snps,dw-apb-gpio-port"; 837e38ec5b9SDuc Dang gpio-controller; 838e90ac411SKrzysztof Kozlowski #gpio-cells = <2>; 839e38ec5b9SDuc Dang snps,nr-gpios = <32>; 840e38ec5b9SDuc Dang reg = <0>; 841e38ec5b9SDuc Dang }; 842e38ec5b9SDuc Dang }; 843e38ec5b9SDuc Dang 84493beff2cSDuc Dang i2c0: i2c@10512000 { 84562ff9683SDuc Dang status = "disabled"; 84662ff9683SDuc Dang #address-cells = <1>; 84762ff9683SDuc Dang #size-cells = <0>; 84862ff9683SDuc Dang compatible = "snps,designware-i2c"; 84962ff9683SDuc Dang reg = <0x0 0x10512000 0x0 0x1000>; 85062ff9683SDuc Dang interrupts = <0 0x44 0x4>; 85162ff9683SDuc Dang #clock-cells = <1>; 8520fe8588fSDuc Dang clocks = <&ahbclk 0>; 85362ff9683SDuc Dang bus_num = <0>; 85462ff9683SDuc Dang }; 85562ff9683SDuc Dang 856ca5b3410SRobert Richter phy1: phy@1f21a000 { 857ca5b3410SRobert Richter compatible = "apm,xgene-phy"; 858ca5b3410SRobert Richter reg = <0x0 0x1f21a000 0x0 0x100>; 859ca5b3410SRobert Richter #phy-cells = <1>; 860ca5b3410SRobert Richter clocks = <&sataphy1clk 0>; 861ca5b3410SRobert Richter status = "disabled"; 862ca5b3410SRobert Richter apm,tx-boost-gain = <30 30 30 30 30 30>; 863ca5b3410SRobert Richter apm,tx-eye-tuning = <2 10 10 2 10 10>; 864ca5b3410SRobert Richter }; 865ca5b3410SRobert Richter 866ca5b3410SRobert Richter phy2: phy@1f22a000 { 867ca5b3410SRobert Richter compatible = "apm,xgene-phy"; 868ca5b3410SRobert Richter reg = <0x0 0x1f22a000 0x0 0x100>; 869ca5b3410SRobert Richter #phy-cells = <1>; 870ca5b3410SRobert Richter clocks = <&sataphy2clk 0>; 8712f308657SKrzysztof Kozlowski status = "okay"; 872ca5b3410SRobert Richter apm,tx-boost-gain = <30 30 30 30 30 30>; 873ca5b3410SRobert Richter apm,tx-eye-tuning = <1 10 10 2 10 10>; 874ca5b3410SRobert Richter }; 875ca5b3410SRobert Richter 876ca5b3410SRobert Richter phy3: phy@1f23a000 { 877ca5b3410SRobert Richter compatible = "apm,xgene-phy"; 878ca5b3410SRobert Richter reg = <0x0 0x1f23a000 0x0 0x100>; 879ca5b3410SRobert Richter #phy-cells = <1>; 880ca5b3410SRobert Richter clocks = <&sataphy3clk 0>; 8812f308657SKrzysztof Kozlowski status = "okay"; 882ca5b3410SRobert Richter apm,tx-boost-gain = <31 31 31 31 31 31>; 883ca5b3410SRobert Richter apm,tx-eye-tuning = <2 10 10 2 10 10>; 884ca5b3410SRobert Richter }; 885ca5b3410SRobert Richter 886ca5b3410SRobert Richter sata1: sata@1a000000 { 887ca5b3410SRobert Richter compatible = "apm,xgene-ahci"; 888ca5b3410SRobert Richter reg = <0x0 0x1a000000 0x0 0x1000>, 889ca5b3410SRobert Richter <0x0 0x1f210000 0x0 0x1000>, 890ca5b3410SRobert Richter <0x0 0x1f21d000 0x0 0x1000>, 891ca5b3410SRobert Richter <0x0 0x1f21e000 0x0 0x1000>, 892ca5b3410SRobert Richter <0x0 0x1f217000 0x0 0x1000>; 893ca5b3410SRobert Richter interrupts = <0x0 0x86 0x4>; 894ca5b3410SRobert Richter dma-coherent; 895ca5b3410SRobert Richter status = "disabled"; 896ca5b3410SRobert Richter clocks = <&sata01clk 0>; 897ca5b3410SRobert Richter phys = <&phy1 0>; 898ca5b3410SRobert Richter phy-names = "sata-phy"; 899ca5b3410SRobert Richter }; 900ca5b3410SRobert Richter 901ca5b3410SRobert Richter sata2: sata@1a400000 { 902ca5b3410SRobert Richter compatible = "apm,xgene-ahci"; 903ca5b3410SRobert Richter reg = <0x0 0x1a400000 0x0 0x1000>, 904ca5b3410SRobert Richter <0x0 0x1f220000 0x0 0x1000>, 905ca5b3410SRobert Richter <0x0 0x1f22d000 0x0 0x1000>, 906ca5b3410SRobert Richter <0x0 0x1f22e000 0x0 0x1000>, 907ca5b3410SRobert Richter <0x0 0x1f227000 0x0 0x1000>; 908ca5b3410SRobert Richter interrupts = <0x0 0x87 0x4>; 909ca5b3410SRobert Richter dma-coherent; 9102f308657SKrzysztof Kozlowski status = "okay"; 911ca5b3410SRobert Richter clocks = <&sata23clk 0>; 912ca5b3410SRobert Richter phys = <&phy2 0>; 913ca5b3410SRobert Richter phy-names = "sata-phy"; 914ca5b3410SRobert Richter }; 915ca5b3410SRobert Richter 916ca5b3410SRobert Richter sata3: sata@1a800000 { 917ca5b3410SRobert Richter compatible = "apm,xgene-ahci"; 918ca5b3410SRobert Richter reg = <0x0 0x1a800000 0x0 0x1000>, 919ca5b3410SRobert Richter <0x0 0x1f230000 0x0 0x1000>, 920ca5b3410SRobert Richter <0x0 0x1f23d000 0x0 0x1000>, 921ca5b3410SRobert Richter <0x0 0x1f23e000 0x0 0x1000>; 922ca5b3410SRobert Richter interrupts = <0x0 0x88 0x4>; 923ca5b3410SRobert Richter dma-coherent; 9242f308657SKrzysztof Kozlowski status = "okay"; 925ca5b3410SRobert Richter clocks = <&sata45clk 0>; 926ca5b3410SRobert Richter phys = <&phy3 0>; 927ca5b3410SRobert Richter phy-names = "sata-phy"; 928ca5b3410SRobert Richter }; 929ca5b3410SRobert Richter 93087ccc38eSSerge Semin /* Node-name might need to be coded as dwusb for backward compatibility */ 93187ccc38eSSerge Semin usb0: usb@19000000 { 932bd410233SDuc Dang status = "disabled"; 933bd410233SDuc Dang compatible = "snps,dwc3"; 934bd410233SDuc Dang reg = <0x0 0x19000000 0x0 0x100000>; 935bd410233SDuc Dang interrupts = <0x0 0x89 0x4>; 936bd410233SDuc Dang dma-coherent; 937bd410233SDuc Dang dr_mode = "host"; 938bd410233SDuc Dang }; 939bd410233SDuc Dang 94087ccc38eSSerge Semin usb1: usb@19800000 { 941bd410233SDuc Dang status = "disabled"; 942bd410233SDuc Dang compatible = "snps,dwc3"; 943bd410233SDuc Dang reg = <0x0 0x19800000 0x0 0x100000>; 944bd410233SDuc Dang interrupts = <0x0 0x8a 0x4>; 945bd410233SDuc Dang dma-coherent; 946bd410233SDuc Dang dr_mode = "host"; 947bd410233SDuc Dang }; 948bd410233SDuc Dang 94993beff2cSDuc Dang sbgpio: gpio@17001000{ 950ea21feb3SY Vo compatible = "apm,xgene-gpio-sb"; 951ea21feb3SY Vo reg = <0x0 0x17001000 0x0 0x400>; 952ea21feb3SY Vo #gpio-cells = <2>; 953ea21feb3SY Vo gpio-controller; 954ea21feb3SY Vo interrupts = <0x0 0x28 0x1>, 955ea21feb3SY Vo <0x0 0x29 0x1>, 956ea21feb3SY Vo <0x0 0x2a 0x1>, 957ea21feb3SY Vo <0x0 0x2b 0x1>, 958ea21feb3SY Vo <0x0 0x2c 0x1>, 959ea21feb3SY Vo <0x0 0x2d 0x1>; 96047f134a2SQuan Nguyen interrupt-parent = <&gic>; 96147f134a2SQuan Nguyen #interrupt-cells = <2>; 96247f134a2SQuan Nguyen interrupt-controller; 963ea21feb3SY Vo }; 964ea21feb3SY Vo 965ca5b3410SRobert Richter rtc: rtc@10510000 { 966ca5b3410SRobert Richter compatible = "apm,xgene-rtc"; 967ca5b3410SRobert Richter reg = <0x0 0x10510000 0x0 0x400>; 968ca5b3410SRobert Richter interrupts = <0x0 0x46 0x4>; 969ca5b3410SRobert Richter #clock-cells = <1>; 970ca5b3410SRobert Richter clocks = <&rtcclk 0>; 971ca5b3410SRobert Richter }; 972ca5b3410SRobert Richter 9738e694cd2SIyappan Subramanian mdio: mdio@17020000 { 9748e694cd2SIyappan Subramanian compatible = "apm,xgene-mdio-rgmii"; 9758e694cd2SIyappan Subramanian #address-cells = <1>; 9768e694cd2SIyappan Subramanian #size-cells = <0>; 9778e694cd2SIyappan Subramanian reg = <0x0 0x17020000 0x0 0xd100>; 9788e694cd2SIyappan Subramanian clocks = <&menetclk 0>; 9798e694cd2SIyappan Subramanian }; 9808e694cd2SIyappan Subramanian 981ca5b3410SRobert Richter menet: ethernet@17020000 { 982ca5b3410SRobert Richter compatible = "apm,xgene-enet"; 983ca5b3410SRobert Richter status = "disabled"; 984ca5b3410SRobert Richter reg = <0x0 0x17020000 0x0 0xd100>, 985cafc4cd0SBjorn Helgaas <0x0 0x17030000 0x0 0xc300>, 986cafc4cd0SBjorn Helgaas <0x0 0x10000000 0x0 0x200>; 987ca5b3410SRobert Richter reg-names = "enet_csr", "ring_csr", "ring_cmd"; 988ca5b3410SRobert Richter interrupts = <0x0 0x3c 0x4>; 989ca5b3410SRobert Richter dma-coherent; 990ca5b3410SRobert Richter clocks = <&menetclk 0>; 991ca5b3410SRobert Richter /* mac address will be overwritten by the bootloader */ 992ca5b3410SRobert Richter local-mac-address = [00 00 00 00 00 00]; 993ca5b3410SRobert Richter phy-connection-type = "rgmii"; 9945ac6caabSIyappan Subramanian phy-handle = <&menetphy>,<&menet0phy>; 995ca5b3410SRobert Richter mdio { 996ca5b3410SRobert Richter compatible = "apm,xgene-mdio"; 997ca5b3410SRobert Richter #address-cells = <1>; 998ca5b3410SRobert Richter #size-cells = <0>; 999ca5b3410SRobert Richter menetphy: menetphy@3 { 1000ca5b3410SRobert Richter compatible = "ethernet-phy-id001c.c915"; 1001ca5b3410SRobert Richter reg = <0x3>; 1002ca5b3410SRobert Richter }; 1003ca5b3410SRobert Richter 1004ca5b3410SRobert Richter }; 1005ca5b3410SRobert Richter }; 1006ca5b3410SRobert Richter 1007ca5b3410SRobert Richter sgenet0: ethernet@1f210000 { 10082a91eb72SIyappan Subramanian compatible = "apm,xgene1-sgenet"; 1009ca5b3410SRobert Richter status = "disabled"; 10106c9e9247SLinus Torvalds reg = <0x0 0x1f210000 0x0 0xd100>, 1011cafc4cd0SBjorn Helgaas <0x0 0x1f200000 0x0 0xc300>, 1012cafc4cd0SBjorn Helgaas <0x0 0x1b000000 0x0 0x200>; 1013ca5b3410SRobert Richter reg-names = "enet_csr", "ring_csr", "ring_cmd"; 1014cafc4cd0SBjorn Helgaas interrupts = <0x0 0xa0 0x4>, 1015cafc4cd0SBjorn Helgaas <0x0 0xa1 0x4>; 1016ca5b3410SRobert Richter dma-coherent; 1017ca5b3410SRobert Richter clocks = <&sge0clk 0>; 1018ca5b3410SRobert Richter local-mac-address = [00 00 00 00 00 00]; 1019ca5b3410SRobert Richter phy-connection-type = "sgmii"; 10208e694cd2SIyappan Subramanian phy-handle = <&sgenet0phy>; 1021ca5b3410SRobert Richter }; 1022ca5b3410SRobert Richter 10232d33394eSKeyur Chudgar sgenet1: ethernet@1f210030 { 10242d33394eSKeyur Chudgar compatible = "apm,xgene1-sgenet"; 10252d33394eSKeyur Chudgar status = "disabled"; 10262d33394eSKeyur Chudgar reg = <0x0 0x1f210030 0x0 0xd100>, 1027cafc4cd0SBjorn Helgaas <0x0 0x1f200000 0x0 0xc300>, 1028cafc4cd0SBjorn Helgaas <0x0 0x1b000000 0x0 0x8000>; 10292d33394eSKeyur Chudgar reg-names = "enet_csr", "ring_csr", "ring_cmd"; 1030cafc4cd0SBjorn Helgaas interrupts = <0x0 0xac 0x4>, 1031cafc4cd0SBjorn Helgaas <0x0 0xad 0x4>; 10322d33394eSKeyur Chudgar port-id = <1>; 10332d33394eSKeyur Chudgar dma-coherent; 10342d33394eSKeyur Chudgar local-mac-address = [00 00 00 00 00 00]; 10352d33394eSKeyur Chudgar phy-connection-type = "sgmii"; 10368e694cd2SIyappan Subramanian phy-handle = <&sgenet1phy>; 10372d33394eSKeyur Chudgar }; 10382d33394eSKeyur Chudgar 1039ca5b3410SRobert Richter xgenet: ethernet@1f610000 { 10402a91eb72SIyappan Subramanian compatible = "apm,xgene1-xgenet"; 1041ca5b3410SRobert Richter status = "disabled"; 1042ca5b3410SRobert Richter reg = <0x0 0x1f610000 0x0 0xd100>, 1043cafc4cd0SBjorn Helgaas <0x0 0x1f600000 0x0 0xc300>, 1044cafc4cd0SBjorn Helgaas <0x0 0x18000000 0x0 0x200>; 1045ca5b3410SRobert Richter reg-names = "enet_csr", "ring_csr", "ring_cmd"; 1046d3134649SIyappan Subramanian interrupts = <0x0 0x60 0x4>, 10470d2c2515SIyappan Subramanian <0x0 0x61 0x4>, 10480d2c2515SIyappan Subramanian <0x0 0x62 0x4>, 10490d2c2515SIyappan Subramanian <0x0 0x63 0x4>, 10500d2c2515SIyappan Subramanian <0x0 0x64 0x4>, 10510d2c2515SIyappan Subramanian <0x0 0x65 0x4>, 10520d2c2515SIyappan Subramanian <0x0 0x66 0x4>, 10530d2c2515SIyappan Subramanian <0x0 0x67 0x4>; 10546619ac5aSIyappan Subramanian channel = <0>; 1055ca5b3410SRobert Richter dma-coherent; 1056ca5b3410SRobert Richter clocks = <&xge0clk 0>; 1057ca5b3410SRobert Richter /* mac address will be overwritten by the bootloader */ 1058ca5b3410SRobert Richter local-mac-address = [00 00 00 00 00 00]; 1059ca5b3410SRobert Richter phy-connection-type = "xgmii"; 1060ca5b3410SRobert Richter }; 1061ca5b3410SRobert Richter 1062e63c7a09SIyappan Subramanian xgenet1: ethernet@1f620000 { 1063e63c7a09SIyappan Subramanian compatible = "apm,xgene1-xgenet"; 1064e63c7a09SIyappan Subramanian status = "disabled"; 1065e63c7a09SIyappan Subramanian reg = <0x0 0x1f620000 0x0 0xd100>, 1066cafc4cd0SBjorn Helgaas <0x0 0x1f600000 0x0 0xc300>, 1067cafc4cd0SBjorn Helgaas <0x0 0x18000000 0x0 0x8000>; 1068e63c7a09SIyappan Subramanian reg-names = "enet_csr", "ring_csr", "ring_cmd"; 1069cafc4cd0SBjorn Helgaas interrupts = <0x0 0x6c 0x4>, 1070cafc4cd0SBjorn Helgaas <0x0 0x6d 0x4>; 1071e63c7a09SIyappan Subramanian port-id = <1>; 1072e63c7a09SIyappan Subramanian dma-coherent; 1073e63c7a09SIyappan Subramanian clocks = <&xge1clk 0>; 1074e63c7a09SIyappan Subramanian /* mac address will be overwritten by the bootloader */ 1075e63c7a09SIyappan Subramanian local-mac-address = [00 00 00 00 00 00]; 1076e63c7a09SIyappan Subramanian phy-connection-type = "xgmii"; 1077e63c7a09SIyappan Subramanian }; 1078e63c7a09SIyappan Subramanian 1079ca5b3410SRobert Richter rng: rng@10520000 { 1080ca5b3410SRobert Richter compatible = "apm,xgene-rng"; 1081ca5b3410SRobert Richter reg = <0x0 0x10520000 0x0 0x100>; 1082ca5b3410SRobert Richter interrupts = <0x0 0x41 0x4>; 1083ca5b3410SRobert Richter clocks = <&rngpkaclk 0>; 1084ca5b3410SRobert Richter }; 108574e353e1SRameshwar Prasad Sahu 108674e353e1SRameshwar Prasad Sahu dma: dma@1f270000 { 108774e353e1SRameshwar Prasad Sahu compatible = "apm,xgene-storm-dma"; 108874e353e1SRameshwar Prasad Sahu device_type = "dma"; 108974e353e1SRameshwar Prasad Sahu reg = <0x0 0x1f270000 0x0 0x10000>, 109074e353e1SRameshwar Prasad Sahu <0x0 0x1f200000 0x0 0x10000>, 1091cda8e937SRameshwar Prasad Sahu <0x0 0x1b000000 0x0 0x400000>, 109274e353e1SRameshwar Prasad Sahu <0x0 0x1054a000 0x0 0x100>; 109374e353e1SRameshwar Prasad Sahu interrupts = <0x0 0x82 0x4>, 109474e353e1SRameshwar Prasad Sahu <0x0 0xb8 0x4>, 109574e353e1SRameshwar Prasad Sahu <0x0 0xb9 0x4>, 109674e353e1SRameshwar Prasad Sahu <0x0 0xba 0x4>, 109774e353e1SRameshwar Prasad Sahu <0x0 0xbb 0x4>; 109874e353e1SRameshwar Prasad Sahu dma-coherent; 109974e353e1SRameshwar Prasad Sahu clocks = <&dmaclk 0>; 110074e353e1SRameshwar Prasad Sahu }; 1101ca5b3410SRobert Richter }; 1102ca5b3410SRobert Richter}; 1103