1d3bf75b5SJianjun Wang // SPDX-License-Identifier: GPL-2.0
2d3bf75b5SJianjun Wang /*
3d3bf75b5SJianjun Wang * MediaTek PCIe host controller driver.
4d3bf75b5SJianjun Wang *
5d3bf75b5SJianjun Wang * Copyright (c) 2020 MediaTek Inc.
6d3bf75b5SJianjun Wang * Author: Jianjun Wang <jianjun.wang@mediatek.com>
7d3bf75b5SJianjun Wang */
8d3bf75b5SJianjun Wang
9d3bf75b5SJianjun Wang #include <linux/clk.h>
10d3bf75b5SJianjun Wang #include <linux/delay.h>
11d3bf75b5SJianjun Wang #include <linux/iopoll.h>
12814cceebSJianjun Wang #include <linux/irq.h>
13814cceebSJianjun Wang #include <linux/irqchip/chained_irq.h>
14814cceebSJianjun Wang #include <linux/irqdomain.h>
15d3bf75b5SJianjun Wang #include <linux/kernel.h>
16d3bf75b5SJianjun Wang #include <linux/module.h>
171bdafba5SJianjun Wang #include <linux/msi.h>
18d3bf75b5SJianjun Wang #include <linux/pci.h>
19d3bf75b5SJianjun Wang #include <linux/phy/phy.h>
20d3bf75b5SJianjun Wang #include <linux/platform_device.h>
21d3bf75b5SJianjun Wang #include <linux/pm_domain.h>
22d3bf75b5SJianjun Wang #include <linux/pm_runtime.h>
23d3bf75b5SJianjun Wang #include <linux/reset.h>
24d3bf75b5SJianjun Wang
25d3bf75b5SJianjun Wang #include "../pci.h"
26d3bf75b5SJianjun Wang
27d3bf75b5SJianjun Wang #define PCIE_SETTING_REG 0x80
28d3bf75b5SJianjun Wang #define PCIE_PCI_IDS_1 0x9c
29d3bf75b5SJianjun Wang #define PCI_CLASS(class) (class << 8)
30d3bf75b5SJianjun Wang #define PCIE_RC_MODE BIT(0)
31d3bf75b5SJianjun Wang
32d3bf75b5SJianjun Wang #define PCIE_CFGNUM_REG 0x140
33d3bf75b5SJianjun Wang #define PCIE_CFG_DEVFN(devfn) ((devfn) & GENMASK(7, 0))
34d3bf75b5SJianjun Wang #define PCIE_CFG_BUS(bus) (((bus) << 8) & GENMASK(15, 8))
35d3bf75b5SJianjun Wang #define PCIE_CFG_BYTE_EN(bytes) (((bytes) << 16) & GENMASK(19, 16))
36d3bf75b5SJianjun Wang #define PCIE_CFG_FORCE_BYTE_EN BIT(20)
37d3bf75b5SJianjun Wang #define PCIE_CFG_OFFSET_ADDR 0x1000
38d3bf75b5SJianjun Wang #define PCIE_CFG_HEADER(bus, devfn) \
39d3bf75b5SJianjun Wang (PCIE_CFG_BUS(bus) | PCIE_CFG_DEVFN(devfn))
40d3bf75b5SJianjun Wang
41d3bf75b5SJianjun Wang #define PCIE_RST_CTRL_REG 0x148
42d3bf75b5SJianjun Wang #define PCIE_MAC_RSTB BIT(0)
43d3bf75b5SJianjun Wang #define PCIE_PHY_RSTB BIT(1)
44d3bf75b5SJianjun Wang #define PCIE_BRG_RSTB BIT(2)
45d3bf75b5SJianjun Wang #define PCIE_PE_RSTB BIT(3)
46d3bf75b5SJianjun Wang
47d3bf75b5SJianjun Wang #define PCIE_LTSSM_STATUS_REG 0x150
48d537dc12SJianjun Wang #define PCIE_LTSSM_STATE_MASK GENMASK(28, 24)
49d537dc12SJianjun Wang #define PCIE_LTSSM_STATE(val) ((val & PCIE_LTSSM_STATE_MASK) >> 24)
50d537dc12SJianjun Wang #define PCIE_LTSSM_STATE_L2_IDLE 0x14
51d3bf75b5SJianjun Wang
52d3bf75b5SJianjun Wang #define PCIE_LINK_STATUS_REG 0x154
53d3bf75b5SJianjun Wang #define PCIE_PORT_LINKUP BIT(8)
54d3bf75b5SJianjun Wang
551bdafba5SJianjun Wang #define PCIE_MSI_SET_NUM 8
561bdafba5SJianjun Wang #define PCIE_MSI_IRQS_PER_SET 32
571bdafba5SJianjun Wang #define PCIE_MSI_IRQS_NUM \
581bdafba5SJianjun Wang (PCIE_MSI_IRQS_PER_SET * PCIE_MSI_SET_NUM)
591bdafba5SJianjun Wang
60814cceebSJianjun Wang #define PCIE_INT_ENABLE_REG 0x180
611bdafba5SJianjun Wang #define PCIE_MSI_ENABLE GENMASK(PCIE_MSI_SET_NUM + 8 - 1, 8)
621bdafba5SJianjun Wang #define PCIE_MSI_SHIFT 8
63814cceebSJianjun Wang #define PCIE_INTX_SHIFT 24
64814cceebSJianjun Wang #define PCIE_INTX_ENABLE \
65814cceebSJianjun Wang GENMASK(PCIE_INTX_SHIFT + PCI_NUM_INTX - 1, PCIE_INTX_SHIFT)
66814cceebSJianjun Wang
67814cceebSJianjun Wang #define PCIE_INT_STATUS_REG 0x184
681bdafba5SJianjun Wang #define PCIE_MSI_SET_ENABLE_REG 0x190
691bdafba5SJianjun Wang #define PCIE_MSI_SET_ENABLE GENMASK(PCIE_MSI_SET_NUM - 1, 0)
701bdafba5SJianjun Wang
711bdafba5SJianjun Wang #define PCIE_MSI_SET_BASE_REG 0xc00
721bdafba5SJianjun Wang #define PCIE_MSI_SET_OFFSET 0x10
731bdafba5SJianjun Wang #define PCIE_MSI_SET_STATUS_OFFSET 0x04
741bdafba5SJianjun Wang #define PCIE_MSI_SET_ENABLE_OFFSET 0x08
751bdafba5SJianjun Wang
761bdafba5SJianjun Wang #define PCIE_MSI_SET_ADDR_HI_BASE 0xc80
771bdafba5SJianjun Wang #define PCIE_MSI_SET_ADDR_HI_OFFSET 0x04
78814cceebSJianjun Wang
79d537dc12SJianjun Wang #define PCIE_ICMD_PM_REG 0x198
80d537dc12SJianjun Wang #define PCIE_TURN_OFF_LINK BIT(4)
81d537dc12SJianjun Wang
82ab344fd4SJianjun Wang #define PCIE_MISC_CTRL_REG 0x348
83ab344fd4SJianjun Wang #define PCIE_DISABLE_DVFSRC_VLT_REQ BIT(1)
84ab344fd4SJianjun Wang
85d3bf75b5SJianjun Wang #define PCIE_TRANS_TABLE_BASE_REG 0x800
86d3bf75b5SJianjun Wang #define PCIE_ATR_SRC_ADDR_MSB_OFFSET 0x4
87d3bf75b5SJianjun Wang #define PCIE_ATR_TRSL_ADDR_LSB_OFFSET 0x8
88d3bf75b5SJianjun Wang #define PCIE_ATR_TRSL_ADDR_MSB_OFFSET 0xc
89d3bf75b5SJianjun Wang #define PCIE_ATR_TRSL_PARAM_OFFSET 0x10
90d3bf75b5SJianjun Wang #define PCIE_ATR_TLB_SET_OFFSET 0x20
91d3bf75b5SJianjun Wang
92d3bf75b5SJianjun Wang #define PCIE_MAX_TRANS_TABLES 8
93d3bf75b5SJianjun Wang #define PCIE_ATR_EN BIT(0)
94d3bf75b5SJianjun Wang #define PCIE_ATR_SIZE(size) \
95d3bf75b5SJianjun Wang (((((size) - 1) << 1) & GENMASK(6, 1)) | PCIE_ATR_EN)
96d3bf75b5SJianjun Wang #define PCIE_ATR_ID(id) ((id) & GENMASK(3, 0))
97d3bf75b5SJianjun Wang #define PCIE_ATR_TYPE_MEM PCIE_ATR_ID(0)
98d3bf75b5SJianjun Wang #define PCIE_ATR_TYPE_IO PCIE_ATR_ID(1)
99d3bf75b5SJianjun Wang #define PCIE_ATR_TLP_TYPE(type) (((type) << 16) & GENMASK(18, 16))
100d3bf75b5SJianjun Wang #define PCIE_ATR_TLP_TYPE_MEM PCIE_ATR_TLP_TYPE(0)
101d3bf75b5SJianjun Wang #define PCIE_ATR_TLP_TYPE_IO PCIE_ATR_TLP_TYPE(2)
102d3bf75b5SJianjun Wang
103d3bf75b5SJianjun Wang /**
1041bdafba5SJianjun Wang * struct mtk_msi_set - MSI information for each set
1051bdafba5SJianjun Wang * @base: IO mapped register base
1061bdafba5SJianjun Wang * @msg_addr: MSI message address
107d537dc12SJianjun Wang * @saved_irq_state: IRQ enable state saved at suspend time
1081bdafba5SJianjun Wang */
1091bdafba5SJianjun Wang struct mtk_msi_set {
1101bdafba5SJianjun Wang void __iomem *base;
1111bdafba5SJianjun Wang phys_addr_t msg_addr;
112d537dc12SJianjun Wang u32 saved_irq_state;
1131bdafba5SJianjun Wang };
1141bdafba5SJianjun Wang
1151bdafba5SJianjun Wang /**
116d5a4835bSFan Fei * struct mtk_gen3_pcie - PCIe port information
117d3bf75b5SJianjun Wang * @dev: pointer to PCIe device
118d3bf75b5SJianjun Wang * @base: IO mapped register base
119d3bf75b5SJianjun Wang * @reg_base: physical register base
120d3bf75b5SJianjun Wang * @mac_reset: MAC reset control
121d3bf75b5SJianjun Wang * @phy_reset: PHY reset control
122d3bf75b5SJianjun Wang * @phy: PHY controller block
123d3bf75b5SJianjun Wang * @clks: PCIe clocks
124d3bf75b5SJianjun Wang * @num_clks: PCIe clocks count for this port
125814cceebSJianjun Wang * @irq: PCIe controller interrupt number
126d537dc12SJianjun Wang * @saved_irq_state: IRQ enable state saved at suspend time
127814cceebSJianjun Wang * @irq_lock: lock protecting IRQ register access
128814cceebSJianjun Wang * @intx_domain: legacy INTx IRQ domain
1291bdafba5SJianjun Wang * @msi_domain: MSI IRQ domain
1301bdafba5SJianjun Wang * @msi_bottom_domain: MSI IRQ bottom domain
1311bdafba5SJianjun Wang * @msi_sets: MSI sets information
1321bdafba5SJianjun Wang * @lock: lock protecting IRQ bit map
1331bdafba5SJianjun Wang * @msi_irq_in_use: bit map for assigned MSI IRQ
134d3bf75b5SJianjun Wang */
135d5a4835bSFan Fei struct mtk_gen3_pcie {
136d3bf75b5SJianjun Wang struct device *dev;
137d3bf75b5SJianjun Wang void __iomem *base;
138d3bf75b5SJianjun Wang phys_addr_t reg_base;
139d3bf75b5SJianjun Wang struct reset_control *mac_reset;
140d3bf75b5SJianjun Wang struct reset_control *phy_reset;
141d3bf75b5SJianjun Wang struct phy *phy;
142d3bf75b5SJianjun Wang struct clk_bulk_data *clks;
143d3bf75b5SJianjun Wang int num_clks;
144814cceebSJianjun Wang
145814cceebSJianjun Wang int irq;
146d537dc12SJianjun Wang u32 saved_irq_state;
147814cceebSJianjun Wang raw_spinlock_t irq_lock;
148814cceebSJianjun Wang struct irq_domain *intx_domain;
1491bdafba5SJianjun Wang struct irq_domain *msi_domain;
1501bdafba5SJianjun Wang struct irq_domain *msi_bottom_domain;
1511bdafba5SJianjun Wang struct mtk_msi_set msi_sets[PCIE_MSI_SET_NUM];
1521bdafba5SJianjun Wang struct mutex lock;
1531bdafba5SJianjun Wang DECLARE_BITMAP(msi_irq_in_use, PCIE_MSI_IRQS_NUM);
154d3bf75b5SJianjun Wang };
155d3bf75b5SJianjun Wang
15628fc842eSJianjun Wang /* LTSSM state in PCIE_LTSSM_STATUS_REG bit[28:24] */
15728fc842eSJianjun Wang static const char *const ltssm_str[] = {
15828fc842eSJianjun Wang "detect.quiet", /* 0x00 */
15928fc842eSJianjun Wang "detect.active", /* 0x01 */
16028fc842eSJianjun Wang "polling.active", /* 0x02 */
16128fc842eSJianjun Wang "polling.compliance", /* 0x03 */
16228fc842eSJianjun Wang "polling.configuration", /* 0x04 */
16328fc842eSJianjun Wang "config.linkwidthstart", /* 0x05 */
16428fc842eSJianjun Wang "config.linkwidthaccept", /* 0x06 */
16528fc842eSJianjun Wang "config.lanenumwait", /* 0x07 */
16628fc842eSJianjun Wang "config.lanenumaccept", /* 0x08 */
16728fc842eSJianjun Wang "config.complete", /* 0x09 */
16828fc842eSJianjun Wang "config.idle", /* 0x0A */
16928fc842eSJianjun Wang "recovery.receiverlock", /* 0x0B */
17028fc842eSJianjun Wang "recovery.equalization", /* 0x0C */
17128fc842eSJianjun Wang "recovery.speed", /* 0x0D */
17228fc842eSJianjun Wang "recovery.receiverconfig", /* 0x0E */
17328fc842eSJianjun Wang "recovery.idle", /* 0x0F */
17428fc842eSJianjun Wang "L0", /* 0x10 */
17528fc842eSJianjun Wang "L0s", /* 0x11 */
17628fc842eSJianjun Wang "L1.entry", /* 0x12 */
17728fc842eSJianjun Wang "L1.idle", /* 0x13 */
17828fc842eSJianjun Wang "L2.idle", /* 0x14 */
17928fc842eSJianjun Wang "L2.transmitwake", /* 0x15 */
18028fc842eSJianjun Wang "disable", /* 0x16 */
18128fc842eSJianjun Wang "loopback.entry", /* 0x17 */
18228fc842eSJianjun Wang "loopback.active", /* 0x18 */
18328fc842eSJianjun Wang "loopback.exit", /* 0x19 */
18428fc842eSJianjun Wang "hotreset", /* 0x1A */
18528fc842eSJianjun Wang };
18628fc842eSJianjun Wang
187d3bf75b5SJianjun Wang /**
188d3bf75b5SJianjun Wang * mtk_pcie_config_tlp_header() - Configure a configuration TLP header
189d3bf75b5SJianjun Wang * @bus: PCI bus to query
190d3bf75b5SJianjun Wang * @devfn: device/function number
191d3bf75b5SJianjun Wang * @where: offset in config space
192d3bf75b5SJianjun Wang * @size: data size in TLP header
193d3bf75b5SJianjun Wang *
194d3bf75b5SJianjun Wang * Set byte enable field and device information in configuration TLP header.
195d3bf75b5SJianjun Wang */
mtk_pcie_config_tlp_header(struct pci_bus * bus,unsigned int devfn,int where,int size)196d3bf75b5SJianjun Wang static void mtk_pcie_config_tlp_header(struct pci_bus *bus, unsigned int devfn,
197d3bf75b5SJianjun Wang int where, int size)
198d3bf75b5SJianjun Wang {
199d5a4835bSFan Fei struct mtk_gen3_pcie *pcie = bus->sysdata;
200d3bf75b5SJianjun Wang int bytes;
201d3bf75b5SJianjun Wang u32 val;
202d3bf75b5SJianjun Wang
203d3bf75b5SJianjun Wang bytes = (GENMASK(size - 1, 0) & 0xf) << (where & 0x3);
204d3bf75b5SJianjun Wang
205d3bf75b5SJianjun Wang val = PCIE_CFG_FORCE_BYTE_EN | PCIE_CFG_BYTE_EN(bytes) |
206d3bf75b5SJianjun Wang PCIE_CFG_HEADER(bus->number, devfn);
207d3bf75b5SJianjun Wang
208d5a4835bSFan Fei writel_relaxed(val, pcie->base + PCIE_CFGNUM_REG);
209d3bf75b5SJianjun Wang }
210d3bf75b5SJianjun Wang
mtk_pcie_map_bus(struct pci_bus * bus,unsigned int devfn,int where)211d3bf75b5SJianjun Wang static void __iomem *mtk_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
212d3bf75b5SJianjun Wang int where)
213d3bf75b5SJianjun Wang {
214d5a4835bSFan Fei struct mtk_gen3_pcie *pcie = bus->sysdata;
215d3bf75b5SJianjun Wang
216d5a4835bSFan Fei return pcie->base + PCIE_CFG_OFFSET_ADDR + where;
217d3bf75b5SJianjun Wang }
218d3bf75b5SJianjun Wang
mtk_pcie_config_read(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 * val)219d3bf75b5SJianjun Wang static int mtk_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
220d3bf75b5SJianjun Wang int where, int size, u32 *val)
221d3bf75b5SJianjun Wang {
222d3bf75b5SJianjun Wang mtk_pcie_config_tlp_header(bus, devfn, where, size);
223d3bf75b5SJianjun Wang
224d3bf75b5SJianjun Wang return pci_generic_config_read32(bus, devfn, where, size, val);
225d3bf75b5SJianjun Wang }
226d3bf75b5SJianjun Wang
mtk_pcie_config_write(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 val)227d3bf75b5SJianjun Wang static int mtk_pcie_config_write(struct pci_bus *bus, unsigned int devfn,
228d3bf75b5SJianjun Wang int where, int size, u32 val)
229d3bf75b5SJianjun Wang {
230d3bf75b5SJianjun Wang mtk_pcie_config_tlp_header(bus, devfn, where, size);
231d3bf75b5SJianjun Wang
232d3bf75b5SJianjun Wang if (size <= 2)
233d3bf75b5SJianjun Wang val <<= (where & 0x3) * 8;
234d3bf75b5SJianjun Wang
235d3bf75b5SJianjun Wang return pci_generic_config_write32(bus, devfn, where, 4, val);
236d3bf75b5SJianjun Wang }
237d3bf75b5SJianjun Wang
238d3bf75b5SJianjun Wang static struct pci_ops mtk_pcie_ops = {
239d3bf75b5SJianjun Wang .map_bus = mtk_pcie_map_bus,
240d3bf75b5SJianjun Wang .read = mtk_pcie_config_read,
241d3bf75b5SJianjun Wang .write = mtk_pcie_config_write,
242d3bf75b5SJianjun Wang };
243d3bf75b5SJianjun Wang
mtk_pcie_set_trans_table(struct mtk_gen3_pcie * pcie,resource_size_t cpu_addr,resource_size_t pci_addr,resource_size_t size,unsigned long type,int * num)244d5a4835bSFan Fei static int mtk_pcie_set_trans_table(struct mtk_gen3_pcie *pcie,
245d3bf75b5SJianjun Wang resource_size_t cpu_addr,
246d3bf75b5SJianjun Wang resource_size_t pci_addr,
247d3bf75b5SJianjun Wang resource_size_t size,
248*a765609fSJianjun Wang unsigned long type, int *num)
249d3bf75b5SJianjun Wang {
250*a765609fSJianjun Wang resource_size_t remaining = size;
251*a765609fSJianjun Wang resource_size_t table_size;
252*a765609fSJianjun Wang resource_size_t addr_align;
253*a765609fSJianjun Wang const char *range_type;
254d3bf75b5SJianjun Wang void __iomem *table;
255d3bf75b5SJianjun Wang u32 val;
256d3bf75b5SJianjun Wang
257*a765609fSJianjun Wang while (remaining && (*num < PCIE_MAX_TRANS_TABLES)) {
258*a765609fSJianjun Wang /* Table size needs to be a power of 2 */
259*a765609fSJianjun Wang table_size = BIT(fls(remaining) - 1);
260*a765609fSJianjun Wang
261*a765609fSJianjun Wang if (cpu_addr > 0) {
262*a765609fSJianjun Wang addr_align = BIT(ffs(cpu_addr) - 1);
263*a765609fSJianjun Wang table_size = min(table_size, addr_align);
264d3bf75b5SJianjun Wang }
265d3bf75b5SJianjun Wang
266*a765609fSJianjun Wang /* Minimum size of translate table is 4KiB */
267*a765609fSJianjun Wang if (table_size < 0x1000) {
268*a765609fSJianjun Wang dev_err(pcie->dev, "illegal table size %#llx\n",
269*a765609fSJianjun Wang (unsigned long long)table_size);
270*a765609fSJianjun Wang return -EINVAL;
271*a765609fSJianjun Wang }
272d3bf75b5SJianjun Wang
273*a765609fSJianjun Wang table = pcie->base + PCIE_TRANS_TABLE_BASE_REG + *num * PCIE_ATR_TLB_SET_OFFSET;
274*a765609fSJianjun Wang writel_relaxed(lower_32_bits(cpu_addr) | PCIE_ATR_SIZE(fls(table_size) - 1), table);
275*a765609fSJianjun Wang writel_relaxed(upper_32_bits(cpu_addr), table + PCIE_ATR_SRC_ADDR_MSB_OFFSET);
276*a765609fSJianjun Wang writel_relaxed(lower_32_bits(pci_addr), table + PCIE_ATR_TRSL_ADDR_LSB_OFFSET);
277*a765609fSJianjun Wang writel_relaxed(upper_32_bits(pci_addr), table + PCIE_ATR_TRSL_ADDR_MSB_OFFSET);
278d3bf75b5SJianjun Wang
279*a765609fSJianjun Wang if (type == IORESOURCE_IO) {
280d3bf75b5SJianjun Wang val = PCIE_ATR_TYPE_IO | PCIE_ATR_TLP_TYPE_IO;
281*a765609fSJianjun Wang range_type = "IO";
282*a765609fSJianjun Wang } else {
283d3bf75b5SJianjun Wang val = PCIE_ATR_TYPE_MEM | PCIE_ATR_TLP_TYPE_MEM;
284*a765609fSJianjun Wang range_type = "MEM";
285*a765609fSJianjun Wang }
286d3bf75b5SJianjun Wang
287d3bf75b5SJianjun Wang writel_relaxed(val, table + PCIE_ATR_TRSL_PARAM_OFFSET);
288d3bf75b5SJianjun Wang
289*a765609fSJianjun Wang dev_dbg(pcie->dev, "set %s trans window[%d]: cpu_addr = %#llx, pci_addr = %#llx, size = %#llx\n",
290*a765609fSJianjun Wang range_type, *num, (unsigned long long)cpu_addr,
291*a765609fSJianjun Wang (unsigned long long)pci_addr, (unsigned long long)table_size);
292*a765609fSJianjun Wang
293*a765609fSJianjun Wang cpu_addr += table_size;
294*a765609fSJianjun Wang pci_addr += table_size;
295*a765609fSJianjun Wang remaining -= table_size;
296*a765609fSJianjun Wang (*num)++;
297*a765609fSJianjun Wang }
298*a765609fSJianjun Wang
299*a765609fSJianjun Wang if (remaining)
300*a765609fSJianjun Wang dev_warn(pcie->dev, "not enough translate table for addr: %#llx, limited to [%d]\n",
301*a765609fSJianjun Wang (unsigned long long)cpu_addr, PCIE_MAX_TRANS_TABLES);
302*a765609fSJianjun Wang
303d3bf75b5SJianjun Wang return 0;
304d3bf75b5SJianjun Wang }
305d3bf75b5SJianjun Wang
mtk_pcie_enable_msi(struct mtk_gen3_pcie * pcie)306d5a4835bSFan Fei static void mtk_pcie_enable_msi(struct mtk_gen3_pcie *pcie)
3071bdafba5SJianjun Wang {
3081bdafba5SJianjun Wang int i;
3091bdafba5SJianjun Wang u32 val;
3101bdafba5SJianjun Wang
3111bdafba5SJianjun Wang for (i = 0; i < PCIE_MSI_SET_NUM; i++) {
312d5a4835bSFan Fei struct mtk_msi_set *msi_set = &pcie->msi_sets[i];
3131bdafba5SJianjun Wang
314d5a4835bSFan Fei msi_set->base = pcie->base + PCIE_MSI_SET_BASE_REG +
3151bdafba5SJianjun Wang i * PCIE_MSI_SET_OFFSET;
316d5a4835bSFan Fei msi_set->msg_addr = pcie->reg_base + PCIE_MSI_SET_BASE_REG +
3171bdafba5SJianjun Wang i * PCIE_MSI_SET_OFFSET;
3181bdafba5SJianjun Wang
3191bdafba5SJianjun Wang /* Configure the MSI capture address */
3201bdafba5SJianjun Wang writel_relaxed(lower_32_bits(msi_set->msg_addr), msi_set->base);
3211bdafba5SJianjun Wang writel_relaxed(upper_32_bits(msi_set->msg_addr),
322d5a4835bSFan Fei pcie->base + PCIE_MSI_SET_ADDR_HI_BASE +
3231bdafba5SJianjun Wang i * PCIE_MSI_SET_ADDR_HI_OFFSET);
3241bdafba5SJianjun Wang }
3251bdafba5SJianjun Wang
326d5a4835bSFan Fei val = readl_relaxed(pcie->base + PCIE_MSI_SET_ENABLE_REG);
3271bdafba5SJianjun Wang val |= PCIE_MSI_SET_ENABLE;
328d5a4835bSFan Fei writel_relaxed(val, pcie->base + PCIE_MSI_SET_ENABLE_REG);
3291bdafba5SJianjun Wang
330d5a4835bSFan Fei val = readl_relaxed(pcie->base + PCIE_INT_ENABLE_REG);
3311bdafba5SJianjun Wang val |= PCIE_MSI_ENABLE;
332d5a4835bSFan Fei writel_relaxed(val, pcie->base + PCIE_INT_ENABLE_REG);
3331bdafba5SJianjun Wang }
3341bdafba5SJianjun Wang
mtk_pcie_startup_port(struct mtk_gen3_pcie * pcie)335d5a4835bSFan Fei static int mtk_pcie_startup_port(struct mtk_gen3_pcie *pcie)
336d3bf75b5SJianjun Wang {
337d3bf75b5SJianjun Wang struct resource_entry *entry;
338d5a4835bSFan Fei struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
339d3bf75b5SJianjun Wang unsigned int table_index = 0;
340d3bf75b5SJianjun Wang int err;
341d3bf75b5SJianjun Wang u32 val;
342d3bf75b5SJianjun Wang
343d3bf75b5SJianjun Wang /* Set as RC mode */
344d5a4835bSFan Fei val = readl_relaxed(pcie->base + PCIE_SETTING_REG);
345d3bf75b5SJianjun Wang val |= PCIE_RC_MODE;
346d5a4835bSFan Fei writel_relaxed(val, pcie->base + PCIE_SETTING_REG);
347d3bf75b5SJianjun Wang
348d3bf75b5SJianjun Wang /* Set class code */
349d5a4835bSFan Fei val = readl_relaxed(pcie->base + PCIE_PCI_IDS_1);
350d3bf75b5SJianjun Wang val &= ~GENMASK(31, 8);
351904b10fbSPali Rohár val |= PCI_CLASS(PCI_CLASS_BRIDGE_PCI_NORMAL);
352d5a4835bSFan Fei writel_relaxed(val, pcie->base + PCIE_PCI_IDS_1);
353d3bf75b5SJianjun Wang
354814cceebSJianjun Wang /* Mask all INTx interrupts */
355d5a4835bSFan Fei val = readl_relaxed(pcie->base + PCIE_INT_ENABLE_REG);
356814cceebSJianjun Wang val &= ~PCIE_INTX_ENABLE;
357d5a4835bSFan Fei writel_relaxed(val, pcie->base + PCIE_INT_ENABLE_REG);
358814cceebSJianjun Wang
359ab344fd4SJianjun Wang /* Disable DVFSRC voltage request */
36087c71931SBjorn Helgaas val = readl_relaxed(pcie->base + PCIE_MISC_CTRL_REG);
361ab344fd4SJianjun Wang val |= PCIE_DISABLE_DVFSRC_VLT_REQ;
36287c71931SBjorn Helgaas writel_relaxed(val, pcie->base + PCIE_MISC_CTRL_REG);
363ab344fd4SJianjun Wang
364d3bf75b5SJianjun Wang /* Assert all reset signals */
365d5a4835bSFan Fei val = readl_relaxed(pcie->base + PCIE_RST_CTRL_REG);
366d3bf75b5SJianjun Wang val |= PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB;
367d5a4835bSFan Fei writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
368d3bf75b5SJianjun Wang
369d3bf75b5SJianjun Wang /*
370ccd36795SKrzysztof Wilczyński * Described in PCIe CEM specification sections 2.2 (PERST# Signal)
371d3bf75b5SJianjun Wang * and 2.2.1 (Initial Power-Up (G3 to S0)).
372d3bf75b5SJianjun Wang * The deassertion of PERST# should be delayed 100ms (TPVPERL)
373d3bf75b5SJianjun Wang * for the power and clock to become stable.
374d3bf75b5SJianjun Wang */
375d3bf75b5SJianjun Wang msleep(100);
376d3bf75b5SJianjun Wang
377d3bf75b5SJianjun Wang /* De-assert reset signals */
378d3bf75b5SJianjun Wang val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB);
379d5a4835bSFan Fei writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
380d3bf75b5SJianjun Wang
381d3bf75b5SJianjun Wang /* Check if the link is up or not */
382d5a4835bSFan Fei err = readl_poll_timeout(pcie->base + PCIE_LINK_STATUS_REG, val,
383d3bf75b5SJianjun Wang !!(val & PCIE_PORT_LINKUP), 20,
384d3bf75b5SJianjun Wang PCI_PM_D3COLD_WAIT * USEC_PER_MSEC);
385d3bf75b5SJianjun Wang if (err) {
38628fc842eSJianjun Wang const char *ltssm_state;
38728fc842eSJianjun Wang int ltssm_index;
38828fc842eSJianjun Wang
389d5a4835bSFan Fei val = readl_relaxed(pcie->base + PCIE_LTSSM_STATUS_REG);
39028fc842eSJianjun Wang ltssm_index = PCIE_LTSSM_STATE(val);
39128fc842eSJianjun Wang ltssm_state = ltssm_index >= ARRAY_SIZE(ltssm_str) ?
39228fc842eSJianjun Wang "Unknown state" : ltssm_str[ltssm_index];
39328fc842eSJianjun Wang dev_err(pcie->dev,
39428fc842eSJianjun Wang "PCIe link down, current LTSSM state: %s (%#x)\n",
39528fc842eSJianjun Wang ltssm_state, val);
396d3bf75b5SJianjun Wang return err;
397d3bf75b5SJianjun Wang }
398d3bf75b5SJianjun Wang
399d5a4835bSFan Fei mtk_pcie_enable_msi(pcie);
4001bdafba5SJianjun Wang
401d3bf75b5SJianjun Wang /* Set PCIe translation windows */
402d3bf75b5SJianjun Wang resource_list_for_each_entry(entry, &host->windows) {
403d3bf75b5SJianjun Wang struct resource *res = entry->res;
404d3bf75b5SJianjun Wang unsigned long type = resource_type(res);
405d3bf75b5SJianjun Wang resource_size_t cpu_addr;
406d3bf75b5SJianjun Wang resource_size_t pci_addr;
407d3bf75b5SJianjun Wang resource_size_t size;
408d3bf75b5SJianjun Wang
409*a765609fSJianjun Wang if (type == IORESOURCE_IO)
410d3bf75b5SJianjun Wang cpu_addr = pci_pio_to_address(res->start);
411*a765609fSJianjun Wang else if (type == IORESOURCE_MEM)
412d3bf75b5SJianjun Wang cpu_addr = res->start;
413*a765609fSJianjun Wang else
414d3bf75b5SJianjun Wang continue;
415d3bf75b5SJianjun Wang
416d3bf75b5SJianjun Wang pci_addr = res->start - entry->offset;
417d3bf75b5SJianjun Wang size = resource_size(res);
418d5a4835bSFan Fei err = mtk_pcie_set_trans_table(pcie, cpu_addr, pci_addr, size,
419*a765609fSJianjun Wang type, &table_index);
420d3bf75b5SJianjun Wang if (err)
421d3bf75b5SJianjun Wang return err;
422d3bf75b5SJianjun Wang }
423d3bf75b5SJianjun Wang
424d3bf75b5SJianjun Wang return 0;
425d3bf75b5SJianjun Wang }
426d3bf75b5SJianjun Wang
mtk_pcie_set_affinity(struct irq_data * data,const struct cpumask * mask,bool force)427814cceebSJianjun Wang static int mtk_pcie_set_affinity(struct irq_data *data,
428814cceebSJianjun Wang const struct cpumask *mask, bool force)
429814cceebSJianjun Wang {
430814cceebSJianjun Wang return -EINVAL;
431814cceebSJianjun Wang }
432814cceebSJianjun Wang
mtk_pcie_msi_irq_mask(struct irq_data * data)4331bdafba5SJianjun Wang static void mtk_pcie_msi_irq_mask(struct irq_data *data)
4341bdafba5SJianjun Wang {
4351bdafba5SJianjun Wang pci_msi_mask_irq(data);
4361bdafba5SJianjun Wang irq_chip_mask_parent(data);
4371bdafba5SJianjun Wang }
4381bdafba5SJianjun Wang
mtk_pcie_msi_irq_unmask(struct irq_data * data)4391bdafba5SJianjun Wang static void mtk_pcie_msi_irq_unmask(struct irq_data *data)
4401bdafba5SJianjun Wang {
4411bdafba5SJianjun Wang pci_msi_unmask_irq(data);
4421bdafba5SJianjun Wang irq_chip_unmask_parent(data);
4431bdafba5SJianjun Wang }
4441bdafba5SJianjun Wang
4451bdafba5SJianjun Wang static struct irq_chip mtk_msi_irq_chip = {
4461bdafba5SJianjun Wang .irq_ack = irq_chip_ack_parent,
4471bdafba5SJianjun Wang .irq_mask = mtk_pcie_msi_irq_mask,
4481bdafba5SJianjun Wang .irq_unmask = mtk_pcie_msi_irq_unmask,
4491bdafba5SJianjun Wang .name = "MSI",
4501bdafba5SJianjun Wang };
4511bdafba5SJianjun Wang
4521bdafba5SJianjun Wang static struct msi_domain_info mtk_msi_domain_info = {
4531bdafba5SJianjun Wang .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
4541bdafba5SJianjun Wang MSI_FLAG_PCI_MSIX | MSI_FLAG_MULTI_PCI_MSI),
4551bdafba5SJianjun Wang .chip = &mtk_msi_irq_chip,
4561bdafba5SJianjun Wang };
4571bdafba5SJianjun Wang
mtk_compose_msi_msg(struct irq_data * data,struct msi_msg * msg)4581bdafba5SJianjun Wang static void mtk_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
4591bdafba5SJianjun Wang {
4601bdafba5SJianjun Wang struct mtk_msi_set *msi_set = irq_data_get_irq_chip_data(data);
461d5a4835bSFan Fei struct mtk_gen3_pcie *pcie = data->domain->host_data;
4621bdafba5SJianjun Wang unsigned long hwirq;
4631bdafba5SJianjun Wang
4641bdafba5SJianjun Wang hwirq = data->hwirq % PCIE_MSI_IRQS_PER_SET;
4651bdafba5SJianjun Wang
4661bdafba5SJianjun Wang msg->address_hi = upper_32_bits(msi_set->msg_addr);
4671bdafba5SJianjun Wang msg->address_lo = lower_32_bits(msi_set->msg_addr);
4681bdafba5SJianjun Wang msg->data = hwirq;
469d5a4835bSFan Fei dev_dbg(pcie->dev, "msi#%#lx address_hi %#x address_lo %#x data %d\n",
4701bdafba5SJianjun Wang hwirq, msg->address_hi, msg->address_lo, msg->data);
4711bdafba5SJianjun Wang }
4721bdafba5SJianjun Wang
mtk_msi_bottom_irq_ack(struct irq_data * data)4731bdafba5SJianjun Wang static void mtk_msi_bottom_irq_ack(struct irq_data *data)
4741bdafba5SJianjun Wang {
4751bdafba5SJianjun Wang struct mtk_msi_set *msi_set = irq_data_get_irq_chip_data(data);
4761bdafba5SJianjun Wang unsigned long hwirq;
4771bdafba5SJianjun Wang
4781bdafba5SJianjun Wang hwirq = data->hwirq % PCIE_MSI_IRQS_PER_SET;
4791bdafba5SJianjun Wang
4801bdafba5SJianjun Wang writel_relaxed(BIT(hwirq), msi_set->base + PCIE_MSI_SET_STATUS_OFFSET);
4811bdafba5SJianjun Wang }
4821bdafba5SJianjun Wang
mtk_msi_bottom_irq_mask(struct irq_data * data)4831bdafba5SJianjun Wang static void mtk_msi_bottom_irq_mask(struct irq_data *data)
4841bdafba5SJianjun Wang {
4851bdafba5SJianjun Wang struct mtk_msi_set *msi_set = irq_data_get_irq_chip_data(data);
486d5a4835bSFan Fei struct mtk_gen3_pcie *pcie = data->domain->host_data;
4871bdafba5SJianjun Wang unsigned long hwirq, flags;
4881bdafba5SJianjun Wang u32 val;
4891bdafba5SJianjun Wang
4901bdafba5SJianjun Wang hwirq = data->hwirq % PCIE_MSI_IRQS_PER_SET;
4911bdafba5SJianjun Wang
492d5a4835bSFan Fei raw_spin_lock_irqsave(&pcie->irq_lock, flags);
4931bdafba5SJianjun Wang val = readl_relaxed(msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET);
4941bdafba5SJianjun Wang val &= ~BIT(hwirq);
4951bdafba5SJianjun Wang writel_relaxed(val, msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET);
496d5a4835bSFan Fei raw_spin_unlock_irqrestore(&pcie->irq_lock, flags);
4971bdafba5SJianjun Wang }
4981bdafba5SJianjun Wang
mtk_msi_bottom_irq_unmask(struct irq_data * data)4991bdafba5SJianjun Wang static void mtk_msi_bottom_irq_unmask(struct irq_data *data)
5001bdafba5SJianjun Wang {
5011bdafba5SJianjun Wang struct mtk_msi_set *msi_set = irq_data_get_irq_chip_data(data);
502d5a4835bSFan Fei struct mtk_gen3_pcie *pcie = data->domain->host_data;
5031bdafba5SJianjun Wang unsigned long hwirq, flags;
5041bdafba5SJianjun Wang u32 val;
5051bdafba5SJianjun Wang
5061bdafba5SJianjun Wang hwirq = data->hwirq % PCIE_MSI_IRQS_PER_SET;
5071bdafba5SJianjun Wang
508d5a4835bSFan Fei raw_spin_lock_irqsave(&pcie->irq_lock, flags);
5091bdafba5SJianjun Wang val = readl_relaxed(msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET);
5101bdafba5SJianjun Wang val |= BIT(hwirq);
5111bdafba5SJianjun Wang writel_relaxed(val, msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET);
512d5a4835bSFan Fei raw_spin_unlock_irqrestore(&pcie->irq_lock, flags);
5131bdafba5SJianjun Wang }
5141bdafba5SJianjun Wang
5151bdafba5SJianjun Wang static struct irq_chip mtk_msi_bottom_irq_chip = {
5161bdafba5SJianjun Wang .irq_ack = mtk_msi_bottom_irq_ack,
5171bdafba5SJianjun Wang .irq_mask = mtk_msi_bottom_irq_mask,
5181bdafba5SJianjun Wang .irq_unmask = mtk_msi_bottom_irq_unmask,
5191bdafba5SJianjun Wang .irq_compose_msi_msg = mtk_compose_msi_msg,
5201bdafba5SJianjun Wang .irq_set_affinity = mtk_pcie_set_affinity,
5211bdafba5SJianjun Wang .name = "MSI",
5221bdafba5SJianjun Wang };
5231bdafba5SJianjun Wang
mtk_msi_bottom_domain_alloc(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs,void * arg)5241bdafba5SJianjun Wang static int mtk_msi_bottom_domain_alloc(struct irq_domain *domain,
5251bdafba5SJianjun Wang unsigned int virq, unsigned int nr_irqs,
5261bdafba5SJianjun Wang void *arg)
5271bdafba5SJianjun Wang {
528d5a4835bSFan Fei struct mtk_gen3_pcie *pcie = domain->host_data;
5291bdafba5SJianjun Wang struct mtk_msi_set *msi_set;
5301bdafba5SJianjun Wang int i, hwirq, set_idx;
5311bdafba5SJianjun Wang
532d5a4835bSFan Fei mutex_lock(&pcie->lock);
5331bdafba5SJianjun Wang
534d5a4835bSFan Fei hwirq = bitmap_find_free_region(pcie->msi_irq_in_use, PCIE_MSI_IRQS_NUM,
5351bdafba5SJianjun Wang order_base_2(nr_irqs));
5361bdafba5SJianjun Wang
537d5a4835bSFan Fei mutex_unlock(&pcie->lock);
5381bdafba5SJianjun Wang
5391bdafba5SJianjun Wang if (hwirq < 0)
5401bdafba5SJianjun Wang return -ENOSPC;
5411bdafba5SJianjun Wang
5421bdafba5SJianjun Wang set_idx = hwirq / PCIE_MSI_IRQS_PER_SET;
543d5a4835bSFan Fei msi_set = &pcie->msi_sets[set_idx];
5441bdafba5SJianjun Wang
5451bdafba5SJianjun Wang for (i = 0; i < nr_irqs; i++)
5461bdafba5SJianjun Wang irq_domain_set_info(domain, virq + i, hwirq + i,
5471bdafba5SJianjun Wang &mtk_msi_bottom_irq_chip, msi_set,
5481bdafba5SJianjun Wang handle_edge_irq, NULL, NULL);
5491bdafba5SJianjun Wang
5501bdafba5SJianjun Wang return 0;
5511bdafba5SJianjun Wang }
5521bdafba5SJianjun Wang
mtk_msi_bottom_domain_free(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs)5531bdafba5SJianjun Wang static void mtk_msi_bottom_domain_free(struct irq_domain *domain,
5541bdafba5SJianjun Wang unsigned int virq, unsigned int nr_irqs)
5551bdafba5SJianjun Wang {
556d5a4835bSFan Fei struct mtk_gen3_pcie *pcie = domain->host_data;
5571bdafba5SJianjun Wang struct irq_data *data = irq_domain_get_irq_data(domain, virq);
5581bdafba5SJianjun Wang
559d5a4835bSFan Fei mutex_lock(&pcie->lock);
5601bdafba5SJianjun Wang
561d5a4835bSFan Fei bitmap_release_region(pcie->msi_irq_in_use, data->hwirq,
5621bdafba5SJianjun Wang order_base_2(nr_irqs));
5631bdafba5SJianjun Wang
564d5a4835bSFan Fei mutex_unlock(&pcie->lock);
5651bdafba5SJianjun Wang
5661bdafba5SJianjun Wang irq_domain_free_irqs_common(domain, virq, nr_irqs);
5671bdafba5SJianjun Wang }
5681bdafba5SJianjun Wang
5691bdafba5SJianjun Wang static const struct irq_domain_ops mtk_msi_bottom_domain_ops = {
5701bdafba5SJianjun Wang .alloc = mtk_msi_bottom_domain_alloc,
5711bdafba5SJianjun Wang .free = mtk_msi_bottom_domain_free,
5721bdafba5SJianjun Wang };
5731bdafba5SJianjun Wang
mtk_intx_mask(struct irq_data * data)574814cceebSJianjun Wang static void mtk_intx_mask(struct irq_data *data)
575814cceebSJianjun Wang {
576d5a4835bSFan Fei struct mtk_gen3_pcie *pcie = irq_data_get_irq_chip_data(data);
577814cceebSJianjun Wang unsigned long flags;
578814cceebSJianjun Wang u32 val;
579814cceebSJianjun Wang
580d5a4835bSFan Fei raw_spin_lock_irqsave(&pcie->irq_lock, flags);
581d5a4835bSFan Fei val = readl_relaxed(pcie->base + PCIE_INT_ENABLE_REG);
582814cceebSJianjun Wang val &= ~BIT(data->hwirq + PCIE_INTX_SHIFT);
583d5a4835bSFan Fei writel_relaxed(val, pcie->base + PCIE_INT_ENABLE_REG);
584d5a4835bSFan Fei raw_spin_unlock_irqrestore(&pcie->irq_lock, flags);
585814cceebSJianjun Wang }
586814cceebSJianjun Wang
mtk_intx_unmask(struct irq_data * data)587814cceebSJianjun Wang static void mtk_intx_unmask(struct irq_data *data)
588814cceebSJianjun Wang {
589d5a4835bSFan Fei struct mtk_gen3_pcie *pcie = irq_data_get_irq_chip_data(data);
590814cceebSJianjun Wang unsigned long flags;
591814cceebSJianjun Wang u32 val;
592814cceebSJianjun Wang
593d5a4835bSFan Fei raw_spin_lock_irqsave(&pcie->irq_lock, flags);
594d5a4835bSFan Fei val = readl_relaxed(pcie->base + PCIE_INT_ENABLE_REG);
595814cceebSJianjun Wang val |= BIT(data->hwirq + PCIE_INTX_SHIFT);
596d5a4835bSFan Fei writel_relaxed(val, pcie->base + PCIE_INT_ENABLE_REG);
597d5a4835bSFan Fei raw_spin_unlock_irqrestore(&pcie->irq_lock, flags);
598814cceebSJianjun Wang }
599814cceebSJianjun Wang
600814cceebSJianjun Wang /**
601814cceebSJianjun Wang * mtk_intx_eoi() - Clear INTx IRQ status at the end of interrupt
602814cceebSJianjun Wang * @data: pointer to chip specific data
603814cceebSJianjun Wang *
604814cceebSJianjun Wang * As an emulated level IRQ, its interrupt status will remain
605814cceebSJianjun Wang * until the corresponding de-assert message is received; hence that
606814cceebSJianjun Wang * the status can only be cleared when the interrupt has been serviced.
607814cceebSJianjun Wang */
mtk_intx_eoi(struct irq_data * data)608814cceebSJianjun Wang static void mtk_intx_eoi(struct irq_data *data)
609814cceebSJianjun Wang {
610d5a4835bSFan Fei struct mtk_gen3_pcie *pcie = irq_data_get_irq_chip_data(data);
611814cceebSJianjun Wang unsigned long hwirq;
612814cceebSJianjun Wang
613814cceebSJianjun Wang hwirq = data->hwirq + PCIE_INTX_SHIFT;
614d5a4835bSFan Fei writel_relaxed(BIT(hwirq), pcie->base + PCIE_INT_STATUS_REG);
615814cceebSJianjun Wang }
616814cceebSJianjun Wang
617814cceebSJianjun Wang static struct irq_chip mtk_intx_irq_chip = {
618814cceebSJianjun Wang .irq_mask = mtk_intx_mask,
619814cceebSJianjun Wang .irq_unmask = mtk_intx_unmask,
620814cceebSJianjun Wang .irq_eoi = mtk_intx_eoi,
621814cceebSJianjun Wang .irq_set_affinity = mtk_pcie_set_affinity,
622814cceebSJianjun Wang .name = "INTx",
623814cceebSJianjun Wang };
624814cceebSJianjun Wang
mtk_pcie_intx_map(struct irq_domain * domain,unsigned int irq,irq_hw_number_t hwirq)625814cceebSJianjun Wang static int mtk_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
626814cceebSJianjun Wang irq_hw_number_t hwirq)
627814cceebSJianjun Wang {
628814cceebSJianjun Wang irq_set_chip_data(irq, domain->host_data);
629814cceebSJianjun Wang irq_set_chip_and_handler_name(irq, &mtk_intx_irq_chip,
630814cceebSJianjun Wang handle_fasteoi_irq, "INTx");
631814cceebSJianjun Wang return 0;
632814cceebSJianjun Wang }
633814cceebSJianjun Wang
634814cceebSJianjun Wang static const struct irq_domain_ops intx_domain_ops = {
635814cceebSJianjun Wang .map = mtk_pcie_intx_map,
636814cceebSJianjun Wang };
637814cceebSJianjun Wang
mtk_pcie_init_irq_domains(struct mtk_gen3_pcie * pcie)638d5a4835bSFan Fei static int mtk_pcie_init_irq_domains(struct mtk_gen3_pcie *pcie)
639814cceebSJianjun Wang {
640d5a4835bSFan Fei struct device *dev = pcie->dev;
641814cceebSJianjun Wang struct device_node *intc_node, *node = dev->of_node;
6421bdafba5SJianjun Wang int ret;
643814cceebSJianjun Wang
644d5a4835bSFan Fei raw_spin_lock_init(&pcie->irq_lock);
645814cceebSJianjun Wang
646814cceebSJianjun Wang /* Setup INTx */
647814cceebSJianjun Wang intc_node = of_get_child_by_name(node, "interrupt-controller");
648814cceebSJianjun Wang if (!intc_node) {
649814cceebSJianjun Wang dev_err(dev, "missing interrupt-controller node\n");
650814cceebSJianjun Wang return -ENODEV;
651814cceebSJianjun Wang }
652814cceebSJianjun Wang
653d5a4835bSFan Fei pcie->intx_domain = irq_domain_add_linear(intc_node, PCI_NUM_INTX,
654d5a4835bSFan Fei &intx_domain_ops, pcie);
655d5a4835bSFan Fei if (!pcie->intx_domain) {
656814cceebSJianjun Wang dev_err(dev, "failed to create INTx IRQ domain\n");
657bf038503SMiaoqian Lin ret = -ENODEV;
658bf038503SMiaoqian Lin goto out_put_node;
659814cceebSJianjun Wang }
660814cceebSJianjun Wang
6611bdafba5SJianjun Wang /* Setup MSI */
662d5a4835bSFan Fei mutex_init(&pcie->lock);
6631bdafba5SJianjun Wang
664d5a4835bSFan Fei pcie->msi_bottom_domain = irq_domain_add_linear(node, PCIE_MSI_IRQS_NUM,
665d5a4835bSFan Fei &mtk_msi_bottom_domain_ops, pcie);
666d5a4835bSFan Fei if (!pcie->msi_bottom_domain) {
6671bdafba5SJianjun Wang dev_err(dev, "failed to create MSI bottom domain\n");
6681bdafba5SJianjun Wang ret = -ENODEV;
6691bdafba5SJianjun Wang goto err_msi_bottom_domain;
6701bdafba5SJianjun Wang }
6711bdafba5SJianjun Wang
672d5a4835bSFan Fei pcie->msi_domain = pci_msi_create_irq_domain(dev->fwnode,
6731bdafba5SJianjun Wang &mtk_msi_domain_info,
674d5a4835bSFan Fei pcie->msi_bottom_domain);
675d5a4835bSFan Fei if (!pcie->msi_domain) {
6761bdafba5SJianjun Wang dev_err(dev, "failed to create MSI domain\n");
6771bdafba5SJianjun Wang ret = -ENODEV;
6781bdafba5SJianjun Wang goto err_msi_domain;
6791bdafba5SJianjun Wang }
6801bdafba5SJianjun Wang
681bf038503SMiaoqian Lin of_node_put(intc_node);
682814cceebSJianjun Wang return 0;
6831bdafba5SJianjun Wang
6841bdafba5SJianjun Wang err_msi_domain:
685d5a4835bSFan Fei irq_domain_remove(pcie->msi_bottom_domain);
6861bdafba5SJianjun Wang err_msi_bottom_domain:
687d5a4835bSFan Fei irq_domain_remove(pcie->intx_domain);
688bf038503SMiaoqian Lin out_put_node:
689bf038503SMiaoqian Lin of_node_put(intc_node);
6901bdafba5SJianjun Wang return ret;
691814cceebSJianjun Wang }
692814cceebSJianjun Wang
mtk_pcie_irq_teardown(struct mtk_gen3_pcie * pcie)693d5a4835bSFan Fei static void mtk_pcie_irq_teardown(struct mtk_gen3_pcie *pcie)
694814cceebSJianjun Wang {
695d5a4835bSFan Fei irq_set_chained_handler_and_data(pcie->irq, NULL, NULL);
696814cceebSJianjun Wang
697d5a4835bSFan Fei if (pcie->intx_domain)
698d5a4835bSFan Fei irq_domain_remove(pcie->intx_domain);
699814cceebSJianjun Wang
700d5a4835bSFan Fei if (pcie->msi_domain)
701d5a4835bSFan Fei irq_domain_remove(pcie->msi_domain);
7021bdafba5SJianjun Wang
703d5a4835bSFan Fei if (pcie->msi_bottom_domain)
704d5a4835bSFan Fei irq_domain_remove(pcie->msi_bottom_domain);
7051bdafba5SJianjun Wang
706d5a4835bSFan Fei irq_dispose_mapping(pcie->irq);
707814cceebSJianjun Wang }
708814cceebSJianjun Wang
mtk_pcie_msi_handler(struct mtk_gen3_pcie * pcie,int set_idx)709d5a4835bSFan Fei static void mtk_pcie_msi_handler(struct mtk_gen3_pcie *pcie, int set_idx)
7101bdafba5SJianjun Wang {
711d5a4835bSFan Fei struct mtk_msi_set *msi_set = &pcie->msi_sets[set_idx];
7121bdafba5SJianjun Wang unsigned long msi_enable, msi_status;
7131bdafba5SJianjun Wang irq_hw_number_t bit, hwirq;
7141bdafba5SJianjun Wang
7151bdafba5SJianjun Wang msi_enable = readl_relaxed(msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET);
7161bdafba5SJianjun Wang
7171bdafba5SJianjun Wang do {
7181bdafba5SJianjun Wang msi_status = readl_relaxed(msi_set->base +
7191bdafba5SJianjun Wang PCIE_MSI_SET_STATUS_OFFSET);
7201bdafba5SJianjun Wang msi_status &= msi_enable;
7211bdafba5SJianjun Wang if (!msi_status)
7221bdafba5SJianjun Wang break;
7231bdafba5SJianjun Wang
7241bdafba5SJianjun Wang for_each_set_bit(bit, &msi_status, PCIE_MSI_IRQS_PER_SET) {
7251bdafba5SJianjun Wang hwirq = bit + set_idx * PCIE_MSI_IRQS_PER_SET;
726d5a4835bSFan Fei generic_handle_domain_irq(pcie->msi_bottom_domain, hwirq);
7271bdafba5SJianjun Wang }
7281bdafba5SJianjun Wang } while (true);
7291bdafba5SJianjun Wang }
7301bdafba5SJianjun Wang
mtk_pcie_irq_handler(struct irq_desc * desc)731814cceebSJianjun Wang static void mtk_pcie_irq_handler(struct irq_desc *desc)
732814cceebSJianjun Wang {
733d5a4835bSFan Fei struct mtk_gen3_pcie *pcie = irq_desc_get_handler_data(desc);
734814cceebSJianjun Wang struct irq_chip *irqchip = irq_desc_get_chip(desc);
735814cceebSJianjun Wang unsigned long status;
736814cceebSJianjun Wang irq_hw_number_t irq_bit = PCIE_INTX_SHIFT;
737814cceebSJianjun Wang
738814cceebSJianjun Wang chained_irq_enter(irqchip, desc);
739814cceebSJianjun Wang
740d5a4835bSFan Fei status = readl_relaxed(pcie->base + PCIE_INT_STATUS_REG);
741814cceebSJianjun Wang for_each_set_bit_from(irq_bit, &status, PCI_NUM_INTX +
742d21faba1SMarc Zyngier PCIE_INTX_SHIFT)
743d5a4835bSFan Fei generic_handle_domain_irq(pcie->intx_domain,
744814cceebSJianjun Wang irq_bit - PCIE_INTX_SHIFT);
745814cceebSJianjun Wang
7461bdafba5SJianjun Wang irq_bit = PCIE_MSI_SHIFT;
7471bdafba5SJianjun Wang for_each_set_bit_from(irq_bit, &status, PCIE_MSI_SET_NUM +
7481bdafba5SJianjun Wang PCIE_MSI_SHIFT) {
749d5a4835bSFan Fei mtk_pcie_msi_handler(pcie, irq_bit - PCIE_MSI_SHIFT);
7501bdafba5SJianjun Wang
751d5a4835bSFan Fei writel_relaxed(BIT(irq_bit), pcie->base + PCIE_INT_STATUS_REG);
7521bdafba5SJianjun Wang }
7531bdafba5SJianjun Wang
754814cceebSJianjun Wang chained_irq_exit(irqchip, desc);
755814cceebSJianjun Wang }
756814cceebSJianjun Wang
mtk_pcie_setup_irq(struct mtk_gen3_pcie * pcie)757d5a4835bSFan Fei static int mtk_pcie_setup_irq(struct mtk_gen3_pcie *pcie)
758814cceebSJianjun Wang {
759d5a4835bSFan Fei struct device *dev = pcie->dev;
760814cceebSJianjun Wang struct platform_device *pdev = to_platform_device(dev);
761814cceebSJianjun Wang int err;
762814cceebSJianjun Wang
763d5a4835bSFan Fei err = mtk_pcie_init_irq_domains(pcie);
764814cceebSJianjun Wang if (err)
765814cceebSJianjun Wang return err;
766814cceebSJianjun Wang
767d5a4835bSFan Fei pcie->irq = platform_get_irq(pdev, 0);
768d5a4835bSFan Fei if (pcie->irq < 0)
769d5a4835bSFan Fei return pcie->irq;
770814cceebSJianjun Wang
771d5a4835bSFan Fei irq_set_chained_handler_and_data(pcie->irq, mtk_pcie_irq_handler, pcie);
772814cceebSJianjun Wang
773814cceebSJianjun Wang return 0;
774814cceebSJianjun Wang }
775814cceebSJianjun Wang
mtk_pcie_parse_port(struct mtk_gen3_pcie * pcie)776d5a4835bSFan Fei static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pcie)
777d3bf75b5SJianjun Wang {
778d5a4835bSFan Fei struct device *dev = pcie->dev;
779d3bf75b5SJianjun Wang struct platform_device *pdev = to_platform_device(dev);
780d3bf75b5SJianjun Wang struct resource *regs;
781d3bf75b5SJianjun Wang int ret;
782d3bf75b5SJianjun Wang
783d3bf75b5SJianjun Wang regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcie-mac");
784d3bf75b5SJianjun Wang if (!regs)
785d3bf75b5SJianjun Wang return -EINVAL;
786d5a4835bSFan Fei pcie->base = devm_ioremap_resource(dev, regs);
787d5a4835bSFan Fei if (IS_ERR(pcie->base)) {
788d3bf75b5SJianjun Wang dev_err(dev, "failed to map register base\n");
789d5a4835bSFan Fei return PTR_ERR(pcie->base);
790d3bf75b5SJianjun Wang }
791d3bf75b5SJianjun Wang
792d5a4835bSFan Fei pcie->reg_base = regs->start;
793d3bf75b5SJianjun Wang
794d5a4835bSFan Fei pcie->phy_reset = devm_reset_control_get_optional_exclusive(dev, "phy");
795d5a4835bSFan Fei if (IS_ERR(pcie->phy_reset)) {
796d5a4835bSFan Fei ret = PTR_ERR(pcie->phy_reset);
797d3bf75b5SJianjun Wang if (ret != -EPROBE_DEFER)
798d3bf75b5SJianjun Wang dev_err(dev, "failed to get PHY reset\n");
799d3bf75b5SJianjun Wang
800d3bf75b5SJianjun Wang return ret;
801d3bf75b5SJianjun Wang }
802d3bf75b5SJianjun Wang
803d5a4835bSFan Fei pcie->mac_reset = devm_reset_control_get_optional_exclusive(dev, "mac");
804d5a4835bSFan Fei if (IS_ERR(pcie->mac_reset)) {
805d5a4835bSFan Fei ret = PTR_ERR(pcie->mac_reset);
806d3bf75b5SJianjun Wang if (ret != -EPROBE_DEFER)
807d3bf75b5SJianjun Wang dev_err(dev, "failed to get MAC reset\n");
808d3bf75b5SJianjun Wang
809d3bf75b5SJianjun Wang return ret;
810d3bf75b5SJianjun Wang }
811d3bf75b5SJianjun Wang
812d5a4835bSFan Fei pcie->phy = devm_phy_optional_get(dev, "pcie-phy");
813d5a4835bSFan Fei if (IS_ERR(pcie->phy)) {
814d5a4835bSFan Fei ret = PTR_ERR(pcie->phy);
815d3bf75b5SJianjun Wang if (ret != -EPROBE_DEFER)
816d3bf75b5SJianjun Wang dev_err(dev, "failed to get PHY\n");
817d3bf75b5SJianjun Wang
818d3bf75b5SJianjun Wang return ret;
819d3bf75b5SJianjun Wang }
820d3bf75b5SJianjun Wang
821d5a4835bSFan Fei pcie->num_clks = devm_clk_bulk_get_all(dev, &pcie->clks);
822d5a4835bSFan Fei if (pcie->num_clks < 0) {
823d3bf75b5SJianjun Wang dev_err(dev, "failed to get clocks\n");
824d5a4835bSFan Fei return pcie->num_clks;
825d3bf75b5SJianjun Wang }
826d3bf75b5SJianjun Wang
827d3bf75b5SJianjun Wang return 0;
828d3bf75b5SJianjun Wang }
829d3bf75b5SJianjun Wang
mtk_pcie_power_up(struct mtk_gen3_pcie * pcie)830d5a4835bSFan Fei static int mtk_pcie_power_up(struct mtk_gen3_pcie *pcie)
831d3bf75b5SJianjun Wang {
832d5a4835bSFan Fei struct device *dev = pcie->dev;
833d3bf75b5SJianjun Wang int err;
834d3bf75b5SJianjun Wang
835d3bf75b5SJianjun Wang /* PHY power on and enable pipe clock */
836d5a4835bSFan Fei reset_control_deassert(pcie->phy_reset);
837d3bf75b5SJianjun Wang
838d5a4835bSFan Fei err = phy_init(pcie->phy);
839d3bf75b5SJianjun Wang if (err) {
840d3bf75b5SJianjun Wang dev_err(dev, "failed to initialize PHY\n");
841d3bf75b5SJianjun Wang goto err_phy_init;
842d3bf75b5SJianjun Wang }
843d3bf75b5SJianjun Wang
844d5a4835bSFan Fei err = phy_power_on(pcie->phy);
845d3bf75b5SJianjun Wang if (err) {
846d3bf75b5SJianjun Wang dev_err(dev, "failed to power on PHY\n");
847d3bf75b5SJianjun Wang goto err_phy_on;
848d3bf75b5SJianjun Wang }
849d3bf75b5SJianjun Wang
850d3bf75b5SJianjun Wang /* MAC power on and enable transaction layer clocks */
851d5a4835bSFan Fei reset_control_deassert(pcie->mac_reset);
852d3bf75b5SJianjun Wang
853d3bf75b5SJianjun Wang pm_runtime_enable(dev);
854d3bf75b5SJianjun Wang pm_runtime_get_sync(dev);
855d3bf75b5SJianjun Wang
856d5a4835bSFan Fei err = clk_bulk_prepare_enable(pcie->num_clks, pcie->clks);
857d3bf75b5SJianjun Wang if (err) {
858d3bf75b5SJianjun Wang dev_err(dev, "failed to enable clocks\n");
859d3bf75b5SJianjun Wang goto err_clk_init;
860d3bf75b5SJianjun Wang }
861d3bf75b5SJianjun Wang
862d3bf75b5SJianjun Wang return 0;
863d3bf75b5SJianjun Wang
864d3bf75b5SJianjun Wang err_clk_init:
865d3bf75b5SJianjun Wang pm_runtime_put_sync(dev);
866d3bf75b5SJianjun Wang pm_runtime_disable(dev);
867d5a4835bSFan Fei reset_control_assert(pcie->mac_reset);
868d5a4835bSFan Fei phy_power_off(pcie->phy);
869d3bf75b5SJianjun Wang err_phy_on:
870d5a4835bSFan Fei phy_exit(pcie->phy);
871d3bf75b5SJianjun Wang err_phy_init:
872d5a4835bSFan Fei reset_control_assert(pcie->phy_reset);
873d3bf75b5SJianjun Wang
874d3bf75b5SJianjun Wang return err;
875d3bf75b5SJianjun Wang }
876d3bf75b5SJianjun Wang
mtk_pcie_power_down(struct mtk_gen3_pcie * pcie)877d5a4835bSFan Fei static void mtk_pcie_power_down(struct mtk_gen3_pcie *pcie)
878d3bf75b5SJianjun Wang {
879d5a4835bSFan Fei clk_bulk_disable_unprepare(pcie->num_clks, pcie->clks);
880d3bf75b5SJianjun Wang
881d5a4835bSFan Fei pm_runtime_put_sync(pcie->dev);
882d5a4835bSFan Fei pm_runtime_disable(pcie->dev);
883d5a4835bSFan Fei reset_control_assert(pcie->mac_reset);
884d3bf75b5SJianjun Wang
885d5a4835bSFan Fei phy_power_off(pcie->phy);
886d5a4835bSFan Fei phy_exit(pcie->phy);
887d5a4835bSFan Fei reset_control_assert(pcie->phy_reset);
888d3bf75b5SJianjun Wang }
889d3bf75b5SJianjun Wang
mtk_pcie_setup(struct mtk_gen3_pcie * pcie)890d5a4835bSFan Fei static int mtk_pcie_setup(struct mtk_gen3_pcie *pcie)
891d3bf75b5SJianjun Wang {
892d3bf75b5SJianjun Wang int err;
893d3bf75b5SJianjun Wang
894d5a4835bSFan Fei err = mtk_pcie_parse_port(pcie);
895d3bf75b5SJianjun Wang if (err)
896d3bf75b5SJianjun Wang return err;
897d3bf75b5SJianjun Wang
8981d565935SAngeloGioacchino Del Regno /*
8991d565935SAngeloGioacchino Del Regno * The controller may have been left out of reset by the bootloader
9001d565935SAngeloGioacchino Del Regno * so make sure that we get a clean start by asserting resets here.
9011d565935SAngeloGioacchino Del Regno */
9021d565935SAngeloGioacchino Del Regno reset_control_assert(pcie->phy_reset);
9031d565935SAngeloGioacchino Del Regno reset_control_assert(pcie->mac_reset);
9041d565935SAngeloGioacchino Del Regno usleep_range(10, 20);
9051d565935SAngeloGioacchino Del Regno
906d3bf75b5SJianjun Wang /* Don't touch the hardware registers before power up */
907d5a4835bSFan Fei err = mtk_pcie_power_up(pcie);
908d3bf75b5SJianjun Wang if (err)
909d3bf75b5SJianjun Wang return err;
910d3bf75b5SJianjun Wang
911d3bf75b5SJianjun Wang /* Try link up */
912d5a4835bSFan Fei err = mtk_pcie_startup_port(pcie);
913d3bf75b5SJianjun Wang if (err)
914d3bf75b5SJianjun Wang goto err_setup;
915d3bf75b5SJianjun Wang
916d5a4835bSFan Fei err = mtk_pcie_setup_irq(pcie);
917814cceebSJianjun Wang if (err)
918814cceebSJianjun Wang goto err_setup;
919814cceebSJianjun Wang
920d3bf75b5SJianjun Wang return 0;
921d3bf75b5SJianjun Wang
922d3bf75b5SJianjun Wang err_setup:
923d5a4835bSFan Fei mtk_pcie_power_down(pcie);
924d3bf75b5SJianjun Wang
925d3bf75b5SJianjun Wang return err;
926d3bf75b5SJianjun Wang }
927d3bf75b5SJianjun Wang
mtk_pcie_probe(struct platform_device * pdev)928d3bf75b5SJianjun Wang static int mtk_pcie_probe(struct platform_device *pdev)
929d3bf75b5SJianjun Wang {
930d3bf75b5SJianjun Wang struct device *dev = &pdev->dev;
931d5a4835bSFan Fei struct mtk_gen3_pcie *pcie;
932d3bf75b5SJianjun Wang struct pci_host_bridge *host;
933d3bf75b5SJianjun Wang int err;
934d3bf75b5SJianjun Wang
935d5a4835bSFan Fei host = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
936d3bf75b5SJianjun Wang if (!host)
937d3bf75b5SJianjun Wang return -ENOMEM;
938d3bf75b5SJianjun Wang
939d5a4835bSFan Fei pcie = pci_host_bridge_priv(host);
940d3bf75b5SJianjun Wang
941d5a4835bSFan Fei pcie->dev = dev;
942d5a4835bSFan Fei platform_set_drvdata(pdev, pcie);
943d3bf75b5SJianjun Wang
944d5a4835bSFan Fei err = mtk_pcie_setup(pcie);
945d3bf75b5SJianjun Wang if (err)
946d3bf75b5SJianjun Wang return err;
947d3bf75b5SJianjun Wang
948d3bf75b5SJianjun Wang host->ops = &mtk_pcie_ops;
949d5a4835bSFan Fei host->sysdata = pcie;
950d3bf75b5SJianjun Wang
951d3bf75b5SJianjun Wang err = pci_host_probe(host);
952d3bf75b5SJianjun Wang if (err) {
953d5a4835bSFan Fei mtk_pcie_irq_teardown(pcie);
954d5a4835bSFan Fei mtk_pcie_power_down(pcie);
955d3bf75b5SJianjun Wang return err;
956d3bf75b5SJianjun Wang }
957d3bf75b5SJianjun Wang
958d3bf75b5SJianjun Wang return 0;
959d3bf75b5SJianjun Wang }
960d3bf75b5SJianjun Wang
mtk_pcie_remove(struct platform_device * pdev)96122626c46SUwe Kleine-König static void mtk_pcie_remove(struct platform_device *pdev)
962d3bf75b5SJianjun Wang {
963d5a4835bSFan Fei struct mtk_gen3_pcie *pcie = platform_get_drvdata(pdev);
964d5a4835bSFan Fei struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
965d3bf75b5SJianjun Wang
966d3bf75b5SJianjun Wang pci_lock_rescan_remove();
967d3bf75b5SJianjun Wang pci_stop_root_bus(host->bus);
968d3bf75b5SJianjun Wang pci_remove_root_bus(host->bus);
969d3bf75b5SJianjun Wang pci_unlock_rescan_remove();
970d3bf75b5SJianjun Wang
971d5a4835bSFan Fei mtk_pcie_irq_teardown(pcie);
972d5a4835bSFan Fei mtk_pcie_power_down(pcie);
973d3bf75b5SJianjun Wang }
974d3bf75b5SJianjun Wang
mtk_pcie_irq_save(struct mtk_gen3_pcie * pcie)97519b7858cSBjorn Helgaas static void mtk_pcie_irq_save(struct mtk_gen3_pcie *pcie)
976d537dc12SJianjun Wang {
977d537dc12SJianjun Wang int i;
978d537dc12SJianjun Wang
979d5a4835bSFan Fei raw_spin_lock(&pcie->irq_lock);
980d537dc12SJianjun Wang
981d5a4835bSFan Fei pcie->saved_irq_state = readl_relaxed(pcie->base + PCIE_INT_ENABLE_REG);
982d537dc12SJianjun Wang
983d537dc12SJianjun Wang for (i = 0; i < PCIE_MSI_SET_NUM; i++) {
984d5a4835bSFan Fei struct mtk_msi_set *msi_set = &pcie->msi_sets[i];
985d537dc12SJianjun Wang
986d537dc12SJianjun Wang msi_set->saved_irq_state = readl_relaxed(msi_set->base +
987d537dc12SJianjun Wang PCIE_MSI_SET_ENABLE_OFFSET);
988d537dc12SJianjun Wang }
989d537dc12SJianjun Wang
990d5a4835bSFan Fei raw_spin_unlock(&pcie->irq_lock);
991d537dc12SJianjun Wang }
992d537dc12SJianjun Wang
mtk_pcie_irq_restore(struct mtk_gen3_pcie * pcie)99319b7858cSBjorn Helgaas static void mtk_pcie_irq_restore(struct mtk_gen3_pcie *pcie)
994d537dc12SJianjun Wang {
995d537dc12SJianjun Wang int i;
996d537dc12SJianjun Wang
997d5a4835bSFan Fei raw_spin_lock(&pcie->irq_lock);
998d537dc12SJianjun Wang
999d5a4835bSFan Fei writel_relaxed(pcie->saved_irq_state, pcie->base + PCIE_INT_ENABLE_REG);
1000d537dc12SJianjun Wang
1001d537dc12SJianjun Wang for (i = 0; i < PCIE_MSI_SET_NUM; i++) {
1002d5a4835bSFan Fei struct mtk_msi_set *msi_set = &pcie->msi_sets[i];
1003d537dc12SJianjun Wang
1004d537dc12SJianjun Wang writel_relaxed(msi_set->saved_irq_state,
1005d537dc12SJianjun Wang msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET);
1006d537dc12SJianjun Wang }
1007d537dc12SJianjun Wang
1008d5a4835bSFan Fei raw_spin_unlock(&pcie->irq_lock);
1009d537dc12SJianjun Wang }
1010d537dc12SJianjun Wang
mtk_pcie_turn_off_link(struct mtk_gen3_pcie * pcie)101119b7858cSBjorn Helgaas static int mtk_pcie_turn_off_link(struct mtk_gen3_pcie *pcie)
1012d537dc12SJianjun Wang {
1013d537dc12SJianjun Wang u32 val;
1014d537dc12SJianjun Wang
1015d5a4835bSFan Fei val = readl_relaxed(pcie->base + PCIE_ICMD_PM_REG);
1016d537dc12SJianjun Wang val |= PCIE_TURN_OFF_LINK;
1017d5a4835bSFan Fei writel_relaxed(val, pcie->base + PCIE_ICMD_PM_REG);
1018d537dc12SJianjun Wang
1019d537dc12SJianjun Wang /* Check the link is L2 */
1020d5a4835bSFan Fei return readl_poll_timeout(pcie->base + PCIE_LTSSM_STATUS_REG, val,
1021d537dc12SJianjun Wang (PCIE_LTSSM_STATE(val) ==
1022d537dc12SJianjun Wang PCIE_LTSSM_STATE_L2_IDLE), 20,
1023d537dc12SJianjun Wang 50 * USEC_PER_MSEC);
1024d537dc12SJianjun Wang }
1025d537dc12SJianjun Wang
mtk_pcie_suspend_noirq(struct device * dev)102619b7858cSBjorn Helgaas static int mtk_pcie_suspend_noirq(struct device *dev)
1027d537dc12SJianjun Wang {
1028d5a4835bSFan Fei struct mtk_gen3_pcie *pcie = dev_get_drvdata(dev);
1029d537dc12SJianjun Wang int err;
1030d537dc12SJianjun Wang u32 val;
1031d537dc12SJianjun Wang
1032d537dc12SJianjun Wang /* Trigger link to L2 state */
1033d5a4835bSFan Fei err = mtk_pcie_turn_off_link(pcie);
1034d537dc12SJianjun Wang if (err) {
1035d5a4835bSFan Fei dev_err(pcie->dev, "cannot enter L2 state\n");
1036d537dc12SJianjun Wang return err;
1037d537dc12SJianjun Wang }
1038d537dc12SJianjun Wang
1039d537dc12SJianjun Wang /* Pull down the PERST# pin */
1040d5a4835bSFan Fei val = readl_relaxed(pcie->base + PCIE_RST_CTRL_REG);
1041d537dc12SJianjun Wang val |= PCIE_PE_RSTB;
1042d5a4835bSFan Fei writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
1043d537dc12SJianjun Wang
1044d5a4835bSFan Fei dev_dbg(pcie->dev, "entered L2 states successfully");
1045d537dc12SJianjun Wang
1046d5a4835bSFan Fei mtk_pcie_irq_save(pcie);
1047d5a4835bSFan Fei mtk_pcie_power_down(pcie);
1048d537dc12SJianjun Wang
1049d537dc12SJianjun Wang return 0;
1050d537dc12SJianjun Wang }
1051d537dc12SJianjun Wang
mtk_pcie_resume_noirq(struct device * dev)105219b7858cSBjorn Helgaas static int mtk_pcie_resume_noirq(struct device *dev)
1053d537dc12SJianjun Wang {
1054d5a4835bSFan Fei struct mtk_gen3_pcie *pcie = dev_get_drvdata(dev);
1055d537dc12SJianjun Wang int err;
1056d537dc12SJianjun Wang
1057d5a4835bSFan Fei err = mtk_pcie_power_up(pcie);
1058d537dc12SJianjun Wang if (err)
1059d537dc12SJianjun Wang return err;
1060d537dc12SJianjun Wang
1061d5a4835bSFan Fei err = mtk_pcie_startup_port(pcie);
1062d537dc12SJianjun Wang if (err) {
1063d5a4835bSFan Fei mtk_pcie_power_down(pcie);
1064d537dc12SJianjun Wang return err;
1065d537dc12SJianjun Wang }
1066d537dc12SJianjun Wang
1067d5a4835bSFan Fei mtk_pcie_irq_restore(pcie);
1068d537dc12SJianjun Wang
1069d537dc12SJianjun Wang return 0;
1070d537dc12SJianjun Wang }
1071d537dc12SJianjun Wang
1072d537dc12SJianjun Wang static const struct dev_pm_ops mtk_pcie_pm_ops = {
107319b7858cSBjorn Helgaas NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_pcie_suspend_noirq,
1074d537dc12SJianjun Wang mtk_pcie_resume_noirq)
1075d537dc12SJianjun Wang };
1076d537dc12SJianjun Wang
1077d3bf75b5SJianjun Wang static const struct of_device_id mtk_pcie_of_match[] = {
1078d3bf75b5SJianjun Wang { .compatible = "mediatek,mt8192-pcie" },
1079d3bf75b5SJianjun Wang {},
1080d3bf75b5SJianjun Wang };
10813a2e476dSZou Wei MODULE_DEVICE_TABLE(of, mtk_pcie_of_match);
1082d3bf75b5SJianjun Wang
1083d3bf75b5SJianjun Wang static struct platform_driver mtk_pcie_driver = {
1084d3bf75b5SJianjun Wang .probe = mtk_pcie_probe,
108522626c46SUwe Kleine-König .remove_new = mtk_pcie_remove,
1086d3bf75b5SJianjun Wang .driver = {
1087034fdac0SFelix Fietkau .name = "mtk-pcie-gen3",
1088d3bf75b5SJianjun Wang .of_match_table = mtk_pcie_of_match,
1089d537dc12SJianjun Wang .pm = &mtk_pcie_pm_ops,
1090d3bf75b5SJianjun Wang },
1091d3bf75b5SJianjun Wang };
1092d3bf75b5SJianjun Wang
1093d3bf75b5SJianjun Wang module_platform_driver(mtk_pcie_driver);
1094d3bf75b5SJianjun Wang MODULE_LICENSE("GPL v2");
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