107ca255eSJianjun Wang# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 207ca255eSJianjun Wang%YAML 1.2 307ca255eSJianjun Wang--- 407ca255eSJianjun Wang$id: http://devicetree.org/schemas/pci/mediatek-pcie-gen3.yaml# 507ca255eSJianjun Wang$schema: http://devicetree.org/meta-schemas/core.yaml# 607ca255eSJianjun Wang 707ca255eSJianjun Wangtitle: Gen3 PCIe controller on MediaTek SoCs 807ca255eSJianjun Wang 907ca255eSJianjun Wangmaintainers: 1007ca255eSJianjun Wang - Jianjun Wang <jianjun.wang@mediatek.com> 1107ca255eSJianjun Wang 1207ca255eSJianjun Wangdescription: |+ 1307ca255eSJianjun Wang PCIe Gen3 MAC controller for MediaTek SoCs, it supports Gen3 speed 1407ca255eSJianjun Wang and compatible with Gen2, Gen1 speed. 1507ca255eSJianjun Wang 1607ca255eSJianjun Wang This PCIe controller supports up to 256 MSI vectors, the MSI hardware 1707ca255eSJianjun Wang block diagram is as follows: 1807ca255eSJianjun Wang 1907ca255eSJianjun Wang +-----+ 2007ca255eSJianjun Wang | GIC | 2107ca255eSJianjun Wang +-----+ 2207ca255eSJianjun Wang ^ 2307ca255eSJianjun Wang | 2407ca255eSJianjun Wang port->irq 2507ca255eSJianjun Wang | 2607ca255eSJianjun Wang +-+-+-+-+-+-+-+-+ 2707ca255eSJianjun Wang |0|1|2|3|4|5|6|7| (PCIe intc) 2807ca255eSJianjun Wang +-+-+-+-+-+-+-+-+ 2907ca255eSJianjun Wang ^ ^ ^ 3007ca255eSJianjun Wang | | ... | 3107ca255eSJianjun Wang +-------+ +------+ +-----------+ 3207ca255eSJianjun Wang | | | 3307ca255eSJianjun Wang +-+-+---+--+--+ +-+-+---+--+--+ +-+-+---+--+--+ 3407ca255eSJianjun Wang |0|1|...|30|31| |0|1|...|30|31| |0|1|...|30|31| (MSI sets) 3507ca255eSJianjun Wang +-+-+---+--+--+ +-+-+---+--+--+ +-+-+---+--+--+ 3607ca255eSJianjun Wang ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 3707ca255eSJianjun Wang | | | | | | | | | | | | (MSI vectors) 3807ca255eSJianjun Wang | | | | | | | | | | | | 3907ca255eSJianjun Wang 4007ca255eSJianjun Wang (MSI SET0) (MSI SET1) ... (MSI SET7) 4107ca255eSJianjun Wang 4207ca255eSJianjun Wang With 256 MSI vectors supported, the MSI vectors are composed of 8 sets, 4307ca255eSJianjun Wang each set has its own address for MSI message, and supports 32 MSI vectors 4407ca255eSJianjun Wang to generate interrupt. 4507ca255eSJianjun Wang 4607ca255eSJianjun Wangproperties: 4707ca255eSJianjun Wang compatible: 487f08e806SJianjun Wang oneOf: 497f08e806SJianjun Wang - items: 507f08e806SJianjun Wang - enum: 51*d3fd0ee7SFrank Wunderlich - mediatek,mt7986-pcie 527f08e806SJianjun Wang - mediatek,mt8188-pcie 537f08e806SJianjun Wang - mediatek,mt8195-pcie 547f08e806SJianjun Wang - const: mediatek,mt8192-pcie 557f08e806SJianjun Wang - const: mediatek,mt8192-pcie 5607ca255eSJianjun Wang 5707ca255eSJianjun Wang reg: 5807ca255eSJianjun Wang maxItems: 1 5907ca255eSJianjun Wang 6007ca255eSJianjun Wang reg-names: 6107ca255eSJianjun Wang items: 6207ca255eSJianjun Wang - const: pcie-mac 6307ca255eSJianjun Wang 6407ca255eSJianjun Wang interrupts: 6507ca255eSJianjun Wang maxItems: 1 6607ca255eSJianjun Wang 6707ca255eSJianjun Wang ranges: 6807ca255eSJianjun Wang minItems: 1 6907ca255eSJianjun Wang maxItems: 8 7007ca255eSJianjun Wang 71c9bfd858SJianjun Wang iommu-map: 72c9bfd858SJianjun Wang maxItems: 1 73c9bfd858SJianjun Wang 74c9bfd858SJianjun Wang iommu-map-mask: 75c9bfd858SJianjun Wang const: 0 76c9bfd858SJianjun Wang 7707ca255eSJianjun Wang resets: 7807ca255eSJianjun Wang minItems: 1 7907ca255eSJianjun Wang maxItems: 2 8007ca255eSJianjun Wang 8107ca255eSJianjun Wang reset-names: 8207ca255eSJianjun Wang minItems: 1 83c9bfd858SJianjun Wang maxItems: 2 8407ca255eSJianjun Wang items: 85c9bfd858SJianjun Wang enum: [ phy, mac ] 8607ca255eSJianjun Wang 8707ca255eSJianjun Wang clocks: 88*d3fd0ee7SFrank Wunderlich minItems: 4 8907ca255eSJianjun Wang maxItems: 6 9007ca255eSJianjun Wang 9107ca255eSJianjun Wang clock-names: 92*d3fd0ee7SFrank Wunderlich minItems: 4 93ec9eaf68SFrank Wunderlich maxItems: 6 9407ca255eSJianjun Wang 9507ca255eSJianjun Wang assigned-clocks: 9607ca255eSJianjun Wang maxItems: 1 9707ca255eSJianjun Wang 9807ca255eSJianjun Wang assigned-clock-parents: 9907ca255eSJianjun Wang maxItems: 1 10007ca255eSJianjun Wang 10107ca255eSJianjun Wang phys: 10207ca255eSJianjun Wang maxItems: 1 10307ca255eSJianjun Wang 104dcd49679SRob Herring phy-names: 105dcd49679SRob Herring items: 106dcd49679SRob Herring - const: pcie-phy 107dcd49679SRob Herring 108c9bfd858SJianjun Wang power-domains: 109c9bfd858SJianjun Wang maxItems: 1 110c9bfd858SJianjun Wang 11107ca255eSJianjun Wang '#interrupt-cells': 11207ca255eSJianjun Wang const: 1 11307ca255eSJianjun Wang 11407ca255eSJianjun Wang interrupt-controller: 11507ca255eSJianjun Wang description: Interrupt controller node for handling legacy PCI interrupts. 11607ca255eSJianjun Wang type: object 11707ca255eSJianjun Wang properties: 11807ca255eSJianjun Wang '#address-cells': 11907ca255eSJianjun Wang const: 0 12007ca255eSJianjun Wang '#interrupt-cells': 12107ca255eSJianjun Wang const: 1 12207ca255eSJianjun Wang interrupt-controller: true 12307ca255eSJianjun Wang 12407ca255eSJianjun Wang required: 12507ca255eSJianjun Wang - '#address-cells' 12607ca255eSJianjun Wang - '#interrupt-cells' 12707ca255eSJianjun Wang - interrupt-controller 12807ca255eSJianjun Wang 12907ca255eSJianjun Wang additionalProperties: false 13007ca255eSJianjun Wang 13107ca255eSJianjun Wangrequired: 13207ca255eSJianjun Wang - compatible 13307ca255eSJianjun Wang - reg 13407ca255eSJianjun Wang - reg-names 13507ca255eSJianjun Wang - interrupts 13607ca255eSJianjun Wang - ranges 13707ca255eSJianjun Wang - clocks 1387f08e806SJianjun Wang - clock-names 13907ca255eSJianjun Wang - '#interrupt-cells' 14007ca255eSJianjun Wang - interrupt-controller 14107ca255eSJianjun Wang 142ec9eaf68SFrank WunderlichallOf: 143ec9eaf68SFrank Wunderlich - $ref: /schemas/pci/pci-bus.yaml# 144ec9eaf68SFrank Wunderlich - if: 145ec9eaf68SFrank Wunderlich properties: 146ec9eaf68SFrank Wunderlich compatible: 147ec9eaf68SFrank Wunderlich const: mediatek,mt8192-pcie 148ec9eaf68SFrank Wunderlich then: 149ec9eaf68SFrank Wunderlich properties: 150ec9eaf68SFrank Wunderlich clock-names: 151ec9eaf68SFrank Wunderlich items: 152ec9eaf68SFrank Wunderlich - const: pl_250m 153ec9eaf68SFrank Wunderlich - const: tl_26m 154ec9eaf68SFrank Wunderlich - const: tl_96m 155ec9eaf68SFrank Wunderlich - const: tl_32k 156ec9eaf68SFrank Wunderlich - const: peri_26m 157ec9eaf68SFrank Wunderlich - const: top_133m 158ec9eaf68SFrank Wunderlich - if: 159ec9eaf68SFrank Wunderlich properties: 160ec9eaf68SFrank Wunderlich compatible: 161ec9eaf68SFrank Wunderlich contains: 162ec9eaf68SFrank Wunderlich enum: 163ec9eaf68SFrank Wunderlich - mediatek,mt8188-pcie 164ec9eaf68SFrank Wunderlich - mediatek,mt8195-pcie 165ec9eaf68SFrank Wunderlich then: 166ec9eaf68SFrank Wunderlich properties: 167ec9eaf68SFrank Wunderlich clock-names: 168ec9eaf68SFrank Wunderlich items: 169ec9eaf68SFrank Wunderlich - const: pl_250m 170ec9eaf68SFrank Wunderlich - const: tl_26m 171ec9eaf68SFrank Wunderlich - const: tl_96m 172ec9eaf68SFrank Wunderlich - const: tl_32k 173ec9eaf68SFrank Wunderlich - const: peri_26m 174ec9eaf68SFrank Wunderlich - const: peri_mem 175*d3fd0ee7SFrank Wunderlich - if: 176*d3fd0ee7SFrank Wunderlich properties: 177*d3fd0ee7SFrank Wunderlich compatible: 178*d3fd0ee7SFrank Wunderlich contains: 179*d3fd0ee7SFrank Wunderlich enum: 180*d3fd0ee7SFrank Wunderlich - mediatek,mt7986-pcie 181*d3fd0ee7SFrank Wunderlich then: 182*d3fd0ee7SFrank Wunderlich properties: 183*d3fd0ee7SFrank Wunderlich clock-names: 184*d3fd0ee7SFrank Wunderlich items: 185*d3fd0ee7SFrank Wunderlich - const: pl_250m 186*d3fd0ee7SFrank Wunderlich - const: tl_26m 187*d3fd0ee7SFrank Wunderlich - const: peri_26m 188*d3fd0ee7SFrank Wunderlich - const: top_133m 189ec9eaf68SFrank Wunderlich 19007ca255eSJianjun WangunevaluatedProperties: false 19107ca255eSJianjun Wang 19207ca255eSJianjun Wangexamples: 19307ca255eSJianjun Wang - | 19407ca255eSJianjun Wang #include <dt-bindings/interrupt-controller/arm-gic.h> 19507ca255eSJianjun Wang #include <dt-bindings/interrupt-controller/irq.h> 19607ca255eSJianjun Wang 19707ca255eSJianjun Wang bus { 19807ca255eSJianjun Wang #address-cells = <2>; 19907ca255eSJianjun Wang #size-cells = <2>; 20007ca255eSJianjun Wang 20107ca255eSJianjun Wang pcie: pcie@11230000 { 20207ca255eSJianjun Wang compatible = "mediatek,mt8192-pcie"; 20307ca255eSJianjun Wang device_type = "pci"; 20407ca255eSJianjun Wang #address-cells = <3>; 20507ca255eSJianjun Wang #size-cells = <2>; 20607ca255eSJianjun Wang reg = <0x00 0x11230000 0x00 0x4000>; 20707ca255eSJianjun Wang reg-names = "pcie-mac"; 20807ca255eSJianjun Wang interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>; 20907ca255eSJianjun Wang bus-range = <0x00 0xff>; 21007ca255eSJianjun Wang ranges = <0x82000000 0x00 0x12000000 0x00 21107ca255eSJianjun Wang 0x12000000 0x00 0x1000000>; 21207ca255eSJianjun Wang clocks = <&infracfg 44>, 21307ca255eSJianjun Wang <&infracfg 40>, 21407ca255eSJianjun Wang <&infracfg 43>, 21507ca255eSJianjun Wang <&infracfg 97>, 21607ca255eSJianjun Wang <&infracfg 99>, 21707ca255eSJianjun Wang <&infracfg 111>; 21807ca255eSJianjun Wang clock-names = "pl_250m", "tl_26m", "tl_96m", 21907ca255eSJianjun Wang "tl_32k", "peri_26m", "top_133m"; 22007ca255eSJianjun Wang assigned-clocks = <&topckgen 50>; 22107ca255eSJianjun Wang assigned-clock-parents = <&topckgen 91>; 22207ca255eSJianjun Wang 22307ca255eSJianjun Wang phys = <&pciephy>; 22407ca255eSJianjun Wang phy-names = "pcie-phy"; 22507ca255eSJianjun Wang 22607ca255eSJianjun Wang resets = <&infracfg_rst 2>, 22707ca255eSJianjun Wang <&infracfg_rst 3>; 22807ca255eSJianjun Wang reset-names = "phy", "mac"; 22907ca255eSJianjun Wang 23007ca255eSJianjun Wang #interrupt-cells = <1>; 23107ca255eSJianjun Wang interrupt-map-mask = <0 0 0 0x7>; 23207ca255eSJianjun Wang interrupt-map = <0 0 0 1 &pcie_intc 0>, 23307ca255eSJianjun Wang <0 0 0 2 &pcie_intc 1>, 23407ca255eSJianjun Wang <0 0 0 3 &pcie_intc 2>, 23507ca255eSJianjun Wang <0 0 0 4 &pcie_intc 3>; 23607ca255eSJianjun Wang pcie_intc: interrupt-controller { 23707ca255eSJianjun Wang #address-cells = <0>; 23807ca255eSJianjun Wang #interrupt-cells = <1>; 23907ca255eSJianjun Wang interrupt-controller; 24007ca255eSJianjun Wang }; 24107ca255eSJianjun Wang }; 24207ca255eSJianjun Wang }; 243