Lines Matching +full:pcie +full:- +full:mac
7 #define OTP_REG_RESERVED -1
8 #define OTP_REG_VALUE -2
9 #define OTP_REG_VALID_BIT -3
43 { 5, 1, 0, "MAC 1 : RMII/NCSI" },
44 { 5, 1, 1, "MAC 1 : RGMII" },
45 { 6, 1, 0, "MAC 2 : RMII/NCSI" },
46 { 6, 1, 1, "MAC 2 : RGMII" },
69 { 20, 1, 0, "Disable Pcie EHCI device" },
70 { 20, 1, 1, "Enable Pcie EHCI device" },
74 { 22, 1, 1, "Disable dedicated BMC functions for non-BMC application" },
76 { 23, 1, 1, "SSPRST# pin is for PCIE root complex dedicated reset pin" },
85 { 32, 1, 0, "MAC 3 : RMII/NCSI" },
86 { 32, 1, 1, "MAC 3 : RGMII" },
87 { 33, 1, 0, "MAC 4 : RMII/NCSI" },
88 { 33, 1, 1, "MAC 4 : RGMII" },
103 { 41, 1, 0, "Disable boot SPI 3B address mode auto-clear" },
104 { 41, 1, 1, "Enable boot SPI 3B address mode auto-clear" },
162 { 5, 1, 0, "MAC 1 : RMII/NCSI" },
163 { 5, 1, 1, "MAC 1 : RGMII" },
164 { 6, 1, 0, "MAC 2 : RMII/NCSI" },
165 { 6, 1, 1, "MAC 2 : RGMII" },
193 { 20, 1, 0, "Disable Pcie EHCI device" },
194 { 20, 1, 1, "Enable Pcie EHCI device" },
198 { 22, 1, 1, "Disable dedicated BMC functions for non-BMC application" },
200 { 23, 1, 1, "SSPRST# pin is for PCIE root complex dedicated reset pin" },
214 { 32, 1, 0, "MAC 3 : RMII/NCSI" },
215 { 32, 1, 1, "MAC 3 : RGMII" },
216 { 33, 1, 0, "MAC 4 : RMII/NCSI" },
217 { 33, 1, 1, "MAC 4 : RGMII" },
232 { 41, 1, 0, "Disable boot SPI 3B address mode auto-clear" },
233 { 41, 1, 1, "Enable boot SPI 3B address mode auto-clear" },
447 { 3, 18, 1, 0, "Enable Auto Boot from VUART2 over PCIE" },
448 { 3, 18, 1, 1, "Disable Auto Boot from VUART2 over PCIE" },
527 { 3, 18, 1, 0, "Enable Auto Boot from VUART2 over PCIE" },
528 { 3, 18, 1, 1, "Disable Auto Boot from VUART2 over PCIE" },
559 { 6, 1, "MAC 1 RMII mode" },
560 { 7, 1, "MAC 2 RMII mode" },
570 { 21, 1, "Enable PCIe EHCI" },
573 { 24, 1, "Enable dedicate PCIe RC reset" },
579 { 32, 1, "MAC 3 RMII mode" },
580 { 33, 1, "MAC 4 RMII mode" },
588 { 41, 1, "Enable boot SPI 3B address mode auto-clear" },