Home
last modified time | relevance | path

Searched +full:nand +full:- +full:ecc +full:- +full:opt (Results 1 – 25 of 82) sorted by relevance

1234

/openbmc/linux/Documentation/devicetree/bindings/mtd/
H A Dti,gpmc-nand.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/ti,gpmc-nand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Texas Instruments GPMC NAND Flash controller.
10 - Tony Lindgren <tony@atomide.com>
11 - Roger Quadros <rogerq@kernel.org>
14 GPMC NAND controller/Flash is represented as a child of the
20 - enum:
21 - ti,am64-nand
[all …]
/openbmc/linux/drivers/mtd/nand/raw/
H A Domap2.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/dma-mapping.h>
18 #include <linux/mtd/nand-ecc-sw-bch.h>
21 #include <linux/omap-dma.h>
29 #include <linux/omap-gpmc.h>
30 #include <linux/platform_data/mtd-nand-omap2.h>
32 #define DRIVER_NAME "omap2-nand"
122 /* GPMC ecc engine settings for read */
129 /* GPMC ecc engine settings for write */
145 struct nand_chip nand; member
[all …]
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Domap3-evm.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
5 /dts-v1/;
8 #include "omap3-evm-common.dtsi"
9 #include "omap3-evm-processor-common.dtsi"
13 compatible = "ti,omap3-evm", "ti,omap3430", "ti,omap3";
17 pinctrl-names = "default";
18 pinctrl-0 = <&hsusb2_2_pins>;
20 ehci_phy_pins: ehci-phy-pins {
21 pinctrl-single,pins = <
[all …]
H A Domap3-evm-37xx.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
5 /dts-v1/;
8 #include "omap3-evm-common.dtsi"
9 #include "omap3-evm-processor-common.dtsi"
13 compatible = "ti,omap3-evm-37xx", "ti,omap3630", "ti,omap3";
17 pinctrl-names = "default";
18 pinctrl-0 = <&hsusb2_2_pins>;
20 ehci_phy_pins: ehci-phy-pins {
21 pinctrl-single,pins = <
[all …]
H A Ddm8148-evm.dts1 // SPDX-License-Identifier: GPL-2.0-only
2 /dts-v1/;
5 #include <dt-bindings/interrupt-controller/irq.h>
9 compatible = "ti,dm8148-evm", "ti,dm8148", "ti,dm814";
18 compatible = "regulator-fixed";
19 regulator-name = "vmmcsd_fixed";
20 regulator-min-microvolt = <3300000>;
21 regulator-max-microvolt = <3300000>;
26 phy-handle = <&ethphy0>;
27 phy-mode = "rgmii-id";
[all …]
H A Ddra62x-j5eco-evm.dts1 // SPDX-License-Identifier: GPL-2.0-only
2 /dts-v1/;
5 #include <dt-bindings/interrupt-controller/irq.h>
9 compatible = "ti,dra62x-j5eco-evm", "ti,dra62x", "ti,dm8148", "ti,dm814";
18 compatible = "regulator-fixed";
19 regulator-name = "vmmcsd_fixed";
20 regulator-min-microvolt = <3300000>;
21 regulator-max-microvolt = <3300000>;
26 phy-handle = <&ethphy0>;
27 phy-mode = "rgmii-id";
[all …]
H A Dam335x-chilisom.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2015 Jablotron s.r.o. -- https://www.jablotron.com/
7 #include <dt-bindings/interrupt-controller/irq.h>
11 compatible = "grinn,am335x-chilisom", "ti,am33xx";
15 cpu0-supply = <&dcdc2_reg>;
26 pinctrl-names = "default";
28 i2c0_pins: i2c0-pins {
29 pinctrl-single,pins = <
35 nandflash_pins: nandflash-pins {
36 pinctrl-single,pins = <
[all …]
H A Domap3430-sdp.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
5 /dts-v1/;
11 compatible = "ti,omap3430-sdp", "ti,omap3430", "ti,omap3";
20 clock-frequency = <2600000>;
32 vmmc-supply = <&vmmc1>;
33 vqmmc-supply = <&vsim>;
35 * S6-3 must be in ON position for 8 bit mode to function
38 bus-width = <8>;
51 <1 0 0x28000000 0x1000000>, /* CS1: 16MB for NAND */
[all …]
H A Dlogicpd-torpedo-som.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 #include <dt-bindings/input/input.h>
7 stdout-path = &uart1;
12 cpu0-supply = <&vcc>;
22 compatible = "gpio-leds";
23 led-user0 {
26 linux,default-trigger = "none";
32 #clock-cells = <0>;
33 compatible = "fixed-clock";
34 clock-frequency = <26000000>;
[all …]
H A Dam3517-som.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Based on am3517-evm.dts
11 cpu0-supply = <&vdd_core_reg>;
16 compatible = "regulator-fixed";
17 regulator-name = "wl1271_buf";
18 regulator-min-microvolt = <1800000>;
19 regulator-max-microvolt = <1800000>;
20 pinctrl-names = "default";
21 pinctrl-0 = <&wl12xx_buffer_pins>;
23 regulator-always-on;
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Domap3-evm.dts2 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
8 /dts-v1/;
11 #include "omap3-evm-common.dtsi"
12 #include "omap3-evm-processor-common.dtsi"
16 compatible = "ti,omap3-evm", "ti,omap3430", "ti,omap3";
20 pinctrl-names = "default";
21 pinctrl-0 = <&hsusb2_2_pins>;
24 pinctrl-single,pins = <
36 pinctrl-single,pins = <
60 nand@0,0 {
[all …]
H A Domap3-evm-37xx.dts2 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
8 /dts-v1/;
11 #include "omap3-evm-common.dtsi"
12 #include "omap3-evm-processor-common.dtsi"
16 compatible = "ti,omap3-evm-37xx", "ti,omap3630", "ti,omap3";
20 pinctrl-names = "default";
21 pinctrl-0 = <&hsusb2_2_pins>;
24 pinctrl-single,pins = <
36 pinctrl-single,pins = <
60 nand@0,0 {
[all …]
H A Dam335x-draco.dtsi4 * Copyright (C) 2013,2014 - Stefan Roese <sr@denx.de>
13 stdout-path = &uart0;
14 tick-timer = &timer2;
24 pinctrl-names = "default";
25 pinctrl-0 = <&uart0_pins>;
30 pinctrl-names = "default";
31 pinctrl-0 = <&i2c0_pins>;
34 clock-frequency = <400000>;
50 usb-phy@47401300 {
54 usb-phy@47401b00 {
[all …]
H A Dam335x-chilisom.dtsi2 * Copyright (C) 2015 Jablotron s.r.o. -- http://www.jablotron.com/
10 #include <dt-bindings/interrupt-controller/irq.h>
14 compatible = "grinn,am335x-chilisom", "ti,am33xx";
18 cpu0-supply = <&dcdc2_reg>;
29 pinctrl-names = "default";
32 pinctrl-single,pins = <
39 pinctrl-single,pins = <
60 pinctrl-names = "default";
61 pinctrl-0 = <&i2c0_pins>;
64 clock-frequency = <400000>;
[all …]
H A Ddm8168-evm.dts6 /dts-v1/;
9 #include <dt-bindings/interrupt-controller/irq.h>
13 compatible = "ti,dm8168-evm", "ti,dm8168";
23 compatible = "regulator-fixed";
24 regulator-name = "vmmcsd_fixed";
25 regulator-min-microvolt = <3300000>;
26 regulator-max-microvolt = <3300000>;
32 pinctrl-single,pins = <
41 pinctrl-single,pins = <
55 pinctrl-single,pins = <
[all …]
H A Dlogicpd-torpedo-som.dtsi7 #include <dt-bindings/input/input.h>
11 stdout-path = &uart1;
16 cpu0-supply = <&vcc>;
26 compatible = "gpio-leds";
30 linux,default-trigger = "none";
36 #clock-cells = <0>;
37 compatible = "fixed-clock";
38 clock-frequency = <26000000>;
43 ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */
45 nand@0,0 {
[all …]
H A Dam335x-brppt1-nand.dts1 // SPDX-License-Identifier: GPL-2.0+
4 * http://www.br-automation.com
7 /dts-v1/;
12 model = "BRPPT1 (NAND) Panel";
15 fset: factory-settings {
16 bl-version = "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456890";
18 order-no = "6PPT30 (NAND)";
19 hw-revision = "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456890";
20 serial-no = "0";
21 device-id = <0x0>;
[all …]
/openbmc/u-boot/include/configs/
H A DBSC9131RDB.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2011-2012 Freescale Semiconductor, Inc.
25 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
31 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
32 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
35 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
112 * Base addresses -- Note these are effective addresses where the
131 * 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M
137 * 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND flash buffer 8M
145 /* NAND Flash on IFC */
[all …]
H A DC29XPCIE.h1 /* SPDX-License-Identifier: GPL-2.0+ */
45 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
46 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
73 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
77 * Memory space is mapped 1-1, but I/O space must start from 0.
121 /* DDR ECC Setup*/
159 /* 16Bit NOR Flash - S29GL512S10TFI01 */
182 /* NAND Flash on IFC */
192 /* 8Bit NAND Flash - K9F1G08U0B */
199 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
[all …]
H A DMPC8572DS.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc.
31 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
129 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
130 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
131 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
136 * Localbus non-cacheable
137 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
138 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
139 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
[all …]
H A DP1010RDB.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2010-2011 Freescale Semiconductor, Inc.
18 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
27 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
41 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
50 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
63 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
69 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
70 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
73 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
[all …]
H A DBSC9132QDS.h1 /* SPDX-License-Identifier: GPL-2.0+ */
33 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
39 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
40 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
43 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
64 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
68 * Memory space is mapped 1-1, but I/O space must start from 0.
236 /* NAND Flash on IFC */
242 | CSPR_MSEL_NAND /* MSEL = NAND */ \
246 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
[all …]
H A DMPC8536DS.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2007-2009,2010-2012 Freescale Semiconductor, Inc.
40 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
63 #define CONFIG_SYS_MEMTEST_END 0x1f000000 /* skip u-boot at top of RAM */
132 * Memory map -- xxx -this is wrong, needs updating
135 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
136 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
137 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
142 * Localbus non-cacheable
143 * 0xe000_0000 0xe7ff_ffff Promjet/free 128M non-cacheable
[all …]
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dti,gpmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ti,gpmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
11 - Roger Quadros <rogerq@kernel.org>
16 - Asynchronous SRAM-like memories and ASICs
17 - Asynchronous, synchronous, and page mode burst NOR flash
18 - NAND flash
19 - Pseudo-SRAM devices
[all …]
/openbmc/u-boot/board/ti/am335x/
H A DREADME12 - AM335x GP EVM
13 - AM335x EVM SK
14 - Beaglebone White
15 - Beaglebone Black
23 worth noting that aside from things such as NAND or MMC only being
27 - GPIO is only required if DDR3 power is controlled in a way similar to
29 - SPI is only required for SPI flash, or exposing the SPI bus.
32 - I2C, to talk with the PMIC and ensure that we do not run afoul of
38 define additional text blocks (such as for NAND or DFU strings). Also
43 NAND
[all …]

1234