1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0-only 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ 4*724ba675SRob Herring */ 5*724ba675SRob Herring/dts-v1/; 6*724ba675SRob Herring 7*724ba675SRob Herring#include "omap34xx.dtsi" 8*724ba675SRob Herring#include "omap3-evm-common.dtsi" 9*724ba675SRob Herring#include "omap3-evm-processor-common.dtsi" 10*724ba675SRob Herring 11*724ba675SRob Herring/ { 12*724ba675SRob Herring model = "TI OMAP35XX EVM (TMDSEVM3530)"; 13*724ba675SRob Herring compatible = "ti,omap3-evm", "ti,omap3430", "ti,omap3"; 14*724ba675SRob Herring}; 15*724ba675SRob Herring 16*724ba675SRob Herring&omap3_pmx_core2 { 17*724ba675SRob Herring pinctrl-names = "default"; 18*724ba675SRob Herring pinctrl-0 = <&hsusb2_2_pins>; 19*724ba675SRob Herring 20*724ba675SRob Herring ehci_phy_pins: ehci-phy-pins { 21*724ba675SRob Herring pinctrl-single,pins = < 22*724ba675SRob Herring 23*724ba675SRob Herring /* EHCI PHY reset GPIO etk_d7.gpio_21 */ 24*724ba675SRob Herring OMAP3430_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) 25*724ba675SRob Herring 26*724ba675SRob Herring /* EHCI VBUS etk_d8.gpio_22 */ 27*724ba675SRob Herring OMAP3430_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) 28*724ba675SRob Herring >; 29*724ba675SRob Herring }; 30*724ba675SRob Herring 31*724ba675SRob Herring /* Used by OHCI and EHCI. OHCI won't work without external phy */ 32*724ba675SRob Herring hsusb2_2_pins: hsusb2-2-pins { 33*724ba675SRob Herring pinctrl-single,pins = < 34*724ba675SRob Herring 35*724ba675SRob Herring /* etk_d10.hsusb2_clk */ 36*724ba675SRob Herring OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) 37*724ba675SRob Herring 38*724ba675SRob Herring /* etk_d11.hsusb2_stp */ 39*724ba675SRob Herring OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) 40*724ba675SRob Herring 41*724ba675SRob Herring /* etk_d12.hsusb2_dir */ 42*724ba675SRob Herring OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) 43*724ba675SRob Herring 44*724ba675SRob Herring /* etk_d13.hsusb2_nxt */ 45*724ba675SRob Herring OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) 46*724ba675SRob Herring 47*724ba675SRob Herring /* etk_d14.hsusb2_data0 */ 48*724ba675SRob Herring OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) 49*724ba675SRob Herring 50*724ba675SRob Herring /* etk_d15.hsusb2_data1 */ 51*724ba675SRob Herring OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) 52*724ba675SRob Herring >; 53*724ba675SRob Herring }; 54*724ba675SRob Herring}; 55*724ba675SRob Herring 56*724ba675SRob Herring&gpmc { 57*724ba675SRob Herring nand@0,0 { 58*724ba675SRob Herring compatible = "ti,omap2-nand"; 59*724ba675SRob Herring reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ 60*724ba675SRob Herring interrupt-parent = <&gpmc>; 61*724ba675SRob Herring interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ 62*724ba675SRob Herring <1 IRQ_TYPE_NONE>; /* termcount */ 63*724ba675SRob Herring linux,mtd-name = "micron,mt29f2g16abdhc"; 64*724ba675SRob Herring nand-bus-width = <16>; 65*724ba675SRob Herring gpmc,device-width = <2>; 66*724ba675SRob Herring ti,nand-ecc-opt = "bch8"; 67*724ba675SRob Herring 68*724ba675SRob Herring gpmc,sync-clk-ps = <0>; 69*724ba675SRob Herring gpmc,cs-on-ns = <0>; 70*724ba675SRob Herring gpmc,cs-rd-off-ns = <44>; 71*724ba675SRob Herring gpmc,cs-wr-off-ns = <44>; 72*724ba675SRob Herring gpmc,adv-on-ns = <6>; 73*724ba675SRob Herring gpmc,adv-rd-off-ns = <34>; 74*724ba675SRob Herring gpmc,adv-wr-off-ns = <44>; 75*724ba675SRob Herring gpmc,we-off-ns = <40>; 76*724ba675SRob Herring gpmc,oe-off-ns = <54>; 77*724ba675SRob Herring gpmc,access-ns = <64>; 78*724ba675SRob Herring gpmc,rd-cycle-ns = <82>; 79*724ba675SRob Herring gpmc,wr-cycle-ns = <82>; 80*724ba675SRob Herring gpmc,wr-access-ns = <40>; 81*724ba675SRob Herring gpmc,wr-data-mux-bus-ns = <0>; 82*724ba675SRob Herring 83*724ba675SRob Herring #address-cells = <1>; 84*724ba675SRob Herring #size-cells = <1>; 85*724ba675SRob Herring }; 86*724ba675SRob Herring}; 87