include/configs/MPC8536DS.h

1 /* SPDX-License-Identifier: GPL-2.0+ */
3  * Copyright 2007-2009,2010-2012 Freescale Semiconductor, Inc.
40 #define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
63 #define CONFIG_SYS_MEMTEST_END   0x1f000000	/* skip u-boot at top of RAM */
132  * Memory map -- xxx -this is wrong, needs updating
135  * 0x8000_0000	0xbfff_ffff	PCI Express Mem		1G non-cacheable
136  * 0xc000_0000	0xdfff_ffff	PCI			512M non-cacheable
137  * 0xe100_0000	0xe3ff_ffff	PCI IO range		4M non-cacheable
142  * Localbus non-cacheable
143  * 0xe000_0000	0xe7ff_ffff	Promjet/free		128M non-cacheable
144  * 0xe800_0000	0xefff_ffff	FLASH			128M non-cacheable
145  * 0xffa0_0000	0xffaf_ffff	NAND			1M non-cacheable
146  * 0xffdf_0000	0xffdf_7fff	PIXIS			32K non-cacheable TLB0
148  * 0xffe0_0000	0xffef_ffff	CCSR			1M non-cacheable
217 #define PIXIS_VBOOT_LBMAP	0xe0	/* VBOOT - CFG_LBMAP */
218 #define PIXIS_VBOOT_LBMAP_NOR0	0x00	/* cfg_lbmap - boot from NOR 0 */
219 #define PIXIS_VBOOT_LBMAP_NOR1	0x01	/* cfg_lbmap - boot from NOR 1 */
220 #define PIXIS_VBOOT_LBMAP_NOR2	0x02	/* cfg_lbmap - boot from NOR 2 */
221 #define PIXIS_VBOOT_LBMAP_NOR3	0x03	/* cfg_lbmap - boot from NOR 3 */
222 #define PIXIS_VBOOT_LBMAP_PJET	0x04	/* cfg_lbmap - boot from projet */
223 #define PIXIS_VBOOT_LBMAP_NAND	0x05	/* cfg_lbmap - boot from NAND */
248 		(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
277 /* NAND boot: 4K NAND loader config */
279 #define CONFIG_SYS_NAND_U_BOOT_SIZE	((768 << 10) - 0x2000)
284 #define CONFIG_SYS_NAND_U_BOOT_RELOC	(CONFIG_SYS_INIT_L2_END - 0x2000)
285 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
287 /* NAND flash config */
290 		| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
305 #define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
306 #define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
310 		| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
314 #define CONFIG_SYS_OR4_PRELIM	CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
317 		| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
321 #define CONFIG_SYS_OR5_PRELIM	CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
325 		| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
329 #define CONFIG_SYS_OR6_PRELIM	CONFIG_SYS_NAND_OR_PRELIM	/* NAND Options */
331 /* Serial Port - controlled on board with jumper J8
332  * open - index 2
333  * shorted - index 1
374  * Memory space is mapped 1-1, but I/O space must start from 0.
508 #define TSEC1_PHY_ADDR		1	/* TSEC1 -> PHY1 */
509 #define TSEC3_PHY_ADDR		0	/* TSEC3 -> PHY0 */
535 	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
539 	#define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
596 #define CONFIG_ROOTPATH		"/opt/nfsroot"
598 #define CONFIG_UBOOTPATH	u-boot.bin /* U-Boot image on TFTP server */
634  "bootm $loadaddr - $fdtaddr"
643  "bootm $loadaddr - $fdtaddr"