include/configs/P1010RDB.h

1 /* SPDX-License-Identifier: GPL-2.0+ */
3  * Copyright 2010-2011 Freescale Semiconductor, Inc.
18 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
27 #define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot.lds"
41 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
50 #define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot.lds"
63 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
69 #define CONFIG_SYS_NAND_U_BOOT_SIZE	((768 << 10) - 0x2000)
70 #define CONFIG_SYS_NAND_U_BOOT_DST	(0x00200000 - CONFIG_SPL_MAX_SIZE)
73 #define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
100 #define CONFIG_SPL_TARGET	"u-boot-with-spl.bin"
101 #define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
105 #ifdef CONFIG_NAND_SECBOOT	/* NAND Boot */
131 #define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
135  * Memory space is mapped 1-1, but I/O space must start from 0.
275  * 0x8000_0000  0xbfff_ffff	PCI Express Mem		1.5G non-cacheable
276  * 0xffc0_0000  0xffc3_ffff	PCI IO range		256k non-cacheable
278  * Localbus non-cacheable
279  * 0xff80_0000	0xff8f_ffff	NAND Flash		1M non-cacheable
280  * 0xffb0_0000	0xffbf_ffff	Board CPLD		1M non-cacheable
282  * 0xffe0_0000	0xffef_ffff	CCSR			1M non-cacheable
328 /* NAND Flash on IFC */
345 #define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
346 				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
347 				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */ \
356 #define CONFIG_SYS_NAND_CSOR   (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
357 				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
358 				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
370 /* NAND Flash Timing Params */
385 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
386 /* ONFI NAND Flash mode0 Timing Params */
403 /* Set up IFC registers for boot location NOR/NAND */
480 						- GENERATED_GBL_DATA_SIZE)
516 #define CONFIG_SPL_RELOC_TEXT_BASE	(CONFIG_SYS_INIT_L2_END - 0x3000)
517 #define CONFIG_SPL_RELOC_STACK		((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
571  * SPI interface will not be available in case of NAND boot SPI CS0 will be
575 /* eSPI - Enhanced SPI */
665 #define CONFIG_ENV_ADDR			(CONFIG_SYS_MONITOR_BASE - 0x1000)
668 #define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
709 #define CONFIG_ROOTPATH		"/opt/nfsroot"
711 #define CONFIG_UBOOTPATH	u-boot.bin/* U-Boot image on TFTP server */