1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 27530d341SPrabhakar Kushwaha /* 37530d341SPrabhakar Kushwaha * Copyright 2011-2012 Freescale Semiconductor, Inc. 47530d341SPrabhakar Kushwaha */ 57530d341SPrabhakar Kushwaha 67530d341SPrabhakar Kushwaha /* 77530d341SPrabhakar Kushwaha * BSC9131 RDB board configuration file 87530d341SPrabhakar Kushwaha */ 97530d341SPrabhakar Kushwaha 107530d341SPrabhakar Kushwaha #ifndef __CONFIG_H 117530d341SPrabhakar Kushwaha #define __CONFIG_H 127530d341SPrabhakar Kushwaha 137530d341SPrabhakar Kushwaha #define CONFIG_NAND_FSL_IFC 147530d341SPrabhakar Kushwaha 157530d341SPrabhakar Kushwaha #ifdef CONFIG_SPIFLASH 167530d341SPrabhakar Kushwaha #define CONFIG_RAMBOOT_SPIFLASH 177530d341SPrabhakar Kushwaha #define CONFIG_SYS_RAMBOOT 18e222b1f3SPrabhakar Kushwaha #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 197530d341SPrabhakar Kushwaha #endif 207530d341SPrabhakar Kushwaha 21f1593269SPrabhakar Kushwaha #ifdef CONFIG_NAND 22f1593269SPrabhakar Kushwaha #define CONFIG_SPL_INIT_MINIMAL 23fbe76ae4SPrabhakar Kushwaha #define CONFIG_SPL_NAND_BOOT 24f1593269SPrabhakar Kushwaha #define CONFIG_SPL_FLUSH_IMAGE 25f1593269SPrabhakar Kushwaha #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 26f1593269SPrabhakar Kushwaha 27f1593269SPrabhakar Kushwaha #define CONFIG_SPL_TEXT_BASE 0xFFFFE000 28f1593269SPrabhakar Kushwaha #define CONFIG_SPL_MAX_SIZE 8192 29f1593269SPrabhakar Kushwaha #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 30f1593269SPrabhakar Kushwaha #define CONFIG_SPL_RELOC_STACK 0x00100000 31e222b1f3SPrabhakar Kushwaha #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 32f1593269SPrabhakar Kushwaha #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) 33f1593269SPrabhakar Kushwaha #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 34f1593269SPrabhakar Kushwaha #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 35f1593269SPrabhakar Kushwaha #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 36f1593269SPrabhakar Kushwaha #endif 37f1593269SPrabhakar Kushwaha 38f1593269SPrabhakar Kushwaha #ifdef CONFIG_SPL_BUILD 39f1593269SPrabhakar Kushwaha #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 40f1593269SPrabhakar Kushwaha #else 417530d341SPrabhakar Kushwaha #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 427530d341SPrabhakar Kushwaha #endif 437530d341SPrabhakar Kushwaha 447530d341SPrabhakar Kushwaha /* High Level Configuration Options */ 457530d341SPrabhakar Kushwaha 467530d341SPrabhakar Kushwaha #define CONFIG_ENV_OVERWRITE 477530d341SPrabhakar Kushwaha 487530d341SPrabhakar Kushwaha #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on 9131 RDB */ 49087cf44fSPriyanka Jain #if defined(CONFIG_SYS_CLK_100) 50087cf44fSPriyanka Jain #define CONFIG_SYS_CLK_FREQ 100000000 /* SYSCLK for 9131 RDB */ 51087cf44fSPriyanka Jain #else 527530d341SPrabhakar Kushwaha #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for 9131 RDB */ 53087cf44fSPriyanka Jain #endif 547530d341SPrabhakar Kushwaha 557530d341SPrabhakar Kushwaha #define CONFIG_HWCONFIG 567530d341SPrabhakar Kushwaha /* 577530d341SPrabhakar Kushwaha * These can be toggled for performance analysis, otherwise use default. 587530d341SPrabhakar Kushwaha */ 597530d341SPrabhakar Kushwaha #define CONFIG_L2_CACHE /* toggle L2 cache */ 607530d341SPrabhakar Kushwaha #define CONFIG_BTB /* enable branch predition */ 617530d341SPrabhakar Kushwaha 627530d341SPrabhakar Kushwaha #define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */ 637530d341SPrabhakar Kushwaha #define CONFIG_SYS_MEMTEST_END 0x01ffffff 647530d341SPrabhakar Kushwaha 657530d341SPrabhakar Kushwaha /* DDR Setup */ 667530d341SPrabhakar Kushwaha #undef CONFIG_SYS_DDR_RAW_TIMING 677530d341SPrabhakar Kushwaha #undef CONFIG_DDR_SPD 687530d341SPrabhakar Kushwaha #define CONFIG_SYS_SPD_BUS_NUM 0 697530d341SPrabhakar Kushwaha #define SPD_EEPROM_ADDRESS 0x52 /* I2C access */ 707530d341SPrabhakar Kushwaha 717530d341SPrabhakar Kushwaha #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 727530d341SPrabhakar Kushwaha 737530d341SPrabhakar Kushwaha #ifndef __ASSEMBLY__ 747530d341SPrabhakar Kushwaha extern unsigned long get_sdram_size(void); 757530d341SPrabhakar Kushwaha #endif 767530d341SPrabhakar Kushwaha #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ 777530d341SPrabhakar Kushwaha #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 787530d341SPrabhakar Kushwaha #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 797530d341SPrabhakar Kushwaha 807530d341SPrabhakar Kushwaha #define CONFIG_DIMM_SLOTS_PER_CTLR 1 817530d341SPrabhakar Kushwaha #define CONFIG_CHIP_SELECTS_PER_CTRL 1 827530d341SPrabhakar Kushwaha 837530d341SPrabhakar Kushwaha #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 847530d341SPrabhakar Kushwaha #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 857530d341SPrabhakar Kushwaha #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 867530d341SPrabhakar Kushwaha 877530d341SPrabhakar Kushwaha #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 887530d341SPrabhakar Kushwaha #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 897530d341SPrabhakar Kushwaha #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 907530d341SPrabhakar Kushwaha #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 917530d341SPrabhakar Kushwaha 927530d341SPrabhakar Kushwaha #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 937530d341SPrabhakar Kushwaha #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 947530d341SPrabhakar Kushwaha #define CONFIG_SYS_DDR_RCW_1 0x00000000 957530d341SPrabhakar Kushwaha #define CONFIG_SYS_DDR_RCW_2 0x00000000 967530d341SPrabhakar Kushwaha #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ 977530d341SPrabhakar Kushwaha #define CONFIG_SYS_DDR_CONTROL_2 0x24401000 987530d341SPrabhakar Kushwaha #define CONFIG_SYS_DDR_TIMING_4 0x00000001 997530d341SPrabhakar Kushwaha #define CONFIG_SYS_DDR_TIMING_5 0x02401400 1007530d341SPrabhakar Kushwaha 1017530d341SPrabhakar Kushwaha #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 1027530d341SPrabhakar Kushwaha #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104 1037530d341SPrabhakar Kushwaha #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644 1047530d341SPrabhakar Kushwaha #define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cf 1057530d341SPrabhakar Kushwaha #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 1067530d341SPrabhakar Kushwaha #define CONFIG_SYS_DDR_MODE_1_800 0x00441420 1077530d341SPrabhakar Kushwaha #define CONFIG_SYS_DDR_MODE_2_800 0x8000c000 1087530d341SPrabhakar Kushwaha #define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100 1097530d341SPrabhakar Kushwaha #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608 1107530d341SPrabhakar Kushwaha 1117530d341SPrabhakar Kushwaha /* 1127530d341SPrabhakar Kushwaha * Base addresses -- Note these are effective addresses where the 1137530d341SPrabhakar Kushwaha * actual resources get mapped (not physical addresses) 1147530d341SPrabhakar Kushwaha */ 1157530d341SPrabhakar Kushwaha /* relocated CCSRBAR */ 1167530d341SPrabhakar Kushwaha #define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT 1177530d341SPrabhakar Kushwaha #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT 1187530d341SPrabhakar Kushwaha 1197530d341SPrabhakar Kushwaha #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */ 1207530d341SPrabhakar Kushwaha /* CONFIG_SYS_IMMR */ 121765b0bdbSPriyanka Jain /* DSP CCSRBAR */ 122765b0bdbSPriyanka Jain #define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 123765b0bdbSPriyanka Jain #define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 1247530d341SPrabhakar Kushwaha 1257530d341SPrabhakar Kushwaha /* 1267530d341SPrabhakar Kushwaha * Memory map 1277530d341SPrabhakar Kushwaha * 1287530d341SPrabhakar Kushwaha * 0x0000_0000 0x3FFF_FFFF DDR 1G cacheable 1297530d341SPrabhakar Kushwaha * 0x8800_0000 0x8810_0000 IFC internal SRAM 1M 130765b0bdbSPriyanka Jain * 0xB000_0000 0xB0FF_FFFF DSP core M2 memory 16M 1317530d341SPrabhakar Kushwaha * 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M 1327530d341SPrabhakar Kushwaha * 0xC1F0_0000 0xC1F3_FFFF PA L2 SRAM Region 0 256K 1337530d341SPrabhakar Kushwaha * 0xC1F8_0000 0xC1F9_FFFF PA L2 SRAM Region 1 128K 1347530d341SPrabhakar Kushwaha * 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K 135765b0bdbSPriyanka Jain * 0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M 1367530d341SPrabhakar Kushwaha * 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M 1377530d341SPrabhakar Kushwaha * 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND flash buffer 8M 1387530d341SPrabhakar Kushwaha * 1397530d341SPrabhakar Kushwaha */ 1407530d341SPrabhakar Kushwaha 1417530d341SPrabhakar Kushwaha /* 1427530d341SPrabhakar Kushwaha * IFC Definitions 1437530d341SPrabhakar Kushwaha */ 1447530d341SPrabhakar Kushwaha 1457530d341SPrabhakar Kushwaha /* NAND Flash on IFC */ 1467530d341SPrabhakar Kushwaha #define CONFIG_SYS_NAND_BASE 0xff800000 1477530d341SPrabhakar Kushwaha #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 1487530d341SPrabhakar Kushwaha 1497530d341SPrabhakar Kushwaha #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 1507530d341SPrabhakar Kushwaha | CSPR_PORT_SIZE_8 /* Port Size = 8 bit*/ \ 1517530d341SPrabhakar Kushwaha | CSPR_MSEL_NAND /* MSEL = NAND */ \ 1527530d341SPrabhakar Kushwaha | CSPR_V) 1537530d341SPrabhakar Kushwaha #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 1547530d341SPrabhakar Kushwaha 1557530d341SPrabhakar Kushwaha #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 1567530d341SPrabhakar Kushwaha | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 1577530d341SPrabhakar Kushwaha | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 1587530d341SPrabhakar Kushwaha | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \ 1597530d341SPrabhakar Kushwaha | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 1607530d341SPrabhakar Kushwaha | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ 1617530d341SPrabhakar Kushwaha | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 1627530d341SPrabhakar Kushwaha 1637530d341SPrabhakar Kushwaha /* NAND Flash Timing Params */ 1644544fd29SPrabhakar Kushwaha #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \ 1654544fd29SPrabhakar Kushwaha | FTIM0_NAND_TWP(0x05) \ 1664544fd29SPrabhakar Kushwaha | FTIM0_NAND_TWCHT(0x02) \ 1677530d341SPrabhakar Kushwaha | FTIM0_NAND_TWH(0x04)) 1684544fd29SPrabhakar Kushwaha #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1C) \ 1694544fd29SPrabhakar Kushwaha | FTIM1_NAND_TWBE(0x1E) \ 1704544fd29SPrabhakar Kushwaha | FTIM1_NAND_TRR(0x07) \ 1717530d341SPrabhakar Kushwaha | FTIM1_NAND_TRP(0x05)) 1727530d341SPrabhakar Kushwaha #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \ 1737530d341SPrabhakar Kushwaha | FTIM2_NAND_TREH(0x04) \ 1744544fd29SPrabhakar Kushwaha | FTIM2_NAND_TWHRE(0x11)) 1754544fd29SPrabhakar Kushwaha #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) 1767530d341SPrabhakar Kushwaha 1777530d341SPrabhakar Kushwaha #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 1787530d341SPrabhakar Kushwaha #define CONFIG_SYS_MAX_NAND_DEVICE 1 1797530d341SPrabhakar Kushwaha #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 1807530d341SPrabhakar Kushwaha 1817530d341SPrabhakar Kushwaha #define CONFIG_SYS_NAND_DDR_LAW 11 1827530d341SPrabhakar Kushwaha 1837530d341SPrabhakar Kushwaha /* Set up IFC registers for boot location NAND */ 1847530d341SPrabhakar Kushwaha #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 1857530d341SPrabhakar Kushwaha #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 1867530d341SPrabhakar Kushwaha #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 1877530d341SPrabhakar Kushwaha #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 1887530d341SPrabhakar Kushwaha #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 1897530d341SPrabhakar Kushwaha #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 1907530d341SPrabhakar Kushwaha #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 1917530d341SPrabhakar Kushwaha 1927530d341SPrabhakar Kushwaha #define CONFIG_SYS_INIT_RAM_LOCK 1937530d341SPrabhakar Kushwaha #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 194b39d1213SYork Sun #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000/* End of used area in RAM */ 1957530d341SPrabhakar Kushwaha 196b39d1213SYork Sun #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ 1977530d341SPrabhakar Kushwaha - GENERATED_GBL_DATA_SIZE) 1987530d341SPrabhakar Kushwaha #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 1997530d341SPrabhakar Kushwaha 2009307cbabSPrabhakar Kushwaha #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 2017530d341SPrabhakar Kushwaha #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ 2027530d341SPrabhakar Kushwaha 2037530d341SPrabhakar Kushwaha /* Serial Port */ 2047530d341SPrabhakar Kushwaha #undef CONFIG_SERIAL_SOFTWARE_FIFO 2057530d341SPrabhakar Kushwaha #define CONFIG_SYS_NS16550_SERIAL 2067530d341SPrabhakar Kushwaha #define CONFIG_SYS_NS16550_REG_SIZE 1 2077530d341SPrabhakar Kushwaha #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 208f1593269SPrabhakar Kushwaha #ifdef CONFIG_SPL_BUILD 209f1593269SPrabhakar Kushwaha #define CONFIG_NS16550_MIN_FUNCTIONS 210f1593269SPrabhakar Kushwaha #endif 2117530d341SPrabhakar Kushwaha 2127530d341SPrabhakar Kushwaha #define CONFIG_SYS_BAUDRATE_TABLE \ 2137530d341SPrabhakar Kushwaha {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 2147530d341SPrabhakar Kushwaha 2157530d341SPrabhakar Kushwaha #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 2167530d341SPrabhakar Kushwaha 21700f792e0SHeiko Schocher #define CONFIG_SYS_I2C 21800f792e0SHeiko Schocher #define CONFIG_SYS_I2C_FSL 21900f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C_SPEED 400000 22000f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 22100f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 2227530d341SPrabhakar Kushwaha 2237530d341SPrabhakar Kushwaha /* I2C EEPROM */ 2247530d341SPrabhakar Kushwaha #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 2257530d341SPrabhakar Kushwaha #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 2267530d341SPrabhakar Kushwaha #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 2277530d341SPrabhakar Kushwaha 2287530d341SPrabhakar Kushwaha /* eSPI - Enhanced SPI */ 2297530d341SPrabhakar Kushwaha 2307530d341SPrabhakar Kushwaha #if defined(CONFIG_TSEC_ENET) 2317530d341SPrabhakar Kushwaha 2327530d341SPrabhakar Kushwaha #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 2337530d341SPrabhakar Kushwaha #define CONFIG_TSEC1 1 2347530d341SPrabhakar Kushwaha #define CONFIG_TSEC1_NAME "eTSEC1" 2357530d341SPrabhakar Kushwaha #define CONFIG_TSEC2 1 2367530d341SPrabhakar Kushwaha #define CONFIG_TSEC2_NAME "eTSEC2" 2377530d341SPrabhakar Kushwaha 2387530d341SPrabhakar Kushwaha #define TSEC1_PHY_ADDR 0 2397530d341SPrabhakar Kushwaha #define TSEC2_PHY_ADDR 3 2407530d341SPrabhakar Kushwaha 2417530d341SPrabhakar Kushwaha #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 2427530d341SPrabhakar Kushwaha #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 2437530d341SPrabhakar Kushwaha 2447530d341SPrabhakar Kushwaha #define TSEC1_PHYIDX 0 2457530d341SPrabhakar Kushwaha 2467530d341SPrabhakar Kushwaha #define TSEC2_PHYIDX 0 2477530d341SPrabhakar Kushwaha 2487530d341SPrabhakar Kushwaha #define CONFIG_ETHPRIME "eTSEC1" 2497530d341SPrabhakar Kushwaha 2507530d341SPrabhakar Kushwaha #endif /* CONFIG_TSEC_ENET */ 2517530d341SPrabhakar Kushwaha 2527530d341SPrabhakar Kushwaha /* 2537530d341SPrabhakar Kushwaha * Environment 2547530d341SPrabhakar Kushwaha */ 2557530d341SPrabhakar Kushwaha #if defined(CONFIG_RAMBOOT_SPIFLASH) 2567530d341SPrabhakar Kushwaha #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 2577530d341SPrabhakar Kushwaha #define CONFIG_ENV_SECT_SIZE 0x10000 2587530d341SPrabhakar Kushwaha #define CONFIG_ENV_SIZE 0x2000 259f1593269SPrabhakar Kushwaha #elif defined(CONFIG_NAND) 260f1593269SPrabhakar Kushwaha #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 261e222b1f3SPrabhakar Kushwaha #define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) 262f1593269SPrabhakar Kushwaha #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 263f1593269SPrabhakar Kushwaha #elif defined(CONFIG_SYS_RAMBOOT) 2647530d341SPrabhakar Kushwaha #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 2657530d341SPrabhakar Kushwaha #define CONFIG_ENV_SIZE 0x2000 2667530d341SPrabhakar Kushwaha #endif 2677530d341SPrabhakar Kushwaha 2687530d341SPrabhakar Kushwaha #define CONFIG_LOADS_ECHO /* echo on for serial download */ 2697530d341SPrabhakar Kushwaha #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 2707530d341SPrabhakar Kushwaha 2717530d341SPrabhakar Kushwaha /* 2727530d341SPrabhakar Kushwaha * Miscellaneous configurable options 2737530d341SPrabhakar Kushwaha */ 2747530d341SPrabhakar Kushwaha #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 2757530d341SPrabhakar Kushwaha 2767530d341SPrabhakar Kushwaha #if defined(CONFIG_CMD_KGDB) 2777530d341SPrabhakar Kushwaha #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 2787530d341SPrabhakar Kushwaha #else 2797530d341SPrabhakar Kushwaha #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 2807530d341SPrabhakar Kushwaha #endif 2817530d341SPrabhakar Kushwaha #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 2827530d341SPrabhakar Kushwaha 2837530d341SPrabhakar Kushwaha /* 2847530d341SPrabhakar Kushwaha * For booting Linux, the board info and command line data 2857530d341SPrabhakar Kushwaha * have to be in the first 64 MB of memory, since this is 2867530d341SPrabhakar Kushwaha * the maximum mapped by the Linux kernel during initialization. 2877530d341SPrabhakar Kushwaha */ 2887530d341SPrabhakar Kushwaha #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 2897530d341SPrabhakar Kushwaha #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 2907530d341SPrabhakar Kushwaha 2917530d341SPrabhakar Kushwaha #if defined(CONFIG_CMD_KGDB) 2927530d341SPrabhakar Kushwaha #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 2937530d341SPrabhakar Kushwaha #endif 2947530d341SPrabhakar Kushwaha 2958850c5d5STom Rini #ifdef CONFIG_USB_EHCI_HCD 2967530d341SPrabhakar Kushwaha #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 2977530d341SPrabhakar Kushwaha #define CONFIG_USB_EHCI_FSL 2987530d341SPrabhakar Kushwaha #define CONFIG_HAS_FSL_DR_USB 2997530d341SPrabhakar Kushwaha #endif 3007530d341SPrabhakar Kushwaha 3017530d341SPrabhakar Kushwaha /* 3027ac1a24aSAshish Kumar * Dynamic MTD Partition support with mtdparts 3037ac1a24aSAshish Kumar */ 3047ac1a24aSAshish Kumar 3057ac1a24aSAshish Kumar /* 3067530d341SPrabhakar Kushwaha * Environment Configuration 3077530d341SPrabhakar Kushwaha */ 3087530d341SPrabhakar Kushwaha 3097530d341SPrabhakar Kushwaha #if defined(CONFIG_TSEC_ENET) 3107530d341SPrabhakar Kushwaha #define CONFIG_HAS_ETH0 3117530d341SPrabhakar Kushwaha #endif 3127530d341SPrabhakar Kushwaha 3135bc0543dSMario Six #define CONFIG_HOSTNAME "BSC9131rdb" 3147530d341SPrabhakar Kushwaha #define CONFIG_ROOTPATH "/opt/nfsroot" 3157530d341SPrabhakar Kushwaha #define CONFIG_BOOTFILE "uImage" 3167530d341SPrabhakar Kushwaha #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 3177530d341SPrabhakar Kushwaha 3187530d341SPrabhakar Kushwaha #define CONFIG_EXTRA_ENV_SETTINGS \ 3197530d341SPrabhakar Kushwaha "netdev=eth0\0" \ 3207530d341SPrabhakar Kushwaha "uboot=" CONFIG_UBOOTPATH "\0" \ 3217530d341SPrabhakar Kushwaha "loadaddr=1000000\0" \ 3227530d341SPrabhakar Kushwaha "bootfile=uImage\0" \ 3237530d341SPrabhakar Kushwaha "consoledev=ttyS0\0" \ 3247530d341SPrabhakar Kushwaha "ramdiskaddr=2000000\0" \ 3257530d341SPrabhakar Kushwaha "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 326b24a4f62SScott Wood "fdtaddr=1e00000\0" \ 3277530d341SPrabhakar Kushwaha "fdtfile=bsc9131rdb.dtb\0" \ 3287530d341SPrabhakar Kushwaha "bdev=sda1\0" \ 3297530d341SPrabhakar Kushwaha "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \ 3301d2949aeSPriyanka Jain "bootm_size=0x37000000\0" \ 3311d2949aeSPriyanka Jain "othbootargs=ramdisk_size=600000 " \ 3321d2949aeSPriyanka Jain "default_hugepagesz=256m hugepagesz=256m hugepages=1\0" \ 3337530d341SPrabhakar Kushwaha "usbext2boot=setenv bootargs root=/dev/ram rw " \ 3347530d341SPrabhakar Kushwaha "console=$consoledev,$baudrate $othbootargs; " \ 3357530d341SPrabhakar Kushwaha "usb start;" \ 3367530d341SPrabhakar Kushwaha "ext2load usb 0:4 $loadaddr $bootfile;" \ 3377530d341SPrabhakar Kushwaha "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 3387530d341SPrabhakar Kushwaha "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 3397530d341SPrabhakar Kushwaha "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 3407530d341SPrabhakar Kushwaha 3417530d341SPrabhakar Kushwaha #define CONFIG_RAMBOOTCOMMAND \ 3427530d341SPrabhakar Kushwaha "setenv bootargs root=/dev/ram rw " \ 3437530d341SPrabhakar Kushwaha "console=$consoledev,$baudrate $othbootargs; " \ 3447530d341SPrabhakar Kushwaha "tftp $ramdiskaddr $ramdiskfile;" \ 3457530d341SPrabhakar Kushwaha "tftp $loadaddr $bootfile;" \ 3467530d341SPrabhakar Kushwaha "tftp $fdtaddr $fdtfile;" \ 3477530d341SPrabhakar Kushwaha "bootm $loadaddr $ramdiskaddr $fdtaddr" 3487530d341SPrabhakar Kushwaha 3497530d341SPrabhakar Kushwaha #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 3507530d341SPrabhakar Kushwaha 3517530d341SPrabhakar Kushwaha #endif /* __CONFIG_H */ 352