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/openbmc/linux/sound/soc/stm/
H A Dstm32_sai_sub.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
10 #include <linux/clk-provider.h>
41 #define STM_SAI_IS_PLAYBACK(ip) ((ip)->dir == SNDRV_PCM_STREAM_PLAYBACK)
42 #define STM_SAI_IS_CAPTURE(ip) ((ip)->dir == SNDRV_PCM_STREAM_CAPTURE)
47 #define STM_SAI_IS_SUB_A(x) ((x)->id == STM_SAI_A_ID)
53 #define STM_SAI_PROTOCOL_IS_SPDIF(ip) ((ip)->spdif)
54 #define STM_SAI_HAS_SPDIF(x) ((x)->pdata->conf.has_spdif_pdm)
55 #define STM_SAI_HAS_PDM(x) ((x)->pdata->conf.has_spdif_pdm)
56 #define STM_SAI_HAS_EXT_SYNC(x) (!STM_SAI_IS_F4(sai->pdata))
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H A Dstm32_i2s.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
11 #include <linux/clk-provider.h>
136 #define I2S_CGFR_I2SDIV_MAX ((1 << (I2S_CGFR_I2SDIV_BIT_H -\
137 I2S_CGFR_I2SDIV_SHIFT)) - 1)
198 #define STM32_I2S_IS_MASTER(x) ((x)->ms_flg == I2S_MS_MASTER)
199 #define STM32_I2S_IS_SLAVE(x) ((x)->ms_flg == I2S_MS_SLAVE)
205 * struct stm32_i2s_data - private data of I2S
214 * @i2smclk: master clock from I2S mclk provider
225 * @div: prescaler div field
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/openbmc/linux/arch/powerpc/platforms/512x/
H A Dclock-commonclk.c1 // SPDX-License-Identifier: GPL-2.0-or-later
12 #include <linux/clk-provider.h>
21 #include <dt-bindings/clock/mpc512x-clock.h>
25 /* helpers to keep the MCLK intermediates "somewhere" in our table */
47 /* intermediates in div+gate combos or fractional dividers */
61 /* intermediates for the mux+gate+div+mux MCLK generation */
89 * interpretation, no CFM, different fourth PSC/CAN mux0 input -- yet
225 int mul, int div) in mpc512x_clk_factor() argument
231 mul, div); in mpc512x_clk_factor()
292 val &= (1 << len) - 1; in get_bit_field()
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/openbmc/linux/sound/aoa/soundbus/i2sbus/
H A Dinterface.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * i2sbus driver -- interface register definitions
61 * - clock source
62 * - MClk divisor
63 * - SClk divisor
64 * - SClk master flag
65 * - serial format (sony, i2s 64x, i2s 32x, dav, silabs)
66 * - external sample frequency interrupt (don't understand)
67 * - external sample frequency
80 /* MClk is the clock that drives the codec, usually called its 'system clock'.
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/openbmc/linux/drivers/spi/
H A Dspi-sun4i.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2012 - 2014 Allwinner Tech
7 * Maxime Ripard <maxime.ripard@free-electrons.com>
57 #define SUN4I_CLK_CTL_CDR2(div) ((div) & SUN4I_CLK_CTL_CDR2_MASK) argument
59 #define SUN4I_CLK_CTL_CDR1(div) (((div) & SUN4I_CLK_CTL_CDR1_MASK) << 8) argument
81 struct clk *mclk; member
92 return readl(sspi->base_addr + reg); in sun4i_spi_read()
97 writel(value, sspi->base_addr + reg); in sun4i_spi_write()
138 while (len--) { in sun4i_spi_drain_fifo()
139 byte = readb(sspi->base_addr + SUN4I_RXDATA_REG); in sun4i_spi_drain_fifo()
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H A Dspi-sun6i.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2012 - 2014 Allwinner Tech
7 * Maxime Ripard <maxime.ripard@free-electrons.com>
74 #define SUN6I_CLK_CTL_CDR2(div) (((div) & SUN6I_CLK_CTL_CDR2_MASK) << 0) argument
76 #define SUN6I_CLK_CTL_CDR1(div) (((div) & SUN6I_CLK_CTL_CDR1_MASK) << 8) argument
105 struct clk *mclk; member
119 return readl(sspi->base_addr + reg); in sun6i_spi_read()
124 writel(value, sspi->base_addr + reg); in sun6i_spi_write()
157 while (len--) { in sun6i_spi_drain_fifo()
158 byte = readb(sspi->base_addr + SUN6I_RXDATA_REG); in sun6i_spi_drain_fifo()
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/openbmc/linux/drivers/clk/hisilicon/
H A Dclk-hi3620.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2012-2013 Hisilicon Limited.
6 * Copyright (c) 2012-2013 Linaro Limited.
13 #include <linux/clk-provider.h>
19 #include <dt-bindings/clock/hi3620-clock.h>
216 CLK_OF_DECLARE(hi3620_clk, "hisilicon,hi3620-clock", hi3620_clk_init);
283 struct clk_mmc *mclk = to_mmc(hw); in mmc_clk_determine_rate() local
285 if ((req->rate <= 13000000) && (mclk->id == HI3620_MMC_CIUCLK1)) { in mmc_clk_determine_rate()
286 req->rate = 13000000; in mmc_clk_determine_rate()
287 req->best_parent_rate = 26000000; in mmc_clk_determine_rate()
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/openbmc/linux/sound/soc/fsl/
H A Dfsl_mqs.c1 // SPDX-License-Identifier: GPL-2.0
5 // Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
12 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
34 * struct fsl_mqs_soc_data - soc specific data
63 struct clk *mclk; member
77 struct snd_soc_component *component = dai->component; in fsl_mqs_hw_params()
80 int div, res; in fsl_mqs_hw_params() local
83 mclk_rate = clk_get_rate(mqs_priv->mclk); in fsl_mqs_hw_params()
91 div = mclk_rate / (32 * lrclk * 2 * 8); in fsl_mqs_hw_params()
94 if (res == 0 && div > 0 && div <= 256) { in fsl_mqs_hw_params()
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/openbmc/linux/sound/soc/codecs/
H A Dsrc4xxx.c1 // SPDX-License-Identifier: GPL-2.0
5 // Copyright 2021-2022 Deqx Pty Ltd
25 static const DECLARE_TLV_DB_SCALE(src_tlv, -12750, 50, 0);
100 SND_SOC_DAPM_INPUT("MCLK"),
132 /* SRC mclk selection */
133 {"SRC mclk source", "Master (MCLK)", "MCLK"},
134 {"SRC mclk source", "Master (RXCLKI)", "RXMCLKI"},
135 {"SRC mclk source", "Recovered receiver clk", "RXMCLKO"},
156 struct snd_soc_component *component = dai->component; in src4xxx_set_dai_fmt()
163 src4xxx->master[dai->id] = true; in src4xxx_set_dai_fmt()
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H A Dak4375.c1 // SPDX-License-Identifier: GPL-2.0-or-later
23 #define PMCP2 BIT(1) /* Charge Pump 2: Class-G HP Amp */
71 #define DIV BIT(4) macro
118 * from -12.5 to 3 dB in 0.5 dB steps (mute instead of -12.5 dB)
120 static DECLARE_TLV_DB_SCALE(dac_tlv, -1250, 50, 0);
123 * HP-Amp Analog volume control:
124 * from -4.2 to 6 dB in 2 dB steps (mute instead of -4.2 dB)
126 static DECLARE_TLV_DB_SCALE(hpg_tlv, -4200, 20, 0);
132 "+-VDD Operation",
133 "+-1/2VDD Operation"
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H A Dadau17x1.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2011-2014 Analog Devices Inc.
6 * Author: Lars-Peter Clausen <lars@metafoo.de>
26 #include "adau-utils.h"
48 static const DECLARE_TLV_DB_MINMAX(adau17x1_digital_tlv, -9563, 0);
60 SOC_SINGLE("Playback De-emphasis Switch", ADAU17X1_DAC_CONTROL0,
74 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in adau17x1_pll_event()
78 adau->pll_regs[5] = 1; in adau17x1_pll_event()
80 adau->pll_regs[5] = 0; in adau17x1_pll_event()
83 regmap_update_bits(adau->regmap, ADAU17X1_CLOCK_CONTROL, in adau17x1_pll_event()
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H A Dwm8960.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * wm8960.c -- WM8960 ALSA SoC Audio driver
5 * Copyright 2007-11 Wolfson Microelectronics, plc
29 /* R25 - Power 1 */
33 /* R26 - Power 2 */
38 /* R28 - Anti-pop 1 */
45 /* R29 - Anti-pop 2 */
133 struct clk *mclk; member
192 if (wm8960->deemph) { in wm8960_set_deemph()
195 if (abs(deemph_settings[i] - wm8960->lrclk) < in wm8960_set_deemph()
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/openbmc/linux/drivers/media/dvb-frontends/
H A Dm88ds3103.c1 // SPDX-License-Identifier: GPL-2.0-or-later
21 ret = regmap_bulk_read(dev->regmap, reg, &tmp, 1); in m88ds3103_update_bits()
30 return regmap_bulk_write(dev->regmap, reg, &val, 1); in m88ds3103_update_bits()
37 struct i2c_client *client = dev->client; in m88ds3103_wr_reg_val_tab()
41 dev_dbg(&client->dev, "tab_len=%d\n", tab_len); in m88ds3103_wr_reg_val_tab()
44 ret = -EINVAL; in m88ds3103_wr_reg_val_tab()
51 if (i == tab_len - 1 || tab[i].reg != tab[i + 1].reg - 1 || in m88ds3103_wr_reg_val_tab()
52 !((j + 1) % (dev->cfg->i2c_wr_max - 1))) { in m88ds3103_wr_reg_val_tab()
53 ret = regmap_bulk_write(dev->regmap, tab[i].reg - j, buf, j + 1); in m88ds3103_wr_reg_val_tab()
57 j = -1; in m88ds3103_wr_reg_val_tab()
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H A Dbsbe1.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * bsbe1.h - ALPS BSBE1 tuner support
13 0x02, 0x30, /* MCLK = 88 MHz */
57 struct dtv_frontend_properties *p = &fe->dtv_property_cache; in alps_bsbe1_tuner_set_params()
60 u32 div; in alps_bsbe1_tuner_set_params() local
62 struct i2c_adapter *i2c = fe->tuner_priv; in alps_bsbe1_tuner_set_params()
64 if ((p->frequency < 950000) || (p->frequency > 2150000)) in alps_bsbe1_tuner_set_params()
65 return -EINVAL; in alps_bsbe1_tuner_set_params()
67 div = p->frequency / 1000; in alps_bsbe1_tuner_set_params()
68 data[0] = (div >> 8) & 0x7f; in alps_bsbe1_tuner_set_params()
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/openbmc/linux/sound/soc/cirrus/
H A Dep93xx-i2s.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/sound/soc/ep93xx-i2s.c
27 #include <linux/platform_data/dma-ep93xx.h>
30 #include "ep93xx-pcm.h"
60 * 0 - Generate interrupt when FIFO is half empty
61 * 1 - Generate interrupt when FIFO is empty
75 struct clk *mclk; member
85 .name = "i2s-pcm-out",
90 .name = "i2s-pcm-in",
99 __raw_writel(val, info->regs + reg); in ep93xx_i2s_write_reg()
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/openbmc/linux/drivers/i2c/busses/
H A Di2c-bcm2835.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
27 * 16-bit field for the number of SCL cycles to wait after rising SCL
76 writel(val, i2c_dev->regs + reg); in bcm2835_i2c_writel()
81 return readl(i2c_dev->regs + reg); in bcm2835_i2c_readl()
104 return -EINVAL; in clk_bcm2835_i2c_calc_divider()
112 struct clk_bcm2835_i2c *div = to_clk_bcm2835_i2c(hw); in clk_bcm2835_i2c_set_rate() local
116 if (divider == -EINVAL) in clk_bcm2835_i2c_set_rate()
117 return -EINVAL; in clk_bcm2835_i2c_set_rate()
119 bcm2835_i2c_writel(div->i2c_dev, BCM2835_I2C_DIV, divider); in clk_bcm2835_i2c_set_rate()
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/openbmc/linux/sound/soc/jz4740/
H A Djz4740-i2s.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
9 #include <linux/dma-mapping.h>
105 if (!i2s->soc_info->shared_fifo_flush) { in jz4740_i2s_startup()
106 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) in jz4740_i2s_startup()
107 regmap_set_bits(i2s->regmap, JZ_REG_AIC_CTRL, JZ_AIC_CTRL_TFLUSH); in jz4740_i2s_startup()
109 regmap_set_bits(i2s->regmap, JZ_REG_AIC_CTRL, JZ_AIC_CTRL_RFLUSH); in jz4740_i2s_startup()
121 if (i2s->soc_info->shared_fifo_flush) in jz4740_i2s_startup()
122 regmap_set_bits(i2s->regmap, JZ_REG_AIC_CTRL, JZ_AIC_CTRL_TFLUSH); in jz4740_i2s_startup()
124 ret = clk_prepare_enable(i2s->clk_i2s); in jz4740_i2s_startup()
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/openbmc/linux/drivers/media/tuners/
H A Dm88rs6000t.c1 // SPDX-License-Identifier: GPL-2.0-or-later
23 /* set demod main mclk and ts mclk */
26 struct m88rs6000t_dev *dev = fe->tuner_priv; in m88rs6000t_set_demod_mclk()
27 struct dtv_frontend_properties *c = &fe->dtv_property_cache; in m88rs6000t_set_demod_mclk()
31 u32 div, ts_mclk; in m88rs6000t_set_demod_mclk() local
35 /* select demod main mclk */ in m88rs6000t_set_demod_mclk()
36 ret = regmap_read(dev->regmap, 0x15, &utmp); in m88rs6000t_set_demod_mclk()
40 if (c->symbol_rate > 45010000) { in m88rs6000t_set_demod_mclk()
43 reg16 = 115; /* mclk = 110.25MHz */ in m88rs6000t_set_demod_mclk()
47 reg16 = 96; /* mclk = 96MHz */ in m88rs6000t_set_demod_mclk()
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/openbmc/linux/drivers/clk/ingenic/
H A Djz4740-cgu.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
14 #include <dt-bindings/clock/ingenic,jz4740-cgu.h>
51 0x0, 0x1, -1, 0x3,
71 .parents = { JZ4740_CLK_EXT, -1, -1, -1 },
96 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
97 .div = {
98 CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1, 0,
110 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
111 .div = {
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H A Djz4725b-cgu.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/ingenic,jz4725b-cgu.h>
36 0x0, 0x1, -1, 0x3,
56 .parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
81 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
82 .div = {
83 CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1, 0,
95 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
96 .div = {
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H A Djz4760-cgu.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
15 #include <dt-bindings/clock/ingenic,jz4760-cgu.h>
45 0x0, 0x1, -1, 0x2, -1, -1, -1, 0x3,
61 unsigned int m, n, od, m_max = (1 << pll_info->m_bits) - 1; in jz4760_cgu_calc_m_n_od()
67 n = clamp_val(n, 2, 1 << pll_info->n_bits); in jz4760_cgu_calc_m_n_od()
72 for (m = m_max; m >= m_max && n >= 2; n--) { in jz4760_cgu_calc_m_n_od()
133 .bypass_bit = -1,
150 .div = {
151 CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, 0,
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/openbmc/linux/arch/arm/boot/dts/arm/
H A Darm-realview-eb.dtsi23 #include <dt-bindings/interrupt-controller/irq.h>
24 #include <dt-bindings/gpio/gpio.h>
27 #address-cells = <1>;
28 #size-cells = <1>;
29 compatible = "arm,realview-eb";
49 compatible = "regulator-fixed";
50 regulator-name = "vmmc";
51 regulator-min-microvolt = <3300000>;
52 regulator-max-microvolt = <3300000>;
53 regulator-boot-on;
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/openbmc/linux/drivers/gpu/drm/ast/
H A Dast_main.c14 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
70 struct drm_device *dev = &ast->base; in ast_enable_mmio()
74 return devm_add_action_or_reset(dev->dev, ast_enable_mmio_release, ast); in ast_enable_mmio()
84 struct drm_device *dev = &ast->base; in ast_device_config_init()
85 struct pci_dev *pdev = to_pci_dev(dev->dev); in ast_device_config_init()
86 struct device_node *np = dev->dev->of_node; in ast_device_config_init()
95 ast->config_mode = ast_use_defaults; in ast_device_config_init()
97 /* Check if we have device-tree properties */ in ast_device_config_init()
98 if (np && !of_property_read_u32(np, "aspeed,scu-revision-id", &data)) { in ast_device_config_init()
100 ast->config_mode = ast_use_dt; in ast_device_config_init()
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/openbmc/linux/sound/soc/sunxi/
H A Dsun4i-i2s.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Maxime Ripard <maxime.ripard@free-electrons.com>
22 #include <sound/soc-dai.h>
78 #define SUN4I_I2S_CLK_DIV_MCLK(mclk) ((mclk) << 0) argument
85 #define SUN4I_I2S_CHAN_SEL(num_chan) (((num_chan) - 1) << 0)
93 /* Defines required for sun8i-h3 support */
106 #define SUN8I_I2S_FMT0_LRCK_PERIOD(period) ((period - 1) << 8)
119 #define SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(chan) ((chan - 1) << 4)
121 #define SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(chan) (chan - 1)
128 #define SUN8I_I2S_TX_CHAN_EN(num_chan) (((1 << num_chan) - 1) << 4)
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/openbmc/linux/drivers/media/i2c/
H A Dtc358746.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * TC358746 - Parallel <-> CSI-2 Bridge
8 * - Currently only 'Parallel-in -> CSI-out' mode is supported!
13 #include <linux/clk-provider.h>
19 #include <linux/phy/phy-mipi-dphy.h>
24 #include <media/v4l2-ctrls.h>
25 #include <media/v4l2-device.h>
26 #include <media/v4l2-fwnode.h>
27 #include <media/v4l2-mc.h>
29 /* 16-bit registers */
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