Lines Matching +full:mclk +full:- +full:div
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2012 - 2014 Allwinner Tech
7 * Maxime Ripard <maxime.ripard@free-electrons.com>
74 #define SUN6I_CLK_CTL_CDR2(div) (((div) & SUN6I_CLK_CTL_CDR2_MASK) << 0) argument
76 #define SUN6I_CLK_CTL_CDR1(div) (((div) & SUN6I_CLK_CTL_CDR1_MASK) << 8) argument
105 struct clk *mclk; member
119 return readl(sspi->base_addr + reg); in sun6i_spi_read()
124 writel(value, sspi->base_addr + reg); in sun6i_spi_write()
157 while (len--) { in sun6i_spi_drain_fifo()
158 byte = readb(sspi->base_addr + SUN6I_RXDATA_REG); in sun6i_spi_drain_fifo()
159 if (sspi->rx_buf) in sun6i_spi_drain_fifo()
160 *sspi->rx_buf++ = byte; in sun6i_spi_drain_fifo()
171 cnt = sspi->cfg->fifo_depth - sun6i_spi_get_tx_fifo_count(sspi); in sun6i_spi_fill_fifo()
173 len = min((int)cnt, sspi->len); in sun6i_spi_fill_fifo()
175 while (len--) { in sun6i_spi_fill_fifo()
176 byte = sspi->tx_buf ? *sspi->tx_buf++ : 0; in sun6i_spi_fill_fifo()
177 writeb(byte, sspi->base_addr + SUN6I_TXDATA_REG); in sun6i_spi_fill_fifo()
178 sspi->len--; in sun6i_spi_fill_fifo()
184 struct sun6i_spi *sspi = spi_master_get_devdata(spi->master); in sun6i_spi_set_cs()
201 return SUN6I_MAX_XFER_SIZE - 1; in sun6i_spi_max_transfer_size()
208 complete(&sspi->dma_rx_done); in sun6i_spi_dma_rx_cb()
215 struct spi_master *master = sspi->master; in sun6i_spi_prepare_dma()
218 if (tfr->rx_buf) { in sun6i_spi_prepare_dma()
221 .src_addr = sspi->dma_addr_rx, in sun6i_spi_prepare_dma()
226 dmaengine_slave_config(master->dma_rx, &rxconf); in sun6i_spi_prepare_dma()
228 rxdesc = dmaengine_prep_slave_sg(master->dma_rx, in sun6i_spi_prepare_dma()
229 tfr->rx_sg.sgl, in sun6i_spi_prepare_dma()
230 tfr->rx_sg.nents, in sun6i_spi_prepare_dma()
234 return -EINVAL; in sun6i_spi_prepare_dma()
235 rxdesc->callback_param = sspi; in sun6i_spi_prepare_dma()
236 rxdesc->callback = sun6i_spi_dma_rx_cb; in sun6i_spi_prepare_dma()
240 if (tfr->tx_buf) { in sun6i_spi_prepare_dma()
243 .dst_addr = sspi->dma_addr_tx, in sun6i_spi_prepare_dma()
248 dmaengine_slave_config(master->dma_tx, &txconf); in sun6i_spi_prepare_dma()
250 txdesc = dmaengine_prep_slave_sg(master->dma_tx, in sun6i_spi_prepare_dma()
251 tfr->tx_sg.sgl, in sun6i_spi_prepare_dma()
252 tfr->tx_sg.nents, in sun6i_spi_prepare_dma()
257 dmaengine_terminate_sync(master->dma_rx); in sun6i_spi_prepare_dma()
258 return -EINVAL; in sun6i_spi_prepare_dma()
262 if (tfr->rx_buf) { in sun6i_spi_prepare_dma()
264 dma_async_issue_pending(master->dma_rx); in sun6i_spi_prepare_dma()
267 if (tfr->tx_buf) { in sun6i_spi_prepare_dma()
269 dma_async_issue_pending(master->dma_tx); in sun6i_spi_prepare_dma()
280 unsigned int div, div_cdr1, div_cdr2, timeout; in sun6i_spi_transfer_one() local
288 if (tfr->len > SUN6I_MAX_XFER_SIZE) in sun6i_spi_transfer_one()
289 return -EINVAL; in sun6i_spi_transfer_one()
291 reinit_completion(&sspi->done); in sun6i_spi_transfer_one()
292 reinit_completion(&sspi->dma_rx_done); in sun6i_spi_transfer_one()
293 sspi->tx_buf = tfr->tx_buf; in sun6i_spi_transfer_one()
294 sspi->rx_buf = tfr->rx_buf; in sun6i_spi_transfer_one()
295 sspi->len = tfr->len; in sun6i_spi_transfer_one()
296 use_dma = master->can_dma ? master->can_dma(master, spi, tfr) : false; in sun6i_spi_transfer_one()
312 * SPI controller. (See spi-sun4i.c) in sun6i_spi_transfer_one()
314 trig_level = sspi->cfg->fifo_depth / 4 * 3; in sun6i_spi_transfer_one()
321 trig_level = sspi->cfg->fifo_depth / 2; in sun6i_spi_transfer_one()
323 if (tfr->tx_buf) in sun6i_spi_transfer_one()
325 if (tfr->rx_buf) in sun6i_spi_transfer_one()
340 if (spi->mode & SPI_CPOL) in sun6i_spi_transfer_one()
345 if (spi->mode & SPI_CPHA) in sun6i_spi_transfer_one()
350 if (spi->mode & SPI_LSB_FIRST) in sun6i_spi_transfer_one()
359 if (sspi->rx_buf) { in sun6i_spi_transfer_one()
361 rx_len = tfr->len; in sun6i_spi_transfer_one()
371 if (sspi->cfg->has_clk_ctl) { in sun6i_spi_transfer_one()
372 unsigned int mclk_rate = clk_get_rate(sspi->mclk); in sun6i_spi_transfer_one()
375 if (mclk_rate < (2 * tfr->speed_hz)) { in sun6i_spi_transfer_one()
376 clk_set_rate(sspi->mclk, 2 * tfr->speed_hz); in sun6i_spi_transfer_one()
377 mclk_rate = clk_get_rate(sspi->mclk); in sun6i_spi_transfer_one()
394 div_cdr1 = DIV_ROUND_UP(mclk_rate, tfr->speed_hz); in sun6i_spi_transfer_one()
397 reg = SUN6I_CLK_CTL_CDR2(div_cdr2 - 1) | SUN6I_CLK_CTL_DRS; in sun6i_spi_transfer_one()
398 tfr->effective_speed_hz = mclk_rate / (2 * div_cdr2); in sun6i_spi_transfer_one()
400 div = min(SUN6I_CLK_CTL_CDR1_MASK, order_base_2(div_cdr1)); in sun6i_spi_transfer_one()
401 reg = SUN6I_CLK_CTL_CDR1(div); in sun6i_spi_transfer_one()
402 tfr->effective_speed_hz = mclk_rate / (1 << div); in sun6i_spi_transfer_one()
407 clk_set_rate(sspi->mclk, tfr->speed_hz); in sun6i_spi_transfer_one()
408 tfr->effective_speed_hz = clk_get_rate(sspi->mclk); in sun6i_spi_transfer_one()
415 * - normal sample mode : CLK <= 24MHz SDM=1 SDC=0 in sun6i_spi_transfer_one()
416 * - delay half-cycle sample mode : CLK <= 40MHz SDM=0 SDC=0 in sun6i_spi_transfer_one()
417 * - delay one-cycle sample mode : CLK >= 80MHz SDM=0 SDC=1 in sun6i_spi_transfer_one()
422 if (tfr->effective_speed_hz <= 24000000) in sun6i_spi_transfer_one()
424 else if (tfr->effective_speed_hz >= 80000000) in sun6i_spi_transfer_one()
430 /* Finally enable the bus - doing so before might raise SCK to HIGH */ in sun6i_spi_transfer_one()
436 if (sspi->tx_buf) { in sun6i_spi_transfer_one()
437 tx_len = tfr->len; in sun6i_spi_transfer_one()
438 nbits = tfr->tx_nbits; in sun6i_spi_transfer_one()
439 } else if (tfr->rx_buf) { in sun6i_spi_transfer_one()
440 nbits = tfr->rx_nbits; in sun6i_spi_transfer_one()
457 sun6i_spi_write(sspi, SUN6I_BURST_CNT_REG, tfr->len); in sun6i_spi_transfer_one()
466 dev_warn(&master->dev, in sun6i_spi_transfer_one()
468 dev_name(&spi->dev), ret); in sun6i_spi_transfer_one()
477 if (rx_len > sspi->cfg->fifo_depth) in sun6i_spi_transfer_one()
479 if (tx_len > sspi->cfg->fifo_depth) in sun6i_spi_transfer_one()
491 timeout = wait_for_completion_timeout(&sspi->done, in sun6i_spi_transfer_one()
502 timeout = wait_for_completion_timeout(&sspi->dma_rx_done, in sun6i_spi_transfer_one()
505 dev_warn(&master->dev, "RX DMA timeout\n"); in sun6i_spi_transfer_one()
511 dev_warn(&master->dev, in sun6i_spi_transfer_one()
513 dev_name(&spi->dev), tfr->len, tfr->speed_hz, in sun6i_spi_transfer_one()
514 jiffies_to_msecs(end - start), tx_time); in sun6i_spi_transfer_one()
515 ret = -ETIMEDOUT; in sun6i_spi_transfer_one()
521 dmaengine_terminate_sync(master->dma_rx); in sun6i_spi_transfer_one()
522 dmaengine_terminate_sync(master->dma_tx); in sun6i_spi_transfer_one()
536 complete(&sspi->done); in sun6i_spi_handler()
552 if (!sspi->len) in sun6i_spi_handler()
556 /* Only clear the interrupt _after_ re-seeding the FIFO */ in sun6i_spi_handler()
571 ret = clk_prepare_enable(sspi->hclk); in sun6i_spi_runtime_resume()
577 ret = clk_prepare_enable(sspi->mclk); in sun6i_spi_runtime_resume()
583 ret = reset_control_deassert(sspi->rstc); in sun6i_spi_runtime_resume()
595 clk_disable_unprepare(sspi->mclk); in sun6i_spi_runtime_resume()
597 clk_disable_unprepare(sspi->hclk); in sun6i_spi_runtime_resume()
607 reset_control_assert(sspi->rstc); in sun6i_spi_runtime_suspend()
608 clk_disable_unprepare(sspi->mclk); in sun6i_spi_runtime_suspend()
609 clk_disable_unprepare(sspi->hclk); in sun6i_spi_runtime_suspend()
625 return xfer->len > sspi->cfg->fifo_depth; in sun6i_spi_can_dma()
635 master = spi_alloc_master(&pdev->dev, sizeof(struct sun6i_spi)); in sun6i_spi_probe()
637 dev_err(&pdev->dev, "Unable to allocate SPI Master\n"); in sun6i_spi_probe()
638 return -ENOMEM; in sun6i_spi_probe()
644 sspi->base_addr = devm_platform_get_and_ioremap_resource(pdev, 0, &mem); in sun6i_spi_probe()
645 if (IS_ERR(sspi->base_addr)) { in sun6i_spi_probe()
646 ret = PTR_ERR(sspi->base_addr); in sun6i_spi_probe()
652 ret = -ENXIO; in sun6i_spi_probe()
656 ret = devm_request_irq(&pdev->dev, irq, sun6i_spi_handler, in sun6i_spi_probe()
657 0, "sun6i-spi", sspi); in sun6i_spi_probe()
659 dev_err(&pdev->dev, "Cannot request IRQ\n"); in sun6i_spi_probe()
663 sspi->master = master; in sun6i_spi_probe()
664 sspi->cfg = of_device_get_match_data(&pdev->dev); in sun6i_spi_probe()
666 master->max_speed_hz = 100 * 1000 * 1000; in sun6i_spi_probe()
667 master->min_speed_hz = 3 * 1000; in sun6i_spi_probe()
668 master->use_gpio_descriptors = true; in sun6i_spi_probe()
669 master->set_cs = sun6i_spi_set_cs; in sun6i_spi_probe()
670 master->transfer_one = sun6i_spi_transfer_one; in sun6i_spi_probe()
671 master->num_chipselect = 4; in sun6i_spi_probe()
672 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST | in sun6i_spi_probe()
673 sspi->cfg->mode_bits; in sun6i_spi_probe()
674 master->bits_per_word_mask = SPI_BPW_MASK(8); in sun6i_spi_probe()
675 master->dev.of_node = pdev->dev.of_node; in sun6i_spi_probe()
676 master->auto_runtime_pm = true; in sun6i_spi_probe()
677 master->max_transfer_size = sun6i_spi_max_transfer_size; in sun6i_spi_probe()
679 sspi->hclk = devm_clk_get(&pdev->dev, "ahb"); in sun6i_spi_probe()
680 if (IS_ERR(sspi->hclk)) { in sun6i_spi_probe()
681 dev_err(&pdev->dev, "Unable to acquire AHB clock\n"); in sun6i_spi_probe()
682 ret = PTR_ERR(sspi->hclk); in sun6i_spi_probe()
686 sspi->mclk = devm_clk_get(&pdev->dev, "mod"); in sun6i_spi_probe()
687 if (IS_ERR(sspi->mclk)) { in sun6i_spi_probe()
688 dev_err(&pdev->dev, "Unable to acquire module clock\n"); in sun6i_spi_probe()
689 ret = PTR_ERR(sspi->mclk); in sun6i_spi_probe()
693 init_completion(&sspi->done); in sun6i_spi_probe()
694 init_completion(&sspi->dma_rx_done); in sun6i_spi_probe()
696 sspi->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); in sun6i_spi_probe()
697 if (IS_ERR(sspi->rstc)) { in sun6i_spi_probe()
698 dev_err(&pdev->dev, "Couldn't get reset controller\n"); in sun6i_spi_probe()
699 ret = PTR_ERR(sspi->rstc); in sun6i_spi_probe()
703 master->dma_tx = dma_request_chan(&pdev->dev, "tx"); in sun6i_spi_probe()
704 if (IS_ERR(master->dma_tx)) { in sun6i_spi_probe()
706 if (PTR_ERR(master->dma_tx) == -EPROBE_DEFER) { in sun6i_spi_probe()
707 ret = -EPROBE_DEFER; in sun6i_spi_probe()
710 dev_warn(&pdev->dev, "Failed to request TX DMA channel\n"); in sun6i_spi_probe()
711 master->dma_tx = NULL; in sun6i_spi_probe()
714 master->dma_rx = dma_request_chan(&pdev->dev, "rx"); in sun6i_spi_probe()
715 if (IS_ERR(master->dma_rx)) { in sun6i_spi_probe()
716 if (PTR_ERR(master->dma_rx) == -EPROBE_DEFER) { in sun6i_spi_probe()
717 ret = -EPROBE_DEFER; in sun6i_spi_probe()
720 dev_warn(&pdev->dev, "Failed to request RX DMA channel\n"); in sun6i_spi_probe()
721 master->dma_rx = NULL; in sun6i_spi_probe()
724 if (master->dma_tx && master->dma_rx) { in sun6i_spi_probe()
725 sspi->dma_addr_tx = mem->start + SUN6I_TXDATA_REG; in sun6i_spi_probe()
726 sspi->dma_addr_rx = mem->start + SUN6I_RXDATA_REG; in sun6i_spi_probe()
727 master->can_dma = sun6i_spi_can_dma; in sun6i_spi_probe()
731 * This wake-up/shutdown pattern is to be able to have the in sun6i_spi_probe()
734 ret = sun6i_spi_runtime_resume(&pdev->dev); in sun6i_spi_probe()
736 dev_err(&pdev->dev, "Couldn't resume the device\n"); in sun6i_spi_probe()
740 pm_runtime_set_autosuspend_delay(&pdev->dev, SUN6I_AUTOSUSPEND_TIMEOUT); in sun6i_spi_probe()
741 pm_runtime_use_autosuspend(&pdev->dev); in sun6i_spi_probe()
742 pm_runtime_set_active(&pdev->dev); in sun6i_spi_probe()
743 pm_runtime_enable(&pdev->dev); in sun6i_spi_probe()
745 ret = devm_spi_register_master(&pdev->dev, master); in sun6i_spi_probe()
747 dev_err(&pdev->dev, "cannot register SPI master\n"); in sun6i_spi_probe()
754 pm_runtime_disable(&pdev->dev); in sun6i_spi_probe()
755 sun6i_spi_runtime_suspend(&pdev->dev); in sun6i_spi_probe()
757 if (master->dma_rx) in sun6i_spi_probe()
758 dma_release_channel(master->dma_rx); in sun6i_spi_probe()
760 if (master->dma_tx) in sun6i_spi_probe()
761 dma_release_channel(master->dma_tx); in sun6i_spi_probe()
771 pm_runtime_force_suspend(&pdev->dev); in sun6i_spi_remove()
773 if (master->dma_tx) in sun6i_spi_remove()
774 dma_release_channel(master->dma_tx); in sun6i_spi_remove()
775 if (master->dma_rx) in sun6i_spi_remove()
776 dma_release_channel(master->dma_rx); in sun6i_spi_remove()
795 { .compatible = "allwinner,sun6i-a31-spi", .data = &sun6i_a31_spi_cfg },
796 { .compatible = "allwinner,sun8i-h3-spi", .data = &sun8i_h3_spi_cfg },
798 .compatible = "allwinner,sun50i-r329-spi",
814 .name = "sun6i-spi",
822 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");