spi: sun6i: fix race between DMA RX transfer completion and RX FIFO drain

Previously the transfer complete IRQ immediately drained to RX FIFO to
read any data remaining in FIFO to the RX buffer. Thi

spi: sun6i: fix race between DMA RX transfer completion and RX FIFO drain

Previously the transfer complete IRQ immediately drained to RX FIFO to
read any data remaining in FIFO to the RX buffer. This behaviour is
correct when dealing with SPI in interrupt mode. However in DMA mode the
transfer complete interrupt still fires as soon as all bytes to be
transferred have been stored in the FIFO. At that point data in the FIFO
still needs to be picked up by the DMA engine. Thus the drain procedure
and DMA engine end up racing to read from RX FIFO, corrupting any data
read. Additionally the RX buffer pointer is never adjusted according to
DMA progress in DMA mode, thus calling the RX FIFO drain procedure in DMA
mode is a bug.
Fix corruptions in DMA RX mode by draining RX FIFO only in interrupt mode.
Also wait for completion of RX DMA when in DMA mode before returning to
ensure all data has been copied to the supplied memory buffer.

Signed-off-by: Tobias Schramm <t.schramm@manjaro.org>
Link: https://lore.kernel.org/r/20230827152558.5368-3-t.schramm@manjaro.org
Signed-off-by: Mark Brown <broonie@kernel.org>

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spi: sun6i: reduce DMA RX transfer width to single byte

Through empirical testing it has been determined that sometimes RX SPI
transfers with DMA enabled return corrupted data. This is down to singl

spi: sun6i: reduce DMA RX transfer width to single byte

Through empirical testing it has been determined that sometimes RX SPI
transfers with DMA enabled return corrupted data. This is down to single
or even multiple bytes lost during DMA transfer from SPI peripheral to
memory. It seems the RX FIFO within the SPI peripheral can become
confused when performing bus read accesses wider than a single byte to it
during an active SPI transfer.

This patch reduces the width of individual DMA read accesses to the
RX FIFO to a single byte to mitigate that issue.

Signed-off-by: Tobias Schramm <t.schramm@manjaro.org>
Link: https://lore.kernel.org/r/20230827152558.5368-2-t.schramm@manjaro.org
Signed-off-by: Mark Brown <broonie@kernel.org>

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spi: Explicitly include correct DT includes

The DT of_device.h and of_platform.h date back to the separate
of_platform_bus_type before it as merged into the regular platform bus.
As part of that mer

spi: Explicitly include correct DT includes

The DT of_device.h and of_platform.h date back to the separate
of_platform_bus_type before it as merged into the regular platform bus.
As part of that merge prepping Arm DT support 13 years ago, they
"temporarily" include each other. They also include platform_device.h
and of.h. As a result, there's a pretty much random mix of those include
files used throughout the tree. In order to detangle these headers and
replace the implicit includes with struct declarations, users need to
explicitly include the correct includes.

Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230714174955.4064174-1-robh@kernel.org
Signed-off-by: Mark Brown <broonie@kernel.org>

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spi: sun6i: add dual and quad SPI modes support for R329/D1/R528/T113s

Listed SoCs have SPI controllers that can operate in dual or quad modes.
This patch adds dual/quad mode bits for spi_master on

spi: sun6i: add dual and quad SPI modes support for R329/D1/R528/T113s

Listed SoCs have SPI controllers that can operate in dual or quad modes.
This patch adds dual/quad mode bits for spi_master on these SoCS.

Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com>
Link: https://lore.kernel.org/r/20230624131632.2972546-3-bigunclemax@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>

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spi: sun6i: add quirk for dual and quad SPI modes support

New Allwinner's SPI controllers can support dual and quad SPI modes.
To enable one of these modes, we should set the corresponding bit in
th

spi: sun6i: add quirk for dual and quad SPI modes support

New Allwinner's SPI controllers can support dual and quad SPI modes.
To enable one of these modes, we should set the corresponding bit in
the SUN6I_BURST_CTL_CNT_REG register. DRM (28 bits) for dual mode and
Quad_EN (29 bits) for quad transmission.

Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com>
Link: https://lore.kernel.org/r/20230624131632.2972546-2-bigunclemax@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>

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spi: sun6i: Use the new helper to derive the xfer timeout value

A helper was recently added to the core to factorize common code between
drivers, like the amount of time a driver should wait for a t

spi: sun6i: Use the new helper to derive the xfer timeout value

A helper was recently added to the core to factorize common code between
drivers, like the amount of time a driver should wait for a transfer to
happen.

It is of course possible to use a default value (like eg. 1s) but it is
way stronger to adapt this amount of time to the transfer. Indeed, long
transfers (eg. 4MiB) on a slow single-spi bus might take more than the
usual second of timeout and prevent lengthy transfers.

The core helper was heavily inspired by the logic applied in this
driver, the only difference being the minimum amount of time which was
enlarged from 0.1s to 0.5s.

Use this helper instead of open-coding it.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Jernej Škrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/Message-Id: <20230622090634.3411468-4-miquel.raynal@bootlin.com>
Signed-off-by: Mark Brown <broonie@kernel.org>

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spi: sun6i: add support for R329/D1/R528/T113s SPI controllers

These SoCs has two SPI controllers. One of it is quite similar to previous
ones, but with internal clock divider removed; the other add

spi: sun6i: add support for R329/D1/R528/T113s SPI controllers

These SoCs has two SPI controllers. One of it is quite similar to previous
ones, but with internal clock divider removed; the other added MIPI DBI
Type-C offload based on the first one.

Add basical support for these controllers. As we're not going to
support the DBI functionality now, just implement the two kinds of
controllers as the same.

Co-developed-by: Icenowy Zheng <icenowy@aosc.io
Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com
Reviewed-by: Andre Przywara <andre.przywara@arm.com
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com
Link: https://lore.kernel.org/r/20230510081121.3463710-5-bigunclemax@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org

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spi: sun6i: add quirk for in-controller clock divider

Previously SPI controllers in Allwinner SoCs has a clock divider inside.
However now the clock divider is removed and to set the transfer clock

spi: sun6i: add quirk for in-controller clock divider

Previously SPI controllers in Allwinner SoCs has a clock divider inside.
However now the clock divider is removed and to set the transfer clock
rate it's only needed to set the SPI module clock to the target value
and configure a proper work mode.

According to the datasheet there are three work modes:

| SPI Sample Mode | SDM(bit13) | SDC(bit11) | Run Clock |
|-------------------------|------------|------------|-----------|
| normal sample | 1 | 0 | <= 24 MHz |
| delay half cycle sample | 0 | 0 | <= 40 MHz |
| delay one cycle sample | 0 | 1 | >= 80 MHz |

Add a quirk for this kind of SPI controllers.

Co-developed-by: Icenowy Zheng <icenowy@aosc.io
Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com
Reviewed-by: Andre Przywara <andre.przywara@arm.com
Link: https://lore.kernel.org/r/20230510081121.3463710-4-bigunclemax@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org

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spi: sun6i: change OF match data to a struct

As we're adding more properties to the OF match data, convert it to a
struct now.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io
Signed-off-by: Maksim Ki

spi: sun6i: change OF match data to a struct

As we're adding more properties to the OF match data, convert it to a
struct now.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io
Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com
Reviewed-by: Samuel Holland <samuel@sholland.org
Reviewed-by: Andre Przywara <andre.przywara@arm.com
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com
Link: https://lore.kernel.org/r/20230510081121.3463710-3-bigunclemax@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org

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spi: Replace all spi->chip_select and spi->cs_gpiod references with function call

Supporting multi-cs in spi drivers would require the chip_select & cs_gpiod
members of struct spi_device to be an ar

spi: Replace all spi->chip_select and spi->cs_gpiod references with function call

Supporting multi-cs in spi drivers would require the chip_select & cs_gpiod
members of struct spi_device to be an array. But changing the type of these
members to array would break the spi driver functionality. To make the
transition smoother introduced four new APIs to get/set the
spi->chip_select & spi->cs_gpiod and replaced all spi->chip_select and
spi->cs_gpiod references with get or set API calls.
While adding multi-cs support in further patches the chip_select & cs_gpiod
members of the spi_device structure would be converted to arrays & the
"idx" parameter of the APIs would be used as array index i.e.,
spi->chip_select[idx] & spi->cs_gpiod[idx] respectively.

Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com>
Acked-by: Heiko Stuebner <heiko@sntech.de> # Rockchip drivers
Reviewed-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org> # Aspeed driver
Reviewed-by: Dhruva Gole <d-gole@ti.com> # SPI Cadence QSPI
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> # spi-stm32-qspi
Acked-by: William Zhang <william.zhang@broadcom.com> # bcm63xx-hsspi driver
Reviewed-by: Serge Semin <fancer.lancer@gmail.com> # DW SSI part
Link: https://lore.kernel.org/r/167847070432.26.15076794204368669839@mailman-core.alsa-project.org
Signed-off-by: Mark Brown <broonie@kernel.org>

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spi: sun6i: Convert to platform remove callback returning void

The .remove() callback for a platform driver returns an int which makes
many driver authors wrongly assume it's possible to do error ha

spi: sun6i: Convert to platform remove callback returning void

The .remove() callback for a platform driver returns an int which makes
many driver authors wrongly assume it's possible to do error handling by
returning an error code. However the value returned is (mostly) ignored
and this typically results in resource leaks. To improve here there is a
quest to make the remove callback return void. In the first step of this
quest all drivers are converted to .remove_new() which already returns
void.

Trivially convert this driver from always returning zero in the remove
callback to the void returning variant.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Link: https://lore.kernel.org/r/20230303172041.2103336-76-u.kleine-koenig@pengutronix.de
Signed-off-by: Mark Brown <broonie@kernel.org>

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spi: spi-sun6i: Fix chipselect/clock bug

The current sun6i SPI implementation initializes the transfer too early,
resulting in SCK going high before the transfer. When using an additional
(gpio) chi

spi: spi-sun6i: Fix chipselect/clock bug

The current sun6i SPI implementation initializes the transfer too early,
resulting in SCK going high before the transfer. When using an additional
(gpio) chipselect with sun6i, the chipselect is asserted at a time when
clock is high, making the SPI transfer fail.

This is due to SUN6I_GBL_CTL_BUS_ENABLE being written into
SUN6I_GBL_CTL_REG at an early stage. Moving that to the transfer
function, hence, right before the transfer starts, mitigates that
problem.

Fixes: 3558fe900e8af (spi: sunxi: Add Allwinner A31 SPI controller driver)
Signed-off-by: Mirko Vogt <mirko-dev|linux@nanl.de>
Signed-off-by: Ralf Schlatterbeck <rsc@runtux.com>
Link: https://lore.kernel.org/r/20210614144507.y3udezjfbko7eavv@runtux.com
Signed-off-by: Mark Brown <broonie@kernel.org>

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spi: spi-sun6i: enable autosuspend feature

If SPI is used for periodic polling any sensor, significant delays
sometimes appear. Switching on module clocks during resume lead to delays.
Enabling auto

spi: spi-sun6i: enable autosuspend feature

If SPI is used for periodic polling any sensor, significant delays
sometimes appear. Switching on module clocks during resume lead to delays.
Enabling autosuspend mode causes the controller to not suspend between
SPI transfers and the delays disappear.

The commit also remove unnecessary call to pm_runtime_idle() used
to explicit put device to suspended state. Without pm_runtime_idle() PM
core will put device in the suspended state just after probe() returns.

Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>
Acked-by: Maxime Ripard <mripard@kernel.org>
Link: https://lore.kernel.org/r/20201019150343.2520-1-akochetkov@lintech.ru
Signed-off-by: Mark Brown <broonie@kernel.org>

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spi: spi-sun6i: implement DMA-based transfer mode

DMA-based transfer will be enabled if data length is larger than FIFO size
(64 bytes for A64). This greatly reduce number of interrupts for
transfer

spi: spi-sun6i: implement DMA-based transfer mode

DMA-based transfer will be enabled if data length is larger than FIFO size
(64 bytes for A64). This greatly reduce number of interrupts for
transferring data.

For smaller data size PIO mode will be used. In PIO mode whole buffer will
be loaded into FIFO.

If driver failed to request DMA channels then it fallback for PIO mode.

Tested on SOPINE (https://www.pine64.org/sopine/)

Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>
Acked-by: Maxime Ripard <mripard@kernel.org>
Link: https://lore.kernel.org/r/20201022075221.23332-1-akochetkov@lintech.ru
Signed-off-by: Mark Brown <broonie@kernel.org>

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spi: spi-sun6i: Fix chipselect/clock bug

[ Upstream commit 0d7993b234c9fad8cb6bec6adfaa74694ba85ecb ]

The current sun6i SPI implementation initializes the transfer too early,
resulting in SCK going

spi: spi-sun6i: Fix chipselect/clock bug

[ Upstream commit 0d7993b234c9fad8cb6bec6adfaa74694ba85ecb ]

The current sun6i SPI implementation initializes the transfer too early,
resulting in SCK going high before the transfer. When using an additional
(gpio) chipselect with sun6i, the chipselect is asserted at a time when
clock is high, making the SPI transfer fail.

This is due to SUN6I_GBL_CTL_BUS_ENABLE being written into
SUN6I_GBL_CTL_REG at an early stage. Moving that to the transfer
function, hence, right before the transfer starts, mitigates that
problem.

Fixes: 3558fe900e8af (spi: sunxi: Add Allwinner A31 SPI controller driver)
Signed-off-by: Mirko Vogt <mirko-dev|linux@nanl.de>
Signed-off-by: Ralf Schlatterbeck <rsc@runtux.com>
Link: https://lore.kernel.org/r/20210614144507.y3udezjfbko7eavv@runtux.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

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spi: spi-sun6i: sun6i_spi_transfer_one(): enable RF_RDY interrupt only if needed

In sun6i_spi_transfer_one() the RX FIFO Ready (SUN6I_INT_CTL_RF_RDY) is
unconditionally enabled.

A RX interrupt is o

spi: spi-sun6i: sun6i_spi_transfer_one(): enable RF_RDY interrupt only if needed

In sun6i_spi_transfer_one() the RX FIFO Ready (SUN6I_INT_CTL_RF_RDY) is
unconditionally enabled.

A RX interrupt is only needed, if more data than fits into the FIFO is going to
be received during this transfer. As the RX-FIFO is drained during transfer
complete interrupt, enable the RX FIFO Ready interrupt only if the data doesn't
fit into the FIFO.

Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Acked-by: Maxime Ripard <mripard@kernel.org>
Link: https://lore.kernel.org/r/20200706143443.9855-11-mkl@pengutronix.de
Signed-off-by: Mark Brown <broonie@kernel.org>

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spi: spi-sun6i: sun6i_spi_transfer_one(): collate write to Interrupt Control Register

In sun6i_spi_transfer_one() the Interrupt Control Register is written three
times. This patch collates the three

spi: spi-sun6i: sun6i_spi_transfer_one(): collate write to Interrupt Control Register

In sun6i_spi_transfer_one() the Interrupt Control Register is written three
times. This patch collates the three writes into one.

Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Acked-by: Maxime Ripard <mripard@kernel.org>
Link: https://lore.kernel.org/r/20200706143443.9855-10-mkl@pengutronix.de
Signed-off-by: Mark Brown <broonie@kernel.org>

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spi: spi-sun6i: sun6i_spi_fill_fifo(): remove not needed length argument

The function sun6i_spi_fill_fifo() is called with a length argument of
"sspi->fifo_depth" and "SUN6I_FIFO_DEPTH".

The driver

spi: spi-sun6i: sun6i_spi_fill_fifo(): remove not needed length argument

The function sun6i_spi_fill_fifo() is called with a length argument of
"sspi->fifo_depth" and "SUN6I_FIFO_DEPTH".

The driver reads the number of free bytes in the FIFO from the hardware and
uses the length argument to limit this value. This is not needed as the number
of free bytes in the FIFO is always less or equal the depth of the FIFO.

This patch removes the length argument and check.

Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Acked-by: Maxime Ripard <mripard@kernel.org>
Link: https://lore.kernel.org/r/20200706143443.9855-9-mkl@pengutronix.de
Signed-off-by: Mark Brown <broonie@kernel.org>

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spi: spi-sun6i: sun6i_spi_drain_fifo(): remove not needed length argument

The function sun6i_spi_drain_fifo() is called with a length argument of
"sspi->fifo_depth" and "SUN6I_FIFO_DEPTH".

The driv

spi: spi-sun6i: sun6i_spi_drain_fifo(): remove not needed length argument

The function sun6i_spi_drain_fifo() is called with a length argument of
"sspi->fifo_depth" and "SUN6I_FIFO_DEPTH".

The driver reads the number of available bytes to read from the FIFO from the
hardware and uses the length argument to limit this value. This is not needed
as the FIFO can contain only the fifo depth number of bytes.

This patch removes the length argument and check.

Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Acked-by: Maxime Ripard <mripard@kernel.org>
Link: https://lore.kernel.org/r/20200706143443.9855-8-mkl@pengutronix.de
Signed-off-by: Mark Brown <broonie@kernel.org>

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spi: spi-sun6i: sun6i_spi_drain_fifo(): introduce sun6i_spi_get_rx_fifo_count() and make use of it

This patch introduces the function sun6i_spi_get_rx_fifo_count(), similar to
the existing sun6i_spi

spi: spi-sun6i: sun6i_spi_drain_fifo(): introduce sun6i_spi_get_rx_fifo_count() and make use of it

This patch introduces the function sun6i_spi_get_rx_fifo_count(), similar to
the existing sun6i_spi_get_tx_fifo_count(), to make the sun6i_spi_drain_fifo()
function a bit easier to read.

Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Acked-by: Maxime Ripard <mripard@kernel.org>
Link: https://lore.kernel.org/r/20200706143443.9855-7-mkl@pengutronix.de
Signed-off-by: Mark Brown <broonie@kernel.org>

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spi: spi-sun6i: sun6i_spi_get_tx_fifo_count: Convert manual shift+mask to FIELD_GET()

This patch converts the manual shift+mask in sun6i_spi_get_tx_fifo_count() to
make use of FIELD_GET()

Signed-of

spi: spi-sun6i: sun6i_spi_get_tx_fifo_count: Convert manual shift+mask to FIELD_GET()

This patch converts the manual shift+mask in sun6i_spi_get_tx_fifo_count() to
make use of FIELD_GET()

Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Link: https://lore.kernel.org/r/20200706143443.9855-6-mkl@pengutronix.de
Signed-off-by: Mark Brown <broonie@kernel.org>

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spi: spi-sun6i: sun6i_spi_transfer_one(): remove not needed masking of transfer length

In sun6i_spi_transfer_one() the driver ensures that the length of the transfer
is smaller or equal to SUN6I_MAX

spi: spi-sun6i: sun6i_spi_transfer_one(): remove not needed masking of transfer length

In sun6i_spi_transfer_one() the driver ensures that the length of the transfer
is smaller or equal to SUN6I_MAX_XFER_SIZE. This means the masking of the
length to SUN6I_MAX_XFER_SIZE can be skipped when writing the transfer length
into the registers.

This patch removes the useless masking of the transfer length to
SUN6I_MAX_XFER_SIZE.

Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Acked-by: Maxime Ripard <mripard@kernel.org>
Link: https://lore.kernel.org/r/20200706143443.9855-5-mkl@pengutronix.de
Signed-off-by: Mark Brown <broonie@kernel.org>

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spi: spi-sun6i: sun6i_spi_transfer_one(): remove useless goto

This patch removes an useless goto at the end of
sun6i_spi_transfer_one().

Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Acked-

spi: spi-sun6i: sun6i_spi_transfer_one(): remove useless goto

This patch removes an useless goto at the end of
sun6i_spi_transfer_one().

Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Acked-by: Maxime Ripard <mripard@kernel.org>
Link: https://lore.kernel.org/r/20200706143443.9855-4-mkl@pengutronix.de
Signed-off-by: Mark Brown <broonie@kernel.org>

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spi: spi-sun6i: sun6i_spi_transfer_one(): report effectivly used speed_hz of transfer

This patch implementes the reporting of the effectivly used speed_hz for the
transfer by setting tfr->effective_

spi: spi-sun6i: sun6i_spi_transfer_one(): report effectivly used speed_hz of transfer

This patch implementes the reporting of the effectivly used speed_hz for the
transfer by setting tfr->effective_speed_hz.

See the following patch, which adds this feature to the SPI core for more
information:

5d7e2b5ed585 spi: core: allow reporting the effectivly used speed_hz for a transfer

Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Acked-by: Maxime Ripard <mripard@kernel.org>
Link: https://lore.kernel.org/r/20200706143443.9855-3-mkl@pengutronix.de
Signed-off-by: Mark Brown <broonie@kernel.org>

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spi: spi-sun6i: sun6i_spi_transfer_one(): fix setting of clock rate

A SPI transfer defines the _maximum_ speed of the SPI transfer. However the
driver doesn't take into account that the clock divide

spi: spi-sun6i: sun6i_spi_transfer_one(): fix setting of clock rate

A SPI transfer defines the _maximum_ speed of the SPI transfer. However the
driver doesn't take into account that the clock divider is always rounded down
(due to integer arithmetics). This results in a too high clock rate for the SPI
transfer.

E.g.: with a mclk_rate of 24 MHz and a SPI transfer speed of 10 MHz, the
original code calculates a reg of "0", which results in a effective divider of
"2" and a 12 MHz clock for the SPI transfer.

This patch fixes the issue by using DIV_ROUND_UP() instead of a plain
integer division.

While there simplify the divider calculation for the CDR1 case, use
order_base_2() instead of two ilog2() calculations.

Fixes: 3558fe900e8a ("spi: sunxi: Add Allwinner A31 SPI controller driver")
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Acked-by: Maxime Ripard <mripard@kernel.org>
Link: https://lore.kernel.org/r/20200706143443.9855-2-mkl@pengutronix.de
Signed-off-by: Mark Brown <broonie@kernel.org>

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