11802d0beSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
23e086edfSolivier moysan /*
33e086edfSolivier moysan * STM32 ALSA SoC Digital Audio Interface (SAI) driver.
43e086edfSolivier moysan *
53e086edfSolivier moysan * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
63e086edfSolivier moysan * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics.
73e086edfSolivier moysan */
83e086edfSolivier moysan
93e086edfSolivier moysan #include <linux/clk.h>
108307b2afSOlivier Moysan #include <linux/clk-provider.h>
113e086edfSolivier moysan #include <linux/kernel.h>
123e086edfSolivier moysan #include <linux/module.h>
133e086edfSolivier moysan #include <linux/of_irq.h>
143e086edfSolivier moysan #include <linux/of_platform.h>
154e723e75SOlivier Moysan #include <linux/pm_runtime.h>
163e086edfSolivier moysan #include <linux/regmap.h>
173e086edfSolivier moysan
186eb17d70SOlivier Moysan #include <sound/asoundef.h>
193e086edfSolivier moysan #include <sound/core.h>
203e086edfSolivier moysan #include <sound/dmaengine_pcm.h>
213e086edfSolivier moysan #include <sound/pcm_params.h>
223e086edfSolivier moysan
233e086edfSolivier moysan #include "stm32_sai.h"
243e086edfSolivier moysan
253e086edfSolivier moysan #define SAI_FREE_PROTOCOL 0x0
266eb17d70SOlivier Moysan #define SAI_SPDIF_PROTOCOL 0x1
273e086edfSolivier moysan
283e086edfSolivier moysan #define SAI_SLOT_SIZE_AUTO 0x0
293e086edfSolivier moysan #define SAI_SLOT_SIZE_16 0x1
303e086edfSolivier moysan #define SAI_SLOT_SIZE_32 0x2
313e086edfSolivier moysan
323e086edfSolivier moysan #define SAI_DATASIZE_8 0x2
333e086edfSolivier moysan #define SAI_DATASIZE_10 0x3
343e086edfSolivier moysan #define SAI_DATASIZE_16 0x4
353e086edfSolivier moysan #define SAI_DATASIZE_20 0x5
363e086edfSolivier moysan #define SAI_DATASIZE_24 0x6
373e086edfSolivier moysan #define SAI_DATASIZE_32 0x7
383e086edfSolivier moysan
393e086edfSolivier moysan #define STM_SAI_DAI_NAME_SIZE 15
403e086edfSolivier moysan
413e086edfSolivier moysan #define STM_SAI_IS_PLAYBACK(ip) ((ip)->dir == SNDRV_PCM_STREAM_PLAYBACK)
423e086edfSolivier moysan #define STM_SAI_IS_CAPTURE(ip) ((ip)->dir == SNDRV_PCM_STREAM_CAPTURE)
433e086edfSolivier moysan
443e086edfSolivier moysan #define STM_SAI_A_ID 0x0
453e086edfSolivier moysan #define STM_SAI_B_ID 0x1
463e086edfSolivier moysan
4703e78a24Solivier moysan #define STM_SAI_IS_SUB_A(x) ((x)->id == STM_SAI_A_ID)
483e086edfSolivier moysan
495914d285SOlivier Moysan #define SAI_SYNC_NONE 0x0
505914d285SOlivier Moysan #define SAI_SYNC_INTERNAL 0x1
515914d285SOlivier Moysan #define SAI_SYNC_EXTERNAL 0x2
525914d285SOlivier Moysan
536eb17d70SOlivier Moysan #define STM_SAI_PROTOCOL_IS_SPDIF(ip) ((ip)->spdif)
541d9c95c1SOlivier Moysan #define STM_SAI_HAS_SPDIF(x) ((x)->pdata->conf.has_spdif_pdm)
551d9c95c1SOlivier Moysan #define STM_SAI_HAS_PDM(x) ((x)->pdata->conf.has_spdif_pdm)
565914d285SOlivier Moysan #define STM_SAI_HAS_EXT_SYNC(x) (!STM_SAI_IS_F4(sai->pdata))
575914d285SOlivier Moysan
586eb17d70SOlivier Moysan #define SAI_IEC60958_BLOCK_FRAMES 192
596eb17d70SOlivier Moysan #define SAI_IEC60958_STATUS_BYTES 24
606eb17d70SOlivier Moysan
618307b2afSOlivier Moysan #define SAI_MCLK_NAME_LEN 32
62e37c2deaSOlivier Moysan #define SAI_RATE_11K 11025
638307b2afSOlivier Moysan
643e086edfSolivier moysan /**
653e086edfSolivier moysan * struct stm32_sai_sub_data - private data of SAI sub block (block A or B)
663e086edfSolivier moysan * @pdev: device data pointer
673e086edfSolivier moysan * @regmap: SAI register map pointer
6803e78a24Solivier moysan * @regmap_config: SAI sub block register map configuration pointer
693e086edfSolivier moysan * @dma_params: dma configuration data for rx or tx channel
703e086edfSolivier moysan * @cpu_dai_drv: DAI driver data pointer
713e086edfSolivier moysan * @cpu_dai: DAI runtime data pointer
723e086edfSolivier moysan * @substream: PCM substream data pointer
733e086edfSolivier moysan * @pdata: SAI block parent data pointer
745914d285SOlivier Moysan * @np_sync_provider: synchronization provider node
753e086edfSolivier moysan * @sai_ck: kernel clock feeding the SAI clock generator
768307b2afSOlivier Moysan * @sai_mclk: master clock from SAI mclk provider
773e086edfSolivier moysan * @phys_addr: SAI registers physical base address
783e086edfSolivier moysan * @mclk_rate: SAI block master clock frequency (Hz). set at init
793e086edfSolivier moysan * @id: SAI sub block id corresponding to sub-block A or B
803e086edfSolivier moysan * @dir: SAI block direction (playback or capture). set at init
813e086edfSolivier moysan * @master: SAI block mode flag. (true=master, false=slave) set at init
826eb17d70SOlivier Moysan * @spdif: SAI S/PDIF iec60958 mode flag. set at init
833e086edfSolivier moysan * @fmt: SAI block format. relevant only for custom protocols. set at init
843e086edfSolivier moysan * @sync: SAI block synchronization mode. (none, internal or external)
855914d285SOlivier Moysan * @synco: SAI block ext sync source (provider setting). (none, sub-block A/B)
865914d285SOlivier Moysan * @synci: SAI block ext sync source (client setting). (SAI sync provider index)
873e086edfSolivier moysan * @fs_length: frame synchronization length. depends on protocol settings
883e086edfSolivier moysan * @slots: rx or tx slot number
893e086edfSolivier moysan * @slot_width: rx or tx slot width in bits
903e086edfSolivier moysan * @slot_mask: rx or tx active slots mask. set at init or at runtime
913e086edfSolivier moysan * @data_size: PCM data width. corresponds to PCM substream width.
926eb17d70SOlivier Moysan * @spdif_frm_cnt: S/PDIF playback frame counter
935f8a1000SOlivier Moysan * @iec958: iec958 data
94187e01d0Solivier moysan * @ctrl_lock: control lock
9526f98e82SOlivier Moysan * @irq_lock: prevent race condition with IRQ
963e086edfSolivier moysan */
973e086edfSolivier moysan struct stm32_sai_sub_data {
983e086edfSolivier moysan struct platform_device *pdev;
993e086edfSolivier moysan struct regmap *regmap;
10003e78a24Solivier moysan const struct regmap_config *regmap_config;
1013e086edfSolivier moysan struct snd_dmaengine_dai_dma_data dma_params;
1028f8a5488SArnaud Pouliquen struct snd_soc_dai_driver cpu_dai_drv;
1033e086edfSolivier moysan struct snd_soc_dai *cpu_dai;
1043e086edfSolivier moysan struct snd_pcm_substream *substream;
1053e086edfSolivier moysan struct stm32_sai_data *pdata;
1065914d285SOlivier Moysan struct device_node *np_sync_provider;
1073e086edfSolivier moysan struct clk *sai_ck;
1088307b2afSOlivier Moysan struct clk *sai_mclk;
1093e086edfSolivier moysan dma_addr_t phys_addr;
1103e086edfSolivier moysan unsigned int mclk_rate;
1113e086edfSolivier moysan unsigned int id;
1123e086edfSolivier moysan int dir;
1133e086edfSolivier moysan bool master;
1146eb17d70SOlivier Moysan bool spdif;
1153e086edfSolivier moysan int fmt;
1163e086edfSolivier moysan int sync;
1175914d285SOlivier Moysan int synco;
1185914d285SOlivier Moysan int synci;
1193e086edfSolivier moysan int fs_length;
1203e086edfSolivier moysan int slots;
1213e086edfSolivier moysan int slot_width;
1223e086edfSolivier moysan int slot_mask;
1233e086edfSolivier moysan int data_size;
1246eb17d70SOlivier Moysan unsigned int spdif_frm_cnt;
125187e01d0Solivier moysan struct snd_aes_iec958 iec958;
126187e01d0Solivier moysan struct mutex ctrl_lock; /* protect resources accessed by controls */
12726f98e82SOlivier Moysan spinlock_t irq_lock; /* used to prevent race condition with IRQ */
1283e086edfSolivier moysan };
1293e086edfSolivier moysan
1303e086edfSolivier moysan enum stm32_sai_fifo_th {
1313e086edfSolivier moysan STM_SAI_FIFO_TH_EMPTY,
1323e086edfSolivier moysan STM_SAI_FIFO_TH_QUARTER,
1333e086edfSolivier moysan STM_SAI_FIFO_TH_HALF,
1343e086edfSolivier moysan STM_SAI_FIFO_TH_3_QUARTER,
1353e086edfSolivier moysan STM_SAI_FIFO_TH_FULL,
1363e086edfSolivier moysan };
1373e086edfSolivier moysan
stm32_sai_sub_readable_reg(struct device * dev,unsigned int reg)1383e086edfSolivier moysan static bool stm32_sai_sub_readable_reg(struct device *dev, unsigned int reg)
1393e086edfSolivier moysan {
1403e086edfSolivier moysan switch (reg) {
1413e086edfSolivier moysan case STM_SAI_CR1_REGX:
1423e086edfSolivier moysan case STM_SAI_CR2_REGX:
1433e086edfSolivier moysan case STM_SAI_FRCR_REGX:
1443e086edfSolivier moysan case STM_SAI_SLOTR_REGX:
1453e086edfSolivier moysan case STM_SAI_IMR_REGX:
1463e086edfSolivier moysan case STM_SAI_SR_REGX:
1473e086edfSolivier moysan case STM_SAI_CLRFR_REGX:
1483e086edfSolivier moysan case STM_SAI_DR_REGX:
14903e78a24Solivier moysan case STM_SAI_PDMCR_REGX:
15003e78a24Solivier moysan case STM_SAI_PDMLY_REGX:
1513e086edfSolivier moysan return true;
1523e086edfSolivier moysan default:
1533e086edfSolivier moysan return false;
1543e086edfSolivier moysan }
1553e086edfSolivier moysan }
1563e086edfSolivier moysan
stm32_sai_sub_volatile_reg(struct device * dev,unsigned int reg)1573e086edfSolivier moysan static bool stm32_sai_sub_volatile_reg(struct device *dev, unsigned int reg)
1583e086edfSolivier moysan {
1593e086edfSolivier moysan switch (reg) {
1603e086edfSolivier moysan case STM_SAI_DR_REGX:
161cf881773SOlivier Moysan case STM_SAI_SR_REGX:
1623e086edfSolivier moysan return true;
1633e086edfSolivier moysan default:
1643e086edfSolivier moysan return false;
1653e086edfSolivier moysan }
1663e086edfSolivier moysan }
1673e086edfSolivier moysan
stm32_sai_sub_writeable_reg(struct device * dev,unsigned int reg)1683e086edfSolivier moysan static bool stm32_sai_sub_writeable_reg(struct device *dev, unsigned int reg)
1693e086edfSolivier moysan {
1703e086edfSolivier moysan switch (reg) {
1713e086edfSolivier moysan case STM_SAI_CR1_REGX:
1723e086edfSolivier moysan case STM_SAI_CR2_REGX:
1733e086edfSolivier moysan case STM_SAI_FRCR_REGX:
1743e086edfSolivier moysan case STM_SAI_SLOTR_REGX:
1753e086edfSolivier moysan case STM_SAI_IMR_REGX:
1763e086edfSolivier moysan case STM_SAI_CLRFR_REGX:
1773e086edfSolivier moysan case STM_SAI_DR_REGX:
17803e78a24Solivier moysan case STM_SAI_PDMCR_REGX:
17903e78a24Solivier moysan case STM_SAI_PDMLY_REGX:
1803e086edfSolivier moysan return true;
1813e086edfSolivier moysan default:
1823e086edfSolivier moysan return false;
1833e086edfSolivier moysan }
1843e086edfSolivier moysan }
1853e086edfSolivier moysan
stm32_sai_sub_reg_up(struct stm32_sai_sub_data * sai,unsigned int reg,unsigned int mask,unsigned int val)186a14bf98cSOlivier Moysan static int stm32_sai_sub_reg_up(struct stm32_sai_sub_data *sai,
187a14bf98cSOlivier Moysan unsigned int reg, unsigned int mask,
188a14bf98cSOlivier Moysan unsigned int val)
189a14bf98cSOlivier Moysan {
190a14bf98cSOlivier Moysan int ret;
191a14bf98cSOlivier Moysan
192a14bf98cSOlivier Moysan ret = clk_enable(sai->pdata->pclk);
193a14bf98cSOlivier Moysan if (ret < 0)
194a14bf98cSOlivier Moysan return ret;
195a14bf98cSOlivier Moysan
196a14bf98cSOlivier Moysan ret = regmap_update_bits(sai->regmap, reg, mask, val);
197a14bf98cSOlivier Moysan
198a14bf98cSOlivier Moysan clk_disable(sai->pdata->pclk);
199a14bf98cSOlivier Moysan
200a14bf98cSOlivier Moysan return ret;
201a14bf98cSOlivier Moysan }
202a14bf98cSOlivier Moysan
stm32_sai_sub_reg_wr(struct stm32_sai_sub_data * sai,unsigned int reg,unsigned int mask,unsigned int val)203a14bf98cSOlivier Moysan static int stm32_sai_sub_reg_wr(struct stm32_sai_sub_data *sai,
204a14bf98cSOlivier Moysan unsigned int reg, unsigned int mask,
205a14bf98cSOlivier Moysan unsigned int val)
206a14bf98cSOlivier Moysan {
207a14bf98cSOlivier Moysan int ret;
208a14bf98cSOlivier Moysan
209a14bf98cSOlivier Moysan ret = clk_enable(sai->pdata->pclk);
210a14bf98cSOlivier Moysan if (ret < 0)
211a14bf98cSOlivier Moysan return ret;
212a14bf98cSOlivier Moysan
213a14bf98cSOlivier Moysan ret = regmap_write_bits(sai->regmap, reg, mask, val);
214a14bf98cSOlivier Moysan
215a14bf98cSOlivier Moysan clk_disable(sai->pdata->pclk);
216a14bf98cSOlivier Moysan
217a14bf98cSOlivier Moysan return ret;
218a14bf98cSOlivier Moysan }
219a14bf98cSOlivier Moysan
stm32_sai_sub_reg_rd(struct stm32_sai_sub_data * sai,unsigned int reg,unsigned int * val)220a14bf98cSOlivier Moysan static int stm32_sai_sub_reg_rd(struct stm32_sai_sub_data *sai,
221a14bf98cSOlivier Moysan unsigned int reg, unsigned int *val)
222a14bf98cSOlivier Moysan {
223a14bf98cSOlivier Moysan int ret;
224a14bf98cSOlivier Moysan
225a14bf98cSOlivier Moysan ret = clk_enable(sai->pdata->pclk);
226a14bf98cSOlivier Moysan if (ret < 0)
227a14bf98cSOlivier Moysan return ret;
228a14bf98cSOlivier Moysan
229a14bf98cSOlivier Moysan ret = regmap_read(sai->regmap, reg, val);
230a14bf98cSOlivier Moysan
231a14bf98cSOlivier Moysan clk_disable(sai->pdata->pclk);
232a14bf98cSOlivier Moysan
233a14bf98cSOlivier Moysan return ret;
234a14bf98cSOlivier Moysan }
235a14bf98cSOlivier Moysan
23603e78a24Solivier moysan static const struct regmap_config stm32_sai_sub_regmap_config_f4 = {
2373e086edfSolivier moysan .reg_bits = 32,
2383e086edfSolivier moysan .reg_stride = 4,
2393e086edfSolivier moysan .val_bits = 32,
2403e086edfSolivier moysan .max_register = STM_SAI_DR_REGX,
2413e086edfSolivier moysan .readable_reg = stm32_sai_sub_readable_reg,
2423e086edfSolivier moysan .volatile_reg = stm32_sai_sub_volatile_reg,
2433e086edfSolivier moysan .writeable_reg = stm32_sai_sub_writeable_reg,
2443e086edfSolivier moysan .fast_io = true,
245cf881773SOlivier Moysan .cache_type = REGCACHE_FLAT,
2463e086edfSolivier moysan };
2473e086edfSolivier moysan
24803e78a24Solivier moysan static const struct regmap_config stm32_sai_sub_regmap_config_h7 = {
24903e78a24Solivier moysan .reg_bits = 32,
25003e78a24Solivier moysan .reg_stride = 4,
25103e78a24Solivier moysan .val_bits = 32,
25203e78a24Solivier moysan .max_register = STM_SAI_PDMLY_REGX,
25303e78a24Solivier moysan .readable_reg = stm32_sai_sub_readable_reg,
25403e78a24Solivier moysan .volatile_reg = stm32_sai_sub_volatile_reg,
25503e78a24Solivier moysan .writeable_reg = stm32_sai_sub_writeable_reg,
25603e78a24Solivier moysan .fast_io = true,
257cf881773SOlivier Moysan .cache_type = REGCACHE_FLAT,
25803e78a24Solivier moysan };
25903e78a24Solivier moysan
snd_pcm_iec958_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)260187e01d0Solivier moysan static int snd_pcm_iec958_info(struct snd_kcontrol *kcontrol,
261187e01d0Solivier moysan struct snd_ctl_elem_info *uinfo)
262187e01d0Solivier moysan {
263187e01d0Solivier moysan uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
264187e01d0Solivier moysan uinfo->count = 1;
265187e01d0Solivier moysan
266187e01d0Solivier moysan return 0;
267187e01d0Solivier moysan }
268187e01d0Solivier moysan
snd_pcm_iec958_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * uctl)269187e01d0Solivier moysan static int snd_pcm_iec958_get(struct snd_kcontrol *kcontrol,
270187e01d0Solivier moysan struct snd_ctl_elem_value *uctl)
271187e01d0Solivier moysan {
272187e01d0Solivier moysan struct stm32_sai_sub_data *sai = snd_kcontrol_chip(kcontrol);
273187e01d0Solivier moysan
274187e01d0Solivier moysan mutex_lock(&sai->ctrl_lock);
275187e01d0Solivier moysan memcpy(uctl->value.iec958.status, sai->iec958.status, 4);
276187e01d0Solivier moysan mutex_unlock(&sai->ctrl_lock);
277187e01d0Solivier moysan
278187e01d0Solivier moysan return 0;
279187e01d0Solivier moysan }
280187e01d0Solivier moysan
snd_pcm_iec958_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * uctl)281187e01d0Solivier moysan static int snd_pcm_iec958_put(struct snd_kcontrol *kcontrol,
282187e01d0Solivier moysan struct snd_ctl_elem_value *uctl)
283187e01d0Solivier moysan {
284187e01d0Solivier moysan struct stm32_sai_sub_data *sai = snd_kcontrol_chip(kcontrol);
285187e01d0Solivier moysan
286187e01d0Solivier moysan mutex_lock(&sai->ctrl_lock);
287187e01d0Solivier moysan memcpy(sai->iec958.status, uctl->value.iec958.status, 4);
288187e01d0Solivier moysan mutex_unlock(&sai->ctrl_lock);
289187e01d0Solivier moysan
290187e01d0Solivier moysan return 0;
291187e01d0Solivier moysan }
292187e01d0Solivier moysan
293187e01d0Solivier moysan static const struct snd_kcontrol_new iec958_ctls = {
294187e01d0Solivier moysan .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
295187e01d0Solivier moysan SNDRV_CTL_ELEM_ACCESS_VOLATILE),
296187e01d0Solivier moysan .iface = SNDRV_CTL_ELEM_IFACE_PCM,
297187e01d0Solivier moysan .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
298187e01d0Solivier moysan .info = snd_pcm_iec958_info,
299187e01d0Solivier moysan .get = snd_pcm_iec958_get,
300187e01d0Solivier moysan .put = snd_pcm_iec958_put,
301187e01d0Solivier moysan };
302187e01d0Solivier moysan
3038307b2afSOlivier Moysan struct stm32_sai_mclk_data {
3048307b2afSOlivier Moysan struct clk_hw hw;
3058307b2afSOlivier Moysan unsigned long freq;
3068307b2afSOlivier Moysan struct stm32_sai_sub_data *sai_data;
3078307b2afSOlivier Moysan };
3088307b2afSOlivier Moysan
3098307b2afSOlivier Moysan #define to_mclk_data(_hw) container_of(_hw, struct stm32_sai_mclk_data, hw)
3108307b2afSOlivier Moysan #define STM32_SAI_MAX_CLKS 1
3118307b2afSOlivier Moysan
stm32_sai_get_clk_div(struct stm32_sai_sub_data * sai,unsigned long input_rate,unsigned long output_rate)3128307b2afSOlivier Moysan static int stm32_sai_get_clk_div(struct stm32_sai_sub_data *sai,
3138307b2afSOlivier Moysan unsigned long input_rate,
3148307b2afSOlivier Moysan unsigned long output_rate)
3158307b2afSOlivier Moysan {
3161d9c95c1SOlivier Moysan int version = sai->pdata->conf.version;
3178307b2afSOlivier Moysan int div;
3188307b2afSOlivier Moysan
3198307b2afSOlivier Moysan div = DIV_ROUND_CLOSEST(input_rate, output_rate);
3208307b2afSOlivier Moysan if (div > SAI_XCR1_MCKDIV_MAX(version)) {
3218307b2afSOlivier Moysan dev_err(&sai->pdev->dev, "Divider %d out of range\n", div);
3228307b2afSOlivier Moysan return -EINVAL;
3238307b2afSOlivier Moysan }
3248307b2afSOlivier Moysan dev_dbg(&sai->pdev->dev, "SAI divider %d\n", div);
3258307b2afSOlivier Moysan
3268307b2afSOlivier Moysan if (input_rate % div)
3278307b2afSOlivier Moysan dev_dbg(&sai->pdev->dev,
3288307b2afSOlivier Moysan "Rate not accurate. requested (%ld), actual (%ld)\n",
3298307b2afSOlivier Moysan output_rate, input_rate / div);
3308307b2afSOlivier Moysan
3318307b2afSOlivier Moysan return div;
3328307b2afSOlivier Moysan }
3338307b2afSOlivier Moysan
stm32_sai_set_clk_div(struct stm32_sai_sub_data * sai,unsigned int div)3348307b2afSOlivier Moysan static int stm32_sai_set_clk_div(struct stm32_sai_sub_data *sai,
3358307b2afSOlivier Moysan unsigned int div)
3368307b2afSOlivier Moysan {
3371d9c95c1SOlivier Moysan int version = sai->pdata->conf.version;
3388307b2afSOlivier Moysan int ret, cr1, mask;
3398307b2afSOlivier Moysan
3408307b2afSOlivier Moysan if (div > SAI_XCR1_MCKDIV_MAX(version)) {
3418307b2afSOlivier Moysan dev_err(&sai->pdev->dev, "Divider %d out of range\n", div);
3428307b2afSOlivier Moysan return -EINVAL;
3438307b2afSOlivier Moysan }
3448307b2afSOlivier Moysan
3458307b2afSOlivier Moysan mask = SAI_XCR1_MCKDIV_MASK(SAI_XCR1_MCKDIV_WIDTH(version));
3468307b2afSOlivier Moysan cr1 = SAI_XCR1_MCKDIV_SET(div);
347a14bf98cSOlivier Moysan ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, mask, cr1);
3488307b2afSOlivier Moysan if (ret < 0)
3498307b2afSOlivier Moysan dev_err(&sai->pdev->dev, "Failed to update CR1 register\n");
3508307b2afSOlivier Moysan
3518307b2afSOlivier Moysan return ret;
3528307b2afSOlivier Moysan }
3538307b2afSOlivier Moysan
stm32_sai_set_parent_clock(struct stm32_sai_sub_data * sai,unsigned int rate)354e37c2deaSOlivier Moysan static int stm32_sai_set_parent_clock(struct stm32_sai_sub_data *sai,
355e37c2deaSOlivier Moysan unsigned int rate)
356e37c2deaSOlivier Moysan {
357e37c2deaSOlivier Moysan struct platform_device *pdev = sai->pdev;
358e37c2deaSOlivier Moysan struct clk *parent_clk = sai->pdata->clk_x8k;
359e37c2deaSOlivier Moysan int ret;
360e37c2deaSOlivier Moysan
361e37c2deaSOlivier Moysan if (!(rate % SAI_RATE_11K))
362e37c2deaSOlivier Moysan parent_clk = sai->pdata->clk_x11k;
363e37c2deaSOlivier Moysan
364e37c2deaSOlivier Moysan ret = clk_set_parent(sai->sai_ck, parent_clk);
365e37c2deaSOlivier Moysan if (ret)
366e37c2deaSOlivier Moysan dev_err(&pdev->dev, " Error %d setting sai_ck parent clock. %s",
367e37c2deaSOlivier Moysan ret, ret == -EBUSY ?
368e37c2deaSOlivier Moysan "Active stream rates conflict\n" : "\n");
369e37c2deaSOlivier Moysan
370e37c2deaSOlivier Moysan return ret;
371e37c2deaSOlivier Moysan }
372e37c2deaSOlivier Moysan
stm32_sai_mclk_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)3738307b2afSOlivier Moysan static long stm32_sai_mclk_round_rate(struct clk_hw *hw, unsigned long rate,
3748307b2afSOlivier Moysan unsigned long *prate)
3758307b2afSOlivier Moysan {
3768307b2afSOlivier Moysan struct stm32_sai_mclk_data *mclk = to_mclk_data(hw);
3778307b2afSOlivier Moysan struct stm32_sai_sub_data *sai = mclk->sai_data;
3788307b2afSOlivier Moysan int div;
3798307b2afSOlivier Moysan
3808307b2afSOlivier Moysan div = stm32_sai_get_clk_div(sai, *prate, rate);
3818307b2afSOlivier Moysan if (div < 0)
3828307b2afSOlivier Moysan return div;
3838307b2afSOlivier Moysan
3848307b2afSOlivier Moysan mclk->freq = *prate / div;
3858307b2afSOlivier Moysan
3868307b2afSOlivier Moysan return mclk->freq;
3878307b2afSOlivier Moysan }
3888307b2afSOlivier Moysan
stm32_sai_mclk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)3898307b2afSOlivier Moysan static unsigned long stm32_sai_mclk_recalc_rate(struct clk_hw *hw,
3908307b2afSOlivier Moysan unsigned long parent_rate)
3918307b2afSOlivier Moysan {
3928307b2afSOlivier Moysan struct stm32_sai_mclk_data *mclk = to_mclk_data(hw);
3938307b2afSOlivier Moysan
3948307b2afSOlivier Moysan return mclk->freq;
3958307b2afSOlivier Moysan }
3968307b2afSOlivier Moysan
stm32_sai_mclk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)3978307b2afSOlivier Moysan static int stm32_sai_mclk_set_rate(struct clk_hw *hw, unsigned long rate,
3988307b2afSOlivier Moysan unsigned long parent_rate)
3998307b2afSOlivier Moysan {
4008307b2afSOlivier Moysan struct stm32_sai_mclk_data *mclk = to_mclk_data(hw);
4018307b2afSOlivier Moysan struct stm32_sai_sub_data *sai = mclk->sai_data;
4026b27e277SColin Ian King int div, ret;
4038307b2afSOlivier Moysan
4048307b2afSOlivier Moysan div = stm32_sai_get_clk_div(sai, parent_rate, rate);
4058307b2afSOlivier Moysan if (div < 0)
4068307b2afSOlivier Moysan return div;
4078307b2afSOlivier Moysan
4088307b2afSOlivier Moysan ret = stm32_sai_set_clk_div(sai, div);
4098307b2afSOlivier Moysan if (ret)
4108307b2afSOlivier Moysan return ret;
4118307b2afSOlivier Moysan
4128307b2afSOlivier Moysan mclk->freq = rate;
4138307b2afSOlivier Moysan
4148307b2afSOlivier Moysan return 0;
4158307b2afSOlivier Moysan }
4168307b2afSOlivier Moysan
stm32_sai_mclk_enable(struct clk_hw * hw)4178307b2afSOlivier Moysan static int stm32_sai_mclk_enable(struct clk_hw *hw)
4188307b2afSOlivier Moysan {
4198307b2afSOlivier Moysan struct stm32_sai_mclk_data *mclk = to_mclk_data(hw);
4208307b2afSOlivier Moysan struct stm32_sai_sub_data *sai = mclk->sai_data;
4218307b2afSOlivier Moysan
4228307b2afSOlivier Moysan dev_dbg(&sai->pdev->dev, "Enable master clock\n");
4238307b2afSOlivier Moysan
424a14bf98cSOlivier Moysan return stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX,
4258307b2afSOlivier Moysan SAI_XCR1_MCKEN, SAI_XCR1_MCKEN);
4268307b2afSOlivier Moysan }
4278307b2afSOlivier Moysan
stm32_sai_mclk_disable(struct clk_hw * hw)4288307b2afSOlivier Moysan static void stm32_sai_mclk_disable(struct clk_hw *hw)
4298307b2afSOlivier Moysan {
4308307b2afSOlivier Moysan struct stm32_sai_mclk_data *mclk = to_mclk_data(hw);
4318307b2afSOlivier Moysan struct stm32_sai_sub_data *sai = mclk->sai_data;
4328307b2afSOlivier Moysan
4338307b2afSOlivier Moysan dev_dbg(&sai->pdev->dev, "Disable master clock\n");
4348307b2afSOlivier Moysan
435a14bf98cSOlivier Moysan stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, SAI_XCR1_MCKEN, 0);
4368307b2afSOlivier Moysan }
4378307b2afSOlivier Moysan
4388307b2afSOlivier Moysan static const struct clk_ops mclk_ops = {
4398307b2afSOlivier Moysan .enable = stm32_sai_mclk_enable,
4408307b2afSOlivier Moysan .disable = stm32_sai_mclk_disable,
4418307b2afSOlivier Moysan .recalc_rate = stm32_sai_mclk_recalc_rate,
4428307b2afSOlivier Moysan .round_rate = stm32_sai_mclk_round_rate,
4438307b2afSOlivier Moysan .set_rate = stm32_sai_mclk_set_rate,
4448307b2afSOlivier Moysan };
4458307b2afSOlivier Moysan
stm32_sai_add_mclk_provider(struct stm32_sai_sub_data * sai)4468307b2afSOlivier Moysan static int stm32_sai_add_mclk_provider(struct stm32_sai_sub_data *sai)
4478307b2afSOlivier Moysan {
4488307b2afSOlivier Moysan struct clk_hw *hw;
4498307b2afSOlivier Moysan struct stm32_sai_mclk_data *mclk;
4508307b2afSOlivier Moysan struct device *dev = &sai->pdev->dev;
4518307b2afSOlivier Moysan const char *pname = __clk_get_name(sai->sai_ck);
4528307b2afSOlivier Moysan char *mclk_name, *p, *s = (char *)pname;
4538307b2afSOlivier Moysan int ret, i = 0;
4548307b2afSOlivier Moysan
455496fa3baSWei Yongjun mclk = devm_kzalloc(dev, sizeof(*mclk), GFP_KERNEL);
4568307b2afSOlivier Moysan if (!mclk)
4578307b2afSOlivier Moysan return -ENOMEM;
4588307b2afSOlivier Moysan
4598307b2afSOlivier Moysan mclk_name = devm_kcalloc(dev, sizeof(char),
4608307b2afSOlivier Moysan SAI_MCLK_NAME_LEN, GFP_KERNEL);
4618307b2afSOlivier Moysan if (!mclk_name)
4628307b2afSOlivier Moysan return -ENOMEM;
4638307b2afSOlivier Moysan
4648307b2afSOlivier Moysan /*
4658307b2afSOlivier Moysan * Forge mclk clock name from parent clock name and suffix.
4668307b2afSOlivier Moysan * String after "_" char is stripped in parent name.
4678307b2afSOlivier Moysan */
4688307b2afSOlivier Moysan p = mclk_name;
4696be0f96dSOlivier Moysan while (*s && *s != '_' && (i < (SAI_MCLK_NAME_LEN - 7))) {
4708307b2afSOlivier Moysan *p++ = *s++;
4718307b2afSOlivier Moysan i++;
4728307b2afSOlivier Moysan }
4736be0f96dSOlivier Moysan STM_SAI_IS_SUB_A(sai) ? strcat(p, "a_mclk") : strcat(p, "b_mclk");
4748307b2afSOlivier Moysan
4758307b2afSOlivier Moysan mclk->hw.init = CLK_HW_INIT(mclk_name, pname, &mclk_ops, 0);
4768307b2afSOlivier Moysan mclk->sai_data = sai;
4778307b2afSOlivier Moysan hw = &mclk->hw;
4788307b2afSOlivier Moysan
4798307b2afSOlivier Moysan dev_dbg(dev, "Register master clock %s\n", mclk_name);
4808307b2afSOlivier Moysan ret = devm_clk_hw_register(&sai->pdev->dev, hw);
4818307b2afSOlivier Moysan if (ret) {
4828307b2afSOlivier Moysan dev_err(dev, "mclk register returned %d\n", ret);
4838307b2afSOlivier Moysan return ret;
4848307b2afSOlivier Moysan }
485a0695853SJerome Brunet sai->sai_mclk = hw->clk;
4868307b2afSOlivier Moysan
4878307b2afSOlivier Moysan /* register mclk provider */
4888307b2afSOlivier Moysan return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
4898307b2afSOlivier Moysan }
4908307b2afSOlivier Moysan
stm32_sai_isr(int irq,void * devid)4913e086edfSolivier moysan static irqreturn_t stm32_sai_isr(int irq, void *devid)
4923e086edfSolivier moysan {
4933e086edfSolivier moysan struct stm32_sai_sub_data *sai = (struct stm32_sai_sub_data *)devid;
4943e086edfSolivier moysan struct platform_device *pdev = sai->pdev;
4953e086edfSolivier moysan unsigned int sr, imr, flags;
4963e086edfSolivier moysan snd_pcm_state_t status = SNDRV_PCM_STATE_RUNNING;
4973e086edfSolivier moysan
498a14bf98cSOlivier Moysan stm32_sai_sub_reg_rd(sai, STM_SAI_IMR_REGX, &imr);
499a14bf98cSOlivier Moysan stm32_sai_sub_reg_rd(sai, STM_SAI_SR_REGX, &sr);
5003e086edfSolivier moysan
5013e086edfSolivier moysan flags = sr & imr;
5023e086edfSolivier moysan if (!flags)
5033e086edfSolivier moysan return IRQ_NONE;
5043e086edfSolivier moysan
505a14bf98cSOlivier Moysan stm32_sai_sub_reg_wr(sai, STM_SAI_CLRFR_REGX, SAI_XCLRFR_MASK,
5063e086edfSolivier moysan SAI_XCLRFR_MASK);
5073e086edfSolivier moysan
508d807cdfbSOlivier Moysan if (!sai->substream) {
509d807cdfbSOlivier Moysan dev_err(&pdev->dev, "Device stopped. Spurious IRQ 0x%x\n", sr);
510d807cdfbSOlivier Moysan return IRQ_NONE;
511d807cdfbSOlivier Moysan }
512d807cdfbSOlivier Moysan
5133e086edfSolivier moysan if (flags & SAI_XIMR_OVRUDRIE) {
514602fdadcSolivier moysan dev_err(&pdev->dev, "IRQ %s\n",
5153e086edfSolivier moysan STM_SAI_IS_PLAYBACK(sai) ? "underrun" : "overrun");
5163e086edfSolivier moysan status = SNDRV_PCM_STATE_XRUN;
5173e086edfSolivier moysan }
5183e086edfSolivier moysan
5193e086edfSolivier moysan if (flags & SAI_XIMR_MUTEDETIE)
520602fdadcSolivier moysan dev_dbg(&pdev->dev, "IRQ mute detected\n");
5213e086edfSolivier moysan
5223e086edfSolivier moysan if (flags & SAI_XIMR_WCKCFGIE) {
523602fdadcSolivier moysan dev_err(&pdev->dev, "IRQ wrong clock configuration\n");
5243e086edfSolivier moysan status = SNDRV_PCM_STATE_DISCONNECTED;
5253e086edfSolivier moysan }
5263e086edfSolivier moysan
5273e086edfSolivier moysan if (flags & SAI_XIMR_CNRDYIE)
528602fdadcSolivier moysan dev_err(&pdev->dev, "IRQ Codec not ready\n");
5293e086edfSolivier moysan
5303e086edfSolivier moysan if (flags & SAI_XIMR_AFSDETIE) {
531602fdadcSolivier moysan dev_err(&pdev->dev, "IRQ Anticipated frame synchro\n");
5323e086edfSolivier moysan status = SNDRV_PCM_STATE_XRUN;
5333e086edfSolivier moysan }
5343e086edfSolivier moysan
5353e086edfSolivier moysan if (flags & SAI_XIMR_LFSDETIE) {
536602fdadcSolivier moysan dev_err(&pdev->dev, "IRQ Late frame synchro\n");
5373e086edfSolivier moysan status = SNDRV_PCM_STATE_XRUN;
5383e086edfSolivier moysan }
5393e086edfSolivier moysan
54026f98e82SOlivier Moysan spin_lock(&sai->irq_lock);
54126f98e82SOlivier Moysan if (status != SNDRV_PCM_STATE_RUNNING && sai->substream)
542b1625fbbSTakashi Iwai snd_pcm_stop_xrun(sai->substream);
54326f98e82SOlivier Moysan spin_unlock(&sai->irq_lock);
5443e086edfSolivier moysan
5453e086edfSolivier moysan return IRQ_HANDLED;
5463e086edfSolivier moysan }
5473e086edfSolivier moysan
stm32_sai_set_sysclk(struct snd_soc_dai * cpu_dai,int clk_id,unsigned int freq,int dir)5483e086edfSolivier moysan static int stm32_sai_set_sysclk(struct snd_soc_dai *cpu_dai,
5493e086edfSolivier moysan int clk_id, unsigned int freq, int dir)
5503e086edfSolivier moysan {
5513e086edfSolivier moysan struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
552701a6ec3Solivier moysan int ret;
5533e086edfSolivier moysan
554e37c2deaSOlivier Moysan if (dir == SND_SOC_CLOCK_OUT && sai->sai_mclk) {
555a14bf98cSOlivier Moysan ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX,
556701a6ec3Solivier moysan SAI_XCR1_NODIV,
5579b7a7f92SOlivier Moysan freq ? 0 : SAI_XCR1_NODIV);
558701a6ec3Solivier moysan if (ret < 0)
559701a6ec3Solivier moysan return ret;
560701a6ec3Solivier moysan
5619b7a7f92SOlivier Moysan /* Assume shutdown if requested frequency is 0Hz */
5629b7a7f92SOlivier Moysan if (!freq) {
5639b7a7f92SOlivier Moysan /* Release mclk rate only if rate was actually set */
5649b7a7f92SOlivier Moysan if (sai->mclk_rate) {
5659b7a7f92SOlivier Moysan clk_rate_exclusive_put(sai->sai_mclk);
5669b7a7f92SOlivier Moysan sai->mclk_rate = 0;
5679b7a7f92SOlivier Moysan }
5689b7a7f92SOlivier Moysan return 0;
5699b7a7f92SOlivier Moysan }
5709b7a7f92SOlivier Moysan
571e37c2deaSOlivier Moysan /* If master clock is used, set parent clock now */
572e37c2deaSOlivier Moysan ret = stm32_sai_set_parent_clock(sai, freq);
573e37c2deaSOlivier Moysan if (ret)
574e37c2deaSOlivier Moysan return ret;
5758307b2afSOlivier Moysan
576e37c2deaSOlivier Moysan ret = clk_set_rate_exclusive(sai->sai_mclk, freq);
5778307b2afSOlivier Moysan if (ret) {
5788307b2afSOlivier Moysan dev_err(cpu_dai->dev,
579e37c2deaSOlivier Moysan ret == -EBUSY ?
580e37c2deaSOlivier Moysan "Active streams have incompatible rates" :
5818307b2afSOlivier Moysan "Could not set mclk rate\n");
5828307b2afSOlivier Moysan return ret;
5838307b2afSOlivier Moysan }
584e37c2deaSOlivier Moysan
585e37c2deaSOlivier Moysan dev_dbg(cpu_dai->dev, "SAI MCLK frequency is %uHz\n", freq);
586e37c2deaSOlivier Moysan sai->mclk_rate = freq;
5873e086edfSolivier moysan }
5883e086edfSolivier moysan
5893e086edfSolivier moysan return 0;
5903e086edfSolivier moysan }
5913e086edfSolivier moysan
stm32_sai_set_dai_tdm_slot(struct snd_soc_dai * cpu_dai,u32 tx_mask,u32 rx_mask,int slots,int slot_width)5923e086edfSolivier moysan static int stm32_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
5933e086edfSolivier moysan u32 rx_mask, int slots, int slot_width)
5943e086edfSolivier moysan {
5953e086edfSolivier moysan struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
5963e086edfSolivier moysan int slotr, slotr_mask, slot_size;
5973e086edfSolivier moysan
5986eb17d70SOlivier Moysan if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
5996eb17d70SOlivier Moysan dev_warn(cpu_dai->dev, "Slot setting relevant only for TDM\n");
6006eb17d70SOlivier Moysan return 0;
6016eb17d70SOlivier Moysan }
6026eb17d70SOlivier Moysan
603602fdadcSolivier moysan dev_dbg(cpu_dai->dev, "Masks tx/rx:%#x/%#x, slots:%d, width:%d\n",
6043e086edfSolivier moysan tx_mask, rx_mask, slots, slot_width);
6053e086edfSolivier moysan
6063e086edfSolivier moysan switch (slot_width) {
6073e086edfSolivier moysan case 16:
6083e086edfSolivier moysan slot_size = SAI_SLOT_SIZE_16;
6093e086edfSolivier moysan break;
6103e086edfSolivier moysan case 32:
6113e086edfSolivier moysan slot_size = SAI_SLOT_SIZE_32;
6123e086edfSolivier moysan break;
6133e086edfSolivier moysan default:
6143e086edfSolivier moysan slot_size = SAI_SLOT_SIZE_AUTO;
6153e086edfSolivier moysan break;
6163e086edfSolivier moysan }
6173e086edfSolivier moysan
6183e086edfSolivier moysan slotr = SAI_XSLOTR_SLOTSZ_SET(slot_size) |
6193e086edfSolivier moysan SAI_XSLOTR_NBSLOT_SET(slots - 1);
6203e086edfSolivier moysan slotr_mask = SAI_XSLOTR_SLOTSZ_MASK | SAI_XSLOTR_NBSLOT_MASK;
6213e086edfSolivier moysan
6223e086edfSolivier moysan /* tx/rx mask set in machine init, if slot number defined in DT */
6233e086edfSolivier moysan if (STM_SAI_IS_PLAYBACK(sai)) {
6243e086edfSolivier moysan sai->slot_mask = tx_mask;
6253e086edfSolivier moysan slotr |= SAI_XSLOTR_SLOTEN_SET(tx_mask);
6263e086edfSolivier moysan }
6273e086edfSolivier moysan
6283e086edfSolivier moysan if (STM_SAI_IS_CAPTURE(sai)) {
6293e086edfSolivier moysan sai->slot_mask = rx_mask;
6303e086edfSolivier moysan slotr |= SAI_XSLOTR_SLOTEN_SET(rx_mask);
6313e086edfSolivier moysan }
6323e086edfSolivier moysan
6333e086edfSolivier moysan slotr_mask |= SAI_XSLOTR_SLOTEN_MASK;
6343e086edfSolivier moysan
635a14bf98cSOlivier Moysan stm32_sai_sub_reg_up(sai, STM_SAI_SLOTR_REGX, slotr_mask, slotr);
6363e086edfSolivier moysan
6373e086edfSolivier moysan sai->slot_width = slot_width;
6383e086edfSolivier moysan sai->slots = slots;
6393e086edfSolivier moysan
6403e086edfSolivier moysan return 0;
6413e086edfSolivier moysan }
6423e086edfSolivier moysan
stm32_sai_set_dai_fmt(struct snd_soc_dai * cpu_dai,unsigned int fmt)6433e086edfSolivier moysan static int stm32_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
6443e086edfSolivier moysan {
6453e086edfSolivier moysan struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
64661fb4ff7SOlivier Moysan int cr1, frcr = 0;
64761fb4ff7SOlivier Moysan int cr1_mask, frcr_mask = 0;
6483e086edfSolivier moysan int ret;
6493e086edfSolivier moysan
6503e086edfSolivier moysan dev_dbg(cpu_dai->dev, "fmt %x\n", fmt);
6513e086edfSolivier moysan
6526eb17d70SOlivier Moysan /* Do not generate master by default */
6536eb17d70SOlivier Moysan cr1 = SAI_XCR1_NODIV;
6546eb17d70SOlivier Moysan cr1_mask = SAI_XCR1_NODIV;
6556eb17d70SOlivier Moysan
6566eb17d70SOlivier Moysan cr1_mask |= SAI_XCR1_PRTCFG_MASK;
6576eb17d70SOlivier Moysan if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
6586eb17d70SOlivier Moysan cr1 |= SAI_XCR1_PRTCFG_SET(SAI_SPDIF_PROTOCOL);
6596eb17d70SOlivier Moysan goto conf_update;
6606eb17d70SOlivier Moysan }
6616eb17d70SOlivier Moysan
6626eb17d70SOlivier Moysan cr1 |= SAI_XCR1_PRTCFG_SET(SAI_FREE_PROTOCOL);
66361fb4ff7SOlivier Moysan
6643e086edfSolivier moysan switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
6653e086edfSolivier moysan /* SCK active high for all protocols */
6663e086edfSolivier moysan case SND_SOC_DAIFMT_I2S:
6673e086edfSolivier moysan cr1 |= SAI_XCR1_CKSTR;
6683e086edfSolivier moysan frcr |= SAI_XFRCR_FSOFF | SAI_XFRCR_FSDEF;
6693e086edfSolivier moysan break;
6703e086edfSolivier moysan /* Left justified */
6713e086edfSolivier moysan case SND_SOC_DAIFMT_MSB:
6723e086edfSolivier moysan frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSDEF;
6733e086edfSolivier moysan break;
6743e086edfSolivier moysan /* Right justified */
6753e086edfSolivier moysan case SND_SOC_DAIFMT_LSB:
6763e086edfSolivier moysan frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSDEF;
6773e086edfSolivier moysan break;
6783e086edfSolivier moysan case SND_SOC_DAIFMT_DSP_A:
6793e086edfSolivier moysan frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSOFF;
6803e086edfSolivier moysan break;
6813e086edfSolivier moysan case SND_SOC_DAIFMT_DSP_B:
6823e086edfSolivier moysan frcr |= SAI_XFRCR_FSPOL;
6833e086edfSolivier moysan break;
6843e086edfSolivier moysan default:
6853e086edfSolivier moysan dev_err(cpu_dai->dev, "Unsupported protocol %#x\n",
6863e086edfSolivier moysan fmt & SND_SOC_DAIFMT_FORMAT_MASK);
6873e086edfSolivier moysan return -EINVAL;
6883e086edfSolivier moysan }
6893e086edfSolivier moysan
69061fb4ff7SOlivier Moysan cr1_mask |= SAI_XCR1_CKSTR;
6913e086edfSolivier moysan frcr_mask |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSOFF |
6923e086edfSolivier moysan SAI_XFRCR_FSDEF;
6933e086edfSolivier moysan
6943e086edfSolivier moysan /* DAI clock strobing. Invert setting previously set */
6953e086edfSolivier moysan switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
6963e086edfSolivier moysan case SND_SOC_DAIFMT_NB_NF:
6973e086edfSolivier moysan break;
6983e086edfSolivier moysan case SND_SOC_DAIFMT_IB_NF:
6993e086edfSolivier moysan cr1 ^= SAI_XCR1_CKSTR;
7003e086edfSolivier moysan break;
7013e086edfSolivier moysan case SND_SOC_DAIFMT_NB_IF:
7023e086edfSolivier moysan frcr ^= SAI_XFRCR_FSPOL;
7033e086edfSolivier moysan break;
7043e086edfSolivier moysan case SND_SOC_DAIFMT_IB_IF:
7053e086edfSolivier moysan /* Invert fs & sck */
7063e086edfSolivier moysan cr1 ^= SAI_XCR1_CKSTR;
7073e086edfSolivier moysan frcr ^= SAI_XFRCR_FSPOL;
7083e086edfSolivier moysan break;
7093e086edfSolivier moysan default:
7103e086edfSolivier moysan dev_err(cpu_dai->dev, "Unsupported strobing %#x\n",
7113e086edfSolivier moysan fmt & SND_SOC_DAIFMT_INV_MASK);
7123e086edfSolivier moysan return -EINVAL;
7133e086edfSolivier moysan }
7143e086edfSolivier moysan cr1_mask |= SAI_XCR1_CKSTR;
7153e086edfSolivier moysan frcr_mask |= SAI_XFRCR_FSPOL;
7163e086edfSolivier moysan
717a14bf98cSOlivier Moysan stm32_sai_sub_reg_up(sai, STM_SAI_FRCR_REGX, frcr_mask, frcr);
7183e086edfSolivier moysan
7193e086edfSolivier moysan /* DAI clock master masks */
7200092dac9SCharles Keepax switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
7210092dac9SCharles Keepax case SND_SOC_DAIFMT_BC_FC:
7223e086edfSolivier moysan /* codec is master */
7233e086edfSolivier moysan cr1 |= SAI_XCR1_SLAVE;
7243e086edfSolivier moysan sai->master = false;
7253e086edfSolivier moysan break;
7260092dac9SCharles Keepax case SND_SOC_DAIFMT_BP_FP:
7273e086edfSolivier moysan sai->master = true;
7283e086edfSolivier moysan break;
7293e086edfSolivier moysan default:
7303e086edfSolivier moysan dev_err(cpu_dai->dev, "Unsupported mode %#x\n",
7310092dac9SCharles Keepax fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK);
7323e086edfSolivier moysan return -EINVAL;
7333e086edfSolivier moysan }
7345914d285SOlivier Moysan
7355914d285SOlivier Moysan /* Set slave mode if sub-block is synchronized with another SAI */
7365914d285SOlivier Moysan if (sai->sync) {
7375914d285SOlivier Moysan dev_dbg(cpu_dai->dev, "Synchronized SAI configured as slave\n");
7385914d285SOlivier Moysan cr1 |= SAI_XCR1_SLAVE;
7395914d285SOlivier Moysan sai->master = false;
7405914d285SOlivier Moysan }
7415914d285SOlivier Moysan
7423e086edfSolivier moysan cr1_mask |= SAI_XCR1_SLAVE;
7433e086edfSolivier moysan
7446eb17d70SOlivier Moysan conf_update:
745a14bf98cSOlivier Moysan ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, cr1_mask, cr1);
7463e086edfSolivier moysan if (ret < 0) {
7473e086edfSolivier moysan dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
7483e086edfSolivier moysan return ret;
7493e086edfSolivier moysan }
7503e086edfSolivier moysan
7513e086edfSolivier moysan sai->fmt = fmt;
7523e086edfSolivier moysan
7533e086edfSolivier moysan return 0;
7543e086edfSolivier moysan }
7553e086edfSolivier moysan
stm32_sai_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * cpu_dai)7563e086edfSolivier moysan static int stm32_sai_startup(struct snd_pcm_substream *substream,
7573e086edfSolivier moysan struct snd_soc_dai *cpu_dai)
7583e086edfSolivier moysan {
7593e086edfSolivier moysan struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
7603e086edfSolivier moysan int imr, cr2, ret;
76126f98e82SOlivier Moysan unsigned long flags;
7623e086edfSolivier moysan
76326f98e82SOlivier Moysan spin_lock_irqsave(&sai->irq_lock, flags);
7643e086edfSolivier moysan sai->substream = substream;
76526f98e82SOlivier Moysan spin_unlock_irqrestore(&sai->irq_lock, flags);
7663e086edfSolivier moysan
767b8468192SOlivier Moysan if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
768b8468192SOlivier Moysan snd_pcm_hw_constraint_mask64(substream->runtime,
769b8468192SOlivier Moysan SNDRV_PCM_HW_PARAM_FORMAT,
770b8468192SOlivier Moysan SNDRV_PCM_FMTBIT_S32_LE);
771b8468192SOlivier Moysan snd_pcm_hw_constraint_single(substream->runtime,
772b8468192SOlivier Moysan SNDRV_PCM_HW_PARAM_CHANNELS, 2);
773b8468192SOlivier Moysan }
774b8468192SOlivier Moysan
7753e086edfSolivier moysan ret = clk_prepare_enable(sai->sai_ck);
7763e086edfSolivier moysan if (ret < 0) {
777602fdadcSolivier moysan dev_err(cpu_dai->dev, "Failed to enable clock: %d\n", ret);
7783e086edfSolivier moysan return ret;
7793e086edfSolivier moysan }
7803e086edfSolivier moysan
7813e086edfSolivier moysan /* Enable ITs */
782a14bf98cSOlivier Moysan stm32_sai_sub_reg_wr(sai, STM_SAI_CLRFR_REGX,
7833e086edfSolivier moysan SAI_XCLRFR_MASK, SAI_XCLRFR_MASK);
7843e086edfSolivier moysan
7853e086edfSolivier moysan imr = SAI_XIMR_OVRUDRIE;
7863e086edfSolivier moysan if (STM_SAI_IS_CAPTURE(sai)) {
787a14bf98cSOlivier Moysan stm32_sai_sub_reg_rd(sai, STM_SAI_CR2_REGX, &cr2);
7883e086edfSolivier moysan if (cr2 & SAI_XCR2_MUTECNT_MASK)
7893e086edfSolivier moysan imr |= SAI_XIMR_MUTEDETIE;
7903e086edfSolivier moysan }
7913e086edfSolivier moysan
7923e086edfSolivier moysan if (sai->master)
7933e086edfSolivier moysan imr |= SAI_XIMR_WCKCFGIE;
7943e086edfSolivier moysan else
7953e086edfSolivier moysan imr |= SAI_XIMR_AFSDETIE | SAI_XIMR_LFSDETIE;
7963e086edfSolivier moysan
797a14bf98cSOlivier Moysan stm32_sai_sub_reg_up(sai, STM_SAI_IMR_REGX,
7983e086edfSolivier moysan SAI_XIMR_MASK, imr);
7993e086edfSolivier moysan
8003e086edfSolivier moysan return 0;
8013e086edfSolivier moysan }
8023e086edfSolivier moysan
stm32_sai_set_config(struct snd_soc_dai * cpu_dai,struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params)8033e086edfSolivier moysan static int stm32_sai_set_config(struct snd_soc_dai *cpu_dai,
8043e086edfSolivier moysan struct snd_pcm_substream *substream,
8053e086edfSolivier moysan struct snd_pcm_hw_params *params)
8063e086edfSolivier moysan {
8073e086edfSolivier moysan struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
8083e086edfSolivier moysan int cr1, cr1_mask, ret;
8093e086edfSolivier moysan
810a4529d2bSOlivier Moysan /*
811a4529d2bSOlivier Moysan * DMA bursts increment is set to 4 words.
812a4529d2bSOlivier Moysan * SAI fifo threshold is set to half fifo, to keep enough space
813a4529d2bSOlivier Moysan * for DMA incoming bursts.
814a4529d2bSOlivier Moysan */
815a14bf98cSOlivier Moysan stm32_sai_sub_reg_wr(sai, STM_SAI_CR2_REGX,
8163e086edfSolivier moysan SAI_XCR2_FFLUSH | SAI_XCR2_FTH_MASK,
817a4529d2bSOlivier Moysan SAI_XCR2_FFLUSH |
818a4529d2bSOlivier Moysan SAI_XCR2_FTH_SET(STM_SAI_FIFO_TH_HALF));
8193e086edfSolivier moysan
8206eb17d70SOlivier Moysan /* DS bits in CR1 not set for SPDIF (size forced to 24 bits).*/
8216eb17d70SOlivier Moysan if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
8226eb17d70SOlivier Moysan sai->spdif_frm_cnt = 0;
8236eb17d70SOlivier Moysan return 0;
8246eb17d70SOlivier Moysan }
8256eb17d70SOlivier Moysan
8263e086edfSolivier moysan /* Mode, data format and channel config */
82761fb4ff7SOlivier Moysan cr1_mask = SAI_XCR1_DS_MASK;
8283e086edfSolivier moysan switch (params_format(params)) {
8293e086edfSolivier moysan case SNDRV_PCM_FORMAT_S8:
8307e751e37Solivier moysan cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_8);
8313e086edfSolivier moysan break;
8323e086edfSolivier moysan case SNDRV_PCM_FORMAT_S16_LE:
8337e751e37Solivier moysan cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_16);
8343e086edfSolivier moysan break;
8353e086edfSolivier moysan case SNDRV_PCM_FORMAT_S32_LE:
8367e751e37Solivier moysan cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_32);
8373e086edfSolivier moysan break;
8383e086edfSolivier moysan default:
8399de300abSSebastian Fricke dev_err(cpu_dai->dev, "Data format not supported\n");
8403e086edfSolivier moysan return -EINVAL;
8413e086edfSolivier moysan }
8423e086edfSolivier moysan
8433e086edfSolivier moysan cr1_mask |= SAI_XCR1_MONO;
8443e086edfSolivier moysan if ((sai->slots == 2) && (params_channels(params) == 1))
8453e086edfSolivier moysan cr1 |= SAI_XCR1_MONO;
8463e086edfSolivier moysan
847a14bf98cSOlivier Moysan ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, cr1_mask, cr1);
8483e086edfSolivier moysan if (ret < 0) {
8493e086edfSolivier moysan dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
8503e086edfSolivier moysan return ret;
8513e086edfSolivier moysan }
8523e086edfSolivier moysan
8533e086edfSolivier moysan return 0;
8543e086edfSolivier moysan }
8553e086edfSolivier moysan
stm32_sai_set_slots(struct snd_soc_dai * cpu_dai)8563e086edfSolivier moysan static int stm32_sai_set_slots(struct snd_soc_dai *cpu_dai)
8573e086edfSolivier moysan {
8583e086edfSolivier moysan struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
8593e086edfSolivier moysan int slotr, slot_sz;
8603e086edfSolivier moysan
861a14bf98cSOlivier Moysan stm32_sai_sub_reg_rd(sai, STM_SAI_SLOTR_REGX, &slotr);
8623e086edfSolivier moysan
8633e086edfSolivier moysan /*
8643e086edfSolivier moysan * If SLOTSZ is set to auto in SLOTR, align slot width on data size
8653e086edfSolivier moysan * By default slot width = data size, if not forced from DT
8663e086edfSolivier moysan */
8673e086edfSolivier moysan slot_sz = slotr & SAI_XSLOTR_SLOTSZ_MASK;
8683e086edfSolivier moysan if (slot_sz == SAI_XSLOTR_SLOTSZ_SET(SAI_SLOT_SIZE_AUTO))
8693e086edfSolivier moysan sai->slot_width = sai->data_size;
8703e086edfSolivier moysan
8713e086edfSolivier moysan if (sai->slot_width < sai->data_size) {
8723e086edfSolivier moysan dev_err(cpu_dai->dev,
8733e086edfSolivier moysan "Data size %d larger than slot width\n",
8743e086edfSolivier moysan sai->data_size);
8753e086edfSolivier moysan return -EINVAL;
8763e086edfSolivier moysan }
8773e086edfSolivier moysan
8783e086edfSolivier moysan /* Slot number is set to 2, if not specified in DT */
8793e086edfSolivier moysan if (!sai->slots)
8803e086edfSolivier moysan sai->slots = 2;
8813e086edfSolivier moysan
8823e086edfSolivier moysan /* The number of slots in the audio frame is equal to NBSLOT[3:0] + 1*/
883a14bf98cSOlivier Moysan stm32_sai_sub_reg_up(sai, STM_SAI_SLOTR_REGX,
8843e086edfSolivier moysan SAI_XSLOTR_NBSLOT_MASK,
8853e086edfSolivier moysan SAI_XSLOTR_NBSLOT_SET((sai->slots - 1)));
8863e086edfSolivier moysan
8873e086edfSolivier moysan /* Set default slots mask if not already set from DT */
8883e086edfSolivier moysan if (!(slotr & SAI_XSLOTR_SLOTEN_MASK)) {
8893e086edfSolivier moysan sai->slot_mask = (1 << sai->slots) - 1;
890a14bf98cSOlivier Moysan stm32_sai_sub_reg_up(sai,
8913e086edfSolivier moysan STM_SAI_SLOTR_REGX, SAI_XSLOTR_SLOTEN_MASK,
8923e086edfSolivier moysan SAI_XSLOTR_SLOTEN_SET(sai->slot_mask));
8933e086edfSolivier moysan }
8943e086edfSolivier moysan
895602fdadcSolivier moysan dev_dbg(cpu_dai->dev, "Slots %d, slot width %d\n",
8963e086edfSolivier moysan sai->slots, sai->slot_width);
8973e086edfSolivier moysan
8983e086edfSolivier moysan return 0;
8993e086edfSolivier moysan }
9003e086edfSolivier moysan
stm32_sai_set_frame(struct snd_soc_dai * cpu_dai)9013e086edfSolivier moysan static void stm32_sai_set_frame(struct snd_soc_dai *cpu_dai)
9023e086edfSolivier moysan {
9033e086edfSolivier moysan struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
9043e086edfSolivier moysan int fs_active, offset, format;
9053e086edfSolivier moysan int frcr, frcr_mask;
9063e086edfSolivier moysan
9073e086edfSolivier moysan format = sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
9083e086edfSolivier moysan sai->fs_length = sai->slot_width * sai->slots;
9093e086edfSolivier moysan
9103e086edfSolivier moysan fs_active = sai->fs_length / 2;
9113e086edfSolivier moysan if ((format == SND_SOC_DAIFMT_DSP_A) ||
9123e086edfSolivier moysan (format == SND_SOC_DAIFMT_DSP_B))
9133e086edfSolivier moysan fs_active = 1;
9143e086edfSolivier moysan
9153e086edfSolivier moysan frcr = SAI_XFRCR_FRL_SET((sai->fs_length - 1));
9163e086edfSolivier moysan frcr |= SAI_XFRCR_FSALL_SET((fs_active - 1));
9173e086edfSolivier moysan frcr_mask = SAI_XFRCR_FRL_MASK | SAI_XFRCR_FSALL_MASK;
9183e086edfSolivier moysan
919602fdadcSolivier moysan dev_dbg(cpu_dai->dev, "Frame length %d, frame active %d\n",
9203e086edfSolivier moysan sai->fs_length, fs_active);
9213e086edfSolivier moysan
922a14bf98cSOlivier Moysan stm32_sai_sub_reg_up(sai, STM_SAI_FRCR_REGX, frcr_mask, frcr);
9233e086edfSolivier moysan
9243e086edfSolivier moysan if ((sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_LSB) {
9253e086edfSolivier moysan offset = sai->slot_width - sai->data_size;
9263e086edfSolivier moysan
927a14bf98cSOlivier Moysan stm32_sai_sub_reg_up(sai, STM_SAI_SLOTR_REGX,
9283e086edfSolivier moysan SAI_XSLOTR_FBOFF_MASK,
9293e086edfSolivier moysan SAI_XSLOTR_FBOFF_SET(offset));
9303e086edfSolivier moysan }
9313e086edfSolivier moysan }
9323e086edfSolivier moysan
stm32_sai_init_iec958_status(struct stm32_sai_sub_data * sai)933187e01d0Solivier moysan static void stm32_sai_init_iec958_status(struct stm32_sai_sub_data *sai)
934187e01d0Solivier moysan {
935187e01d0Solivier moysan unsigned char *cs = sai->iec958.status;
936187e01d0Solivier moysan
937187e01d0Solivier moysan cs[0] = IEC958_AES0_CON_NOT_COPYRIGHT | IEC958_AES0_CON_EMPHASIS_NONE;
938187e01d0Solivier moysan cs[1] = IEC958_AES1_CON_GENERAL;
939187e01d0Solivier moysan cs[2] = IEC958_AES2_CON_SOURCE_UNSPEC | IEC958_AES2_CON_CHANNEL_UNSPEC;
940187e01d0Solivier moysan cs[3] = IEC958_AES3_CON_CLOCK_1000PPM | IEC958_AES3_CON_FS_NOTID;
941187e01d0Solivier moysan }
942187e01d0Solivier moysan
stm32_sai_set_iec958_status(struct stm32_sai_sub_data * sai,struct snd_pcm_runtime * runtime)943187e01d0Solivier moysan static void stm32_sai_set_iec958_status(struct stm32_sai_sub_data *sai,
944187e01d0Solivier moysan struct snd_pcm_runtime *runtime)
945187e01d0Solivier moysan {
946187e01d0Solivier moysan if (!runtime)
947187e01d0Solivier moysan return;
948187e01d0Solivier moysan
949187e01d0Solivier moysan /* Force the sample rate according to runtime rate */
950187e01d0Solivier moysan mutex_lock(&sai->ctrl_lock);
951187e01d0Solivier moysan switch (runtime->rate) {
952187e01d0Solivier moysan case 22050:
953187e01d0Solivier moysan sai->iec958.status[3] = IEC958_AES3_CON_FS_22050;
954187e01d0Solivier moysan break;
955187e01d0Solivier moysan case 44100:
956187e01d0Solivier moysan sai->iec958.status[3] = IEC958_AES3_CON_FS_44100;
957187e01d0Solivier moysan break;
958187e01d0Solivier moysan case 88200:
959187e01d0Solivier moysan sai->iec958.status[3] = IEC958_AES3_CON_FS_88200;
960187e01d0Solivier moysan break;
961187e01d0Solivier moysan case 176400:
962187e01d0Solivier moysan sai->iec958.status[3] = IEC958_AES3_CON_FS_176400;
963187e01d0Solivier moysan break;
964187e01d0Solivier moysan case 24000:
965187e01d0Solivier moysan sai->iec958.status[3] = IEC958_AES3_CON_FS_24000;
966187e01d0Solivier moysan break;
967187e01d0Solivier moysan case 48000:
968187e01d0Solivier moysan sai->iec958.status[3] = IEC958_AES3_CON_FS_48000;
969187e01d0Solivier moysan break;
970187e01d0Solivier moysan case 96000:
971187e01d0Solivier moysan sai->iec958.status[3] = IEC958_AES3_CON_FS_96000;
972187e01d0Solivier moysan break;
973187e01d0Solivier moysan case 192000:
974187e01d0Solivier moysan sai->iec958.status[3] = IEC958_AES3_CON_FS_192000;
975187e01d0Solivier moysan break;
976187e01d0Solivier moysan case 32000:
977187e01d0Solivier moysan sai->iec958.status[3] = IEC958_AES3_CON_FS_32000;
978187e01d0Solivier moysan break;
979187e01d0Solivier moysan default:
980187e01d0Solivier moysan sai->iec958.status[3] = IEC958_AES3_CON_FS_NOTID;
981187e01d0Solivier moysan break;
982187e01d0Solivier moysan }
983187e01d0Solivier moysan mutex_unlock(&sai->ctrl_lock);
984187e01d0Solivier moysan }
985187e01d0Solivier moysan
stm32_sai_configure_clock(struct snd_soc_dai * cpu_dai,struct snd_pcm_hw_params * params)9863e086edfSolivier moysan static int stm32_sai_configure_clock(struct snd_soc_dai *cpu_dai,
9873e086edfSolivier moysan struct snd_pcm_hw_params *params)
9883e086edfSolivier moysan {
9893e086edfSolivier moysan struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
99071d9537fSOlivier Moysan int div = 0, cr1 = 0;
9918307b2afSOlivier Moysan int sai_clk_rate, mclk_ratio, den;
9926eb17d70SOlivier Moysan unsigned int rate = params_rate(params);
993e37c2deaSOlivier Moysan int ret;
9943e086edfSolivier moysan
995e37c2deaSOlivier Moysan if (!sai->sai_mclk) {
996e37c2deaSOlivier Moysan ret = stm32_sai_set_parent_clock(sai, rate);
997e37c2deaSOlivier Moysan if (ret)
998e37c2deaSOlivier Moysan return ret;
999e37c2deaSOlivier Moysan }
10003e086edfSolivier moysan sai_clk_rate = clk_get_rate(sai->sai_ck);
10013e086edfSolivier moysan
100203e78a24Solivier moysan if (STM_SAI_IS_F4(sai->pdata)) {
10038307b2afSOlivier Moysan /* mclk on (NODIV=0)
10043e086edfSolivier moysan * mclk_rate = 256 * fs
10053e086edfSolivier moysan * MCKDIV = 0 if sai_ck < 3/2 * mclk_rate
10063e086edfSolivier moysan * MCKDIV = sai_ck / (2 * mclk_rate) otherwise
10078307b2afSOlivier Moysan * mclk off (NODIV=1)
10088307b2afSOlivier Moysan * MCKDIV ignored. sck = sai_ck
10093e086edfSolivier moysan */
10108307b2afSOlivier Moysan if (!sai->mclk_rate)
10118307b2afSOlivier Moysan return 0;
10128307b2afSOlivier Moysan
10138307b2afSOlivier Moysan if (2 * sai_clk_rate >= 3 * sai->mclk_rate) {
10148307b2afSOlivier Moysan div = stm32_sai_get_clk_div(sai, sai_clk_rate,
101503e78a24Solivier moysan 2 * sai->mclk_rate);
10168307b2afSOlivier Moysan if (div < 0)
10178307b2afSOlivier Moysan return div;
10188307b2afSOlivier Moysan }
101903e78a24Solivier moysan } else {
102003e78a24Solivier moysan /*
102103e78a24Solivier moysan * TDM mode :
102203e78a24Solivier moysan * mclk on
102303e78a24Solivier moysan * MCKDIV = sai_ck / (ws x 256) (NOMCK=0. OSR=0)
102403e78a24Solivier moysan * MCKDIV = sai_ck / (ws x 512) (NOMCK=0. OSR=1)
102503e78a24Solivier moysan * mclk off
102603e78a24Solivier moysan * MCKDIV = sai_ck / (frl x ws) (NOMCK=1)
102703e78a24Solivier moysan * Note: NOMCK/NODIV correspond to same bit.
102803e78a24Solivier moysan */
10296eb17d70SOlivier Moysan if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
10308307b2afSOlivier Moysan div = stm32_sai_get_clk_div(sai, sai_clk_rate,
10318307b2afSOlivier Moysan rate * 128);
10328307b2afSOlivier Moysan if (div < 0)
10338307b2afSOlivier Moysan return div;
10346eb17d70SOlivier Moysan } else {
103503e78a24Solivier moysan if (sai->mclk_rate) {
10366eb17d70SOlivier Moysan mclk_ratio = sai->mclk_rate / rate;
103771d9537fSOlivier Moysan if (mclk_ratio == 512) {
103871d9537fSOlivier Moysan cr1 = SAI_XCR1_OSR;
103971d9537fSOlivier Moysan } else if (mclk_ratio != 256) {
104003e78a24Solivier moysan dev_err(cpu_dai->dev,
104103e78a24Solivier moysan "Wrong mclk ratio %d\n",
104203e78a24Solivier moysan mclk_ratio);
104303e78a24Solivier moysan return -EINVAL;
104403e78a24Solivier moysan }
104571d9537fSOlivier Moysan
1046a14bf98cSOlivier Moysan stm32_sai_sub_reg_up(sai,
104771d9537fSOlivier Moysan STM_SAI_CR1_REGX,
104871d9537fSOlivier Moysan SAI_XCR1_OSR, cr1);
104971d9537fSOlivier Moysan
10508307b2afSOlivier Moysan div = stm32_sai_get_clk_div(sai, sai_clk_rate,
10516eb17d70SOlivier Moysan sai->mclk_rate);
10528307b2afSOlivier Moysan if (div < 0)
10538307b2afSOlivier Moysan return div;
105403e78a24Solivier moysan } else {
10556eb17d70SOlivier Moysan /* mclk-fs not set, master clock not active */
105603e78a24Solivier moysan den = sai->fs_length * params_rate(params);
10578307b2afSOlivier Moysan div = stm32_sai_get_clk_div(sai, sai_clk_rate,
10588307b2afSOlivier Moysan den);
10598307b2afSOlivier Moysan if (div < 0)
10608307b2afSOlivier Moysan return div;
106103e78a24Solivier moysan }
106203e78a24Solivier moysan }
10636eb17d70SOlivier Moysan }
10643e086edfSolivier moysan
10658307b2afSOlivier Moysan return stm32_sai_set_clk_div(sai, div);
10663e086edfSolivier moysan }
10673e086edfSolivier moysan
stm32_sai_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * cpu_dai)10683e086edfSolivier moysan static int stm32_sai_hw_params(struct snd_pcm_substream *substream,
10693e086edfSolivier moysan struct snd_pcm_hw_params *params,
10703e086edfSolivier moysan struct snd_soc_dai *cpu_dai)
10713e086edfSolivier moysan {
10723e086edfSolivier moysan struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
10733e086edfSolivier moysan int ret;
10743e086edfSolivier moysan
10753e086edfSolivier moysan sai->data_size = params_width(params);
10763e086edfSolivier moysan
1077187e01d0Solivier moysan if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
1078187e01d0Solivier moysan /* Rate not already set in runtime structure */
1079187e01d0Solivier moysan substream->runtime->rate = params_rate(params);
1080187e01d0Solivier moysan stm32_sai_set_iec958_status(sai, substream->runtime);
1081187e01d0Solivier moysan } else {
10823e086edfSolivier moysan ret = stm32_sai_set_slots(cpu_dai);
10833e086edfSolivier moysan if (ret < 0)
10843e086edfSolivier moysan return ret;
10853e086edfSolivier moysan stm32_sai_set_frame(cpu_dai);
10866eb17d70SOlivier Moysan }
10873e086edfSolivier moysan
10883e086edfSolivier moysan ret = stm32_sai_set_config(cpu_dai, substream, params);
10893e086edfSolivier moysan if (ret)
10903e086edfSolivier moysan return ret;
10913e086edfSolivier moysan
10923e086edfSolivier moysan if (sai->master)
10933e086edfSolivier moysan ret = stm32_sai_configure_clock(cpu_dai, params);
10943e086edfSolivier moysan
10953e086edfSolivier moysan return ret;
10963e086edfSolivier moysan }
10973e086edfSolivier moysan
stm32_sai_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * cpu_dai)10983e086edfSolivier moysan static int stm32_sai_trigger(struct snd_pcm_substream *substream, int cmd,
10993e086edfSolivier moysan struct snd_soc_dai *cpu_dai)
11003e086edfSolivier moysan {
11013e086edfSolivier moysan struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
11023e086edfSolivier moysan int ret;
11033e086edfSolivier moysan
11043e086edfSolivier moysan switch (cmd) {
11053e086edfSolivier moysan case SNDRV_PCM_TRIGGER_START:
11063e086edfSolivier moysan case SNDRV_PCM_TRIGGER_RESUME:
11073e086edfSolivier moysan case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
11083e086edfSolivier moysan dev_dbg(cpu_dai->dev, "Enable DMA and SAI\n");
11093e086edfSolivier moysan
1110a14bf98cSOlivier Moysan stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX,
11113e086edfSolivier moysan SAI_XCR1_DMAEN, SAI_XCR1_DMAEN);
11123e086edfSolivier moysan
11133e086edfSolivier moysan /* Enable SAI */
1114a14bf98cSOlivier Moysan ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX,
11153e086edfSolivier moysan SAI_XCR1_SAIEN, SAI_XCR1_SAIEN);
11163e086edfSolivier moysan if (ret < 0)
11173e086edfSolivier moysan dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
11183e086edfSolivier moysan break;
11193e086edfSolivier moysan case SNDRV_PCM_TRIGGER_SUSPEND:
11203e086edfSolivier moysan case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
11213e086edfSolivier moysan case SNDRV_PCM_TRIGGER_STOP:
11223e086edfSolivier moysan dev_dbg(cpu_dai->dev, "Disable DMA and SAI\n");
11233e086edfSolivier moysan
1124a14bf98cSOlivier Moysan stm32_sai_sub_reg_up(sai, STM_SAI_IMR_REGX,
112547a8907dSOlivier Moysan SAI_XIMR_MASK, 0);
112647a8907dSOlivier Moysan
1127a14bf98cSOlivier Moysan stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX,
11283e086edfSolivier moysan SAI_XCR1_SAIEN,
11293e086edfSolivier moysan (unsigned int)~SAI_XCR1_SAIEN);
11304fa17938Solivier moysan
1131a14bf98cSOlivier Moysan ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX,
11324fa17938Solivier moysan SAI_XCR1_DMAEN,
11334fa17938Solivier moysan (unsigned int)~SAI_XCR1_DMAEN);
11343e086edfSolivier moysan if (ret < 0)
11353e086edfSolivier moysan dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
11366eb17d70SOlivier Moysan
11376eb17d70SOlivier Moysan if (STM_SAI_PROTOCOL_IS_SPDIF(sai))
11386eb17d70SOlivier Moysan sai->spdif_frm_cnt = 0;
11393e086edfSolivier moysan break;
11403e086edfSolivier moysan default:
11413e086edfSolivier moysan return -EINVAL;
11423e086edfSolivier moysan }
11433e086edfSolivier moysan
11443e086edfSolivier moysan return ret;
11453e086edfSolivier moysan }
11463e086edfSolivier moysan
stm32_sai_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * cpu_dai)11473e086edfSolivier moysan static void stm32_sai_shutdown(struct snd_pcm_substream *substream,
11483e086edfSolivier moysan struct snd_soc_dai *cpu_dai)
11493e086edfSolivier moysan {
11503e086edfSolivier moysan struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
115126f98e82SOlivier Moysan unsigned long flags;
11523e086edfSolivier moysan
1153a14bf98cSOlivier Moysan stm32_sai_sub_reg_up(sai, STM_SAI_IMR_REGX, SAI_XIMR_MASK, 0);
11543e086edfSolivier moysan
1155e37c2deaSOlivier Moysan clk_disable_unprepare(sai->sai_ck);
11568307b2afSOlivier Moysan
115726f98e82SOlivier Moysan spin_lock_irqsave(&sai->irq_lock, flags);
11583e086edfSolivier moysan sai->substream = NULL;
115926f98e82SOlivier Moysan spin_unlock_irqrestore(&sai->irq_lock, flags);
11603e086edfSolivier moysan }
11613e086edfSolivier moysan
stm32_sai_pcm_new(struct snd_soc_pcm_runtime * rtd,struct snd_soc_dai * cpu_dai)1162187e01d0Solivier moysan static int stm32_sai_pcm_new(struct snd_soc_pcm_runtime *rtd,
1163187e01d0Solivier moysan struct snd_soc_dai *cpu_dai)
1164187e01d0Solivier moysan {
1165187e01d0Solivier moysan struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev);
11665f8a1000SOlivier Moysan struct snd_kcontrol_new knew = iec958_ctls;
1167187e01d0Solivier moysan
1168187e01d0Solivier moysan if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
1169187e01d0Solivier moysan dev_dbg(&sai->pdev->dev, "%s: register iec controls", __func__);
11705f8a1000SOlivier Moysan knew.device = rtd->pcm->device;
11715f8a1000SOlivier Moysan return snd_ctl_add(rtd->pcm->card, snd_ctl_new1(&knew, sai));
1172187e01d0Solivier moysan }
1173187e01d0Solivier moysan
1174187e01d0Solivier moysan return 0;
1175187e01d0Solivier moysan }
1176187e01d0Solivier moysan
stm32_sai_dai_probe(struct snd_soc_dai * cpu_dai)11773e086edfSolivier moysan static int stm32_sai_dai_probe(struct snd_soc_dai *cpu_dai)
11783e086edfSolivier moysan {
11793e086edfSolivier moysan struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev);
1180d4180b4cSOlivier Moysan int cr1 = 0, cr1_mask, ret;
11813e086edfSolivier moysan
11828307b2afSOlivier Moysan sai->cpu_dai = cpu_dai;
11838307b2afSOlivier Moysan
11843e086edfSolivier moysan sai->dma_params.addr = (dma_addr_t)(sai->phys_addr + STM_SAI_DR_REGX);
1185a4529d2bSOlivier Moysan /*
1186a4529d2bSOlivier Moysan * DMA supports 4, 8 or 16 burst sizes. Burst size 4 is the best choice,
1187a4529d2bSOlivier Moysan * as it allows bytes, half-word and words transfers. (See DMA fifos
1188a4529d2bSOlivier Moysan * constraints).
1189a4529d2bSOlivier Moysan */
1190a4529d2bSOlivier Moysan sai->dma_params.maxburst = 4;
11911d9c95c1SOlivier Moysan if (sai->pdata->conf.fifo_size < 8)
11921d9c95c1SOlivier Moysan sai->dma_params.maxburst = 1;
11933e086edfSolivier moysan /* Buswidth will be set by framework at runtime */
11943e086edfSolivier moysan sai->dma_params.addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
11953e086edfSolivier moysan
11963e086edfSolivier moysan if (STM_SAI_IS_PLAYBACK(sai))
11973e086edfSolivier moysan snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params, NULL);
11983e086edfSolivier moysan else
11993e086edfSolivier moysan snd_soc_dai_init_dma_data(cpu_dai, NULL, &sai->dma_params);
12003e086edfSolivier moysan
1201187e01d0Solivier moysan /* Next settings are not relevant for spdif mode */
1202187e01d0Solivier moysan if (STM_SAI_PROTOCOL_IS_SPDIF(sai))
1203187e01d0Solivier moysan return 0;
1204187e01d0Solivier moysan
120561fb4ff7SOlivier Moysan cr1_mask = SAI_XCR1_RX_TX;
120661fb4ff7SOlivier Moysan if (STM_SAI_IS_CAPTURE(sai))
120761fb4ff7SOlivier Moysan cr1 |= SAI_XCR1_RX_TX;
120861fb4ff7SOlivier Moysan
12095914d285SOlivier Moysan /* Configure synchronization */
12105914d285SOlivier Moysan if (sai->sync == SAI_SYNC_EXTERNAL) {
12115914d285SOlivier Moysan /* Configure synchro client and provider */
1212d4180b4cSOlivier Moysan ret = sai->pdata->set_sync(sai->pdata, sai->np_sync_provider,
12135914d285SOlivier Moysan sai->synco, sai->synci);
1214d4180b4cSOlivier Moysan if (ret)
1215d4180b4cSOlivier Moysan return ret;
12165914d285SOlivier Moysan }
12175914d285SOlivier Moysan
12185914d285SOlivier Moysan cr1_mask |= SAI_XCR1_SYNCEN_MASK;
12195914d285SOlivier Moysan cr1 |= SAI_XCR1_SYNCEN_SET(sai->sync);
12205914d285SOlivier Moysan
1221a14bf98cSOlivier Moysan return stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, cr1_mask, cr1);
12223e086edfSolivier moysan }
12233e086edfSolivier moysan
12243e086edfSolivier moysan static const struct snd_soc_dai_ops stm32_sai_pcm_dai_ops = {
122553c577baSKuninori Morimoto .probe = stm32_sai_dai_probe,
122653c577baSKuninori Morimoto .set_sysclk = stm32_sai_set_sysclk,
122753c577baSKuninori Morimoto .set_fmt = stm32_sai_set_dai_fmt,
122853c577baSKuninori Morimoto .set_tdm_slot = stm32_sai_set_dai_tdm_slot,
122953c577baSKuninori Morimoto .startup = stm32_sai_startup,
123053c577baSKuninori Morimoto .hw_params = stm32_sai_hw_params,
123153c577baSKuninori Morimoto .trigger = stm32_sai_trigger,
123253c577baSKuninori Morimoto .shutdown = stm32_sai_shutdown,
123353c577baSKuninori Morimoto .pcm_new = stm32_sai_pcm_new,
123453c577baSKuninori Morimoto };
123553c577baSKuninori Morimoto
123653c577baSKuninori Morimoto static const struct snd_soc_dai_ops stm32_sai_pcm_dai_ops2 = {
123753c577baSKuninori Morimoto .probe = stm32_sai_dai_probe,
12383e086edfSolivier moysan .set_sysclk = stm32_sai_set_sysclk,
12393e086edfSolivier moysan .set_fmt = stm32_sai_set_dai_fmt,
12403e086edfSolivier moysan .set_tdm_slot = stm32_sai_set_dai_tdm_slot,
12413e086edfSolivier moysan .startup = stm32_sai_startup,
12423e086edfSolivier moysan .hw_params = stm32_sai_hw_params,
12433e086edfSolivier moysan .trigger = stm32_sai_trigger,
12443e086edfSolivier moysan .shutdown = stm32_sai_shutdown,
12453e086edfSolivier moysan };
12463e086edfSolivier moysan
stm32_sai_pcm_process_spdif(struct snd_pcm_substream * substream,int channel,unsigned long hwoff,unsigned long bytes)12476eb17d70SOlivier Moysan static int stm32_sai_pcm_process_spdif(struct snd_pcm_substream *substream,
12486eb17d70SOlivier Moysan int channel, unsigned long hwoff,
1249*69d0fd34STakashi Iwai unsigned long bytes)
12506eb17d70SOlivier Moysan {
12516eb17d70SOlivier Moysan struct snd_pcm_runtime *runtime = substream->runtime;
1252ddb4f06dSKuninori Morimoto struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
1253b1bee67cSKuninori Morimoto struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
12546eb17d70SOlivier Moysan struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev);
12556eb17d70SOlivier Moysan int *ptr = (int *)(runtime->dma_area + hwoff +
12566eb17d70SOlivier Moysan channel * (runtime->dma_bytes / runtime->channels));
12576eb17d70SOlivier Moysan ssize_t cnt = bytes_to_samples(runtime, bytes);
12586eb17d70SOlivier Moysan unsigned int frm_cnt = sai->spdif_frm_cnt;
12596eb17d70SOlivier Moysan unsigned int byte;
12606eb17d70SOlivier Moysan unsigned int mask;
12616eb17d70SOlivier Moysan
12626eb17d70SOlivier Moysan do {
12636eb17d70SOlivier Moysan *ptr = ((*ptr >> 8) & 0x00ffffff);
12646eb17d70SOlivier Moysan
12656eb17d70SOlivier Moysan /* Set channel status bit */
12666eb17d70SOlivier Moysan byte = frm_cnt >> 3;
12676eb17d70SOlivier Moysan mask = 1 << (frm_cnt - (byte << 3));
1268187e01d0Solivier moysan if (sai->iec958.status[byte] & mask)
12696eb17d70SOlivier Moysan *ptr |= 0x04000000;
12706eb17d70SOlivier Moysan ptr++;
12716eb17d70SOlivier Moysan
12726eb17d70SOlivier Moysan if (!(cnt % 2))
12736eb17d70SOlivier Moysan frm_cnt++;
12746eb17d70SOlivier Moysan
12756eb17d70SOlivier Moysan if (frm_cnt == SAI_IEC60958_BLOCK_FRAMES)
12766eb17d70SOlivier Moysan frm_cnt = 0;
12776eb17d70SOlivier Moysan } while (--cnt);
12786eb17d70SOlivier Moysan sai->spdif_frm_cnt = frm_cnt;
12796eb17d70SOlivier Moysan
12806eb17d70SOlivier Moysan return 0;
12816eb17d70SOlivier Moysan }
12826eb17d70SOlivier Moysan
1283eaf072e5SOlivier Moysan /* No support of mmap in S/PDIF mode */
1284eaf072e5SOlivier Moysan static const struct snd_pcm_hardware stm32_sai_pcm_hw_spdif = {
1285eaf072e5SOlivier Moysan .info = SNDRV_PCM_INFO_INTERLEAVED,
1286eaf072e5SOlivier Moysan .buffer_bytes_max = 8 * PAGE_SIZE,
1287eaf072e5SOlivier Moysan .period_bytes_min = 1024,
1288eaf072e5SOlivier Moysan .period_bytes_max = PAGE_SIZE,
1289eaf072e5SOlivier Moysan .periods_min = 2,
1290eaf072e5SOlivier Moysan .periods_max = 8,
1291eaf072e5SOlivier Moysan };
1292eaf072e5SOlivier Moysan
12933e086edfSolivier moysan static const struct snd_pcm_hardware stm32_sai_pcm_hw = {
12943e086edfSolivier moysan .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP,
12953e086edfSolivier moysan .buffer_bytes_max = 8 * PAGE_SIZE,
12963e086edfSolivier moysan .period_bytes_min = 1024, /* 5ms at 48kHz */
12973e086edfSolivier moysan .period_bytes_max = PAGE_SIZE,
12983e086edfSolivier moysan .periods_min = 2,
12993e086edfSolivier moysan .periods_max = 8,
13003e086edfSolivier moysan };
13013e086edfSolivier moysan
13028f8a5488SArnaud Pouliquen static struct snd_soc_dai_driver stm32_sai_playback_dai = {
13033e086edfSolivier moysan .id = 1, /* avoid call to fmt_single_name() */
13043e086edfSolivier moysan .playback = {
13053e086edfSolivier moysan .channels_min = 1,
13067fabe7feSOlivier Moysan .channels_max = 16,
13073e086edfSolivier moysan .rate_min = 8000,
13083e086edfSolivier moysan .rate_max = 192000,
13093e086edfSolivier moysan .rates = SNDRV_PCM_RATE_CONTINUOUS,
13103e086edfSolivier moysan /* DMA does not support 24 bits transfers */
13113e086edfSolivier moysan .formats =
13123e086edfSolivier moysan SNDRV_PCM_FMTBIT_S8 |
13133e086edfSolivier moysan SNDRV_PCM_FMTBIT_S16_LE |
13143e086edfSolivier moysan SNDRV_PCM_FMTBIT_S32_LE,
13153e086edfSolivier moysan },
13163e086edfSolivier moysan .ops = &stm32_sai_pcm_dai_ops,
13173e086edfSolivier moysan };
13183e086edfSolivier moysan
13198f8a5488SArnaud Pouliquen static struct snd_soc_dai_driver stm32_sai_capture_dai = {
13203e086edfSolivier moysan .id = 1, /* avoid call to fmt_single_name() */
13213e086edfSolivier moysan .capture = {
13223e086edfSolivier moysan .channels_min = 1,
13237fabe7feSOlivier Moysan .channels_max = 16,
13243e086edfSolivier moysan .rate_min = 8000,
13253e086edfSolivier moysan .rate_max = 192000,
13263e086edfSolivier moysan .rates = SNDRV_PCM_RATE_CONTINUOUS,
13273e086edfSolivier moysan /* DMA does not support 24 bits transfers */
13283e086edfSolivier moysan .formats =
13293e086edfSolivier moysan SNDRV_PCM_FMTBIT_S8 |
13303e086edfSolivier moysan SNDRV_PCM_FMTBIT_S16_LE |
13313e086edfSolivier moysan SNDRV_PCM_FMTBIT_S32_LE,
13323e086edfSolivier moysan },
133353c577baSKuninori Morimoto .ops = &stm32_sai_pcm_dai_ops2,
13343e086edfSolivier moysan };
13353e086edfSolivier moysan
13363e086edfSolivier moysan static const struct snd_dmaengine_pcm_config stm32_sai_pcm_config = {
13373e086edfSolivier moysan .pcm_hardware = &stm32_sai_pcm_hw,
13383e086edfSolivier moysan .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
13393e086edfSolivier moysan };
13403e086edfSolivier moysan
13416eb17d70SOlivier Moysan static const struct snd_dmaengine_pcm_config stm32_sai_pcm_config_spdif = {
1342eaf072e5SOlivier Moysan .pcm_hardware = &stm32_sai_pcm_hw_spdif,
13436eb17d70SOlivier Moysan .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
13446eb17d70SOlivier Moysan .process = stm32_sai_pcm_process_spdif,
13456eb17d70SOlivier Moysan };
13466eb17d70SOlivier Moysan
13473e086edfSolivier moysan static const struct snd_soc_component_driver stm32_component = {
13483e086edfSolivier moysan .name = "stm32-sai",
134936f07985SCharles Keepax .legacy_dai_naming = 1,
13503e086edfSolivier moysan };
13513e086edfSolivier moysan
13523e086edfSolivier moysan static const struct of_device_id stm32_sai_sub_ids[] = {
13533e086edfSolivier moysan { .compatible = "st,stm32-sai-sub-a",
13543e086edfSolivier moysan .data = (void *)STM_SAI_A_ID},
13553e086edfSolivier moysan { .compatible = "st,stm32-sai-sub-b",
13563e086edfSolivier moysan .data = (void *)STM_SAI_B_ID},
13573e086edfSolivier moysan {}
13583e086edfSolivier moysan };
13593e086edfSolivier moysan MODULE_DEVICE_TABLE(of, stm32_sai_sub_ids);
13603e086edfSolivier moysan
stm32_sai_sub_parse_of(struct platform_device * pdev,struct stm32_sai_sub_data * sai)13613e086edfSolivier moysan static int stm32_sai_sub_parse_of(struct platform_device *pdev,
13623e086edfSolivier moysan struct stm32_sai_sub_data *sai)
13633e086edfSolivier moysan {
13643e086edfSolivier moysan struct device_node *np = pdev->dev.of_node;
13653e086edfSolivier moysan struct resource *res;
13663e086edfSolivier moysan void __iomem *base;
13675914d285SOlivier Moysan struct of_phandle_args args;
13685914d285SOlivier Moysan int ret;
13693e086edfSolivier moysan
13703e086edfSolivier moysan if (!np)
13713e086edfSolivier moysan return -ENODEV;
13723e086edfSolivier moysan
1373003ee640SYang Yingliang base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
13743e086edfSolivier moysan if (IS_ERR(base))
13753e086edfSolivier moysan return PTR_ERR(base);
13763e086edfSolivier moysan
13773e086edfSolivier moysan sai->phys_addr = res->start;
137803e78a24Solivier moysan
137903e78a24Solivier moysan sai->regmap_config = &stm32_sai_sub_regmap_config_f4;
13801d9c95c1SOlivier Moysan /* Note: PDM registers not available for sub-block B */
13811d9c95c1SOlivier Moysan if (STM_SAI_HAS_PDM(sai) && STM_SAI_IS_SUB_A(sai))
138203e78a24Solivier moysan sai->regmap_config = &stm32_sai_sub_regmap_config_h7;
138303e78a24Solivier moysan
1384a14bf98cSOlivier Moysan /*
1385a14bf98cSOlivier Moysan * Do not manage peripheral clock through regmap framework as this
1386a14bf98cSOlivier Moysan * can lead to circular locking issue with sai master clock provider.
1387a14bf98cSOlivier Moysan * Manage peripheral clock directly in driver instead.
1388a14bf98cSOlivier Moysan */
1389a14bf98cSOlivier Moysan sai->regmap = devm_regmap_init_mmio(&pdev->dev, base,
1390a14bf98cSOlivier Moysan sai->regmap_config);
1391efc162cbSKuninori Morimoto if (IS_ERR(sai->regmap))
1392efc162cbSKuninori Morimoto return dev_err_probe(&pdev->dev, PTR_ERR(sai->regmap),
1393efc162cbSKuninori Morimoto "Regmap init error\n");
13943e086edfSolivier moysan
13953e086edfSolivier moysan /* Get direction property */
13963e086edfSolivier moysan if (of_property_match_string(np, "dma-names", "tx") >= 0) {
13973e086edfSolivier moysan sai->dir = SNDRV_PCM_STREAM_PLAYBACK;
13983e086edfSolivier moysan } else if (of_property_match_string(np, "dma-names", "rx") >= 0) {
13993e086edfSolivier moysan sai->dir = SNDRV_PCM_STREAM_CAPTURE;
14003e086edfSolivier moysan } else {
14013e086edfSolivier moysan dev_err(&pdev->dev, "Unsupported direction\n");
14023e086edfSolivier moysan return -EINVAL;
14033e086edfSolivier moysan }
14043e086edfSolivier moysan
14056eb17d70SOlivier Moysan /* Get spdif iec60958 property */
14066eb17d70SOlivier Moysan sai->spdif = false;
14071e108e60SRob Herring if (of_property_present(np, "st,iec60958")) {
14086eb17d70SOlivier Moysan if (!STM_SAI_HAS_SPDIF(sai) ||
14096eb17d70SOlivier Moysan sai->dir == SNDRV_PCM_STREAM_CAPTURE) {
14106eb17d70SOlivier Moysan dev_err(&pdev->dev, "S/PDIF IEC60958 not supported\n");
14116eb17d70SOlivier Moysan return -EINVAL;
14126eb17d70SOlivier Moysan }
1413187e01d0Solivier moysan stm32_sai_init_iec958_status(sai);
14146eb17d70SOlivier Moysan sai->spdif = true;
14156eb17d70SOlivier Moysan sai->master = true;
14166eb17d70SOlivier Moysan }
14176eb17d70SOlivier Moysan
14185914d285SOlivier Moysan /* Get synchronization property */
14195914d285SOlivier Moysan args.np = NULL;
14205914d285SOlivier Moysan ret = of_parse_phandle_with_fixed_args(np, "st,sync", 1, 0, &args);
14215914d285SOlivier Moysan if (ret < 0 && ret != -ENOENT) {
14225914d285SOlivier Moysan dev_err(&pdev->dev, "Failed to get st,sync property\n");
14235914d285SOlivier Moysan return ret;
14245914d285SOlivier Moysan }
14255914d285SOlivier Moysan
14265914d285SOlivier Moysan sai->sync = SAI_SYNC_NONE;
14275914d285SOlivier Moysan if (args.np) {
14285914d285SOlivier Moysan if (args.np == np) {
14295d585e1eSRob Herring dev_err(&pdev->dev, "%pOFn sync own reference\n", np);
14305914d285SOlivier Moysan of_node_put(args.np);
14315914d285SOlivier Moysan return -EINVAL;
14325914d285SOlivier Moysan }
14335914d285SOlivier Moysan
14345914d285SOlivier Moysan sai->np_sync_provider = of_get_parent(args.np);
14355914d285SOlivier Moysan if (!sai->np_sync_provider) {
14365d585e1eSRob Herring dev_err(&pdev->dev, "%pOFn parent node not found\n",
14375d585e1eSRob Herring np);
14385914d285SOlivier Moysan of_node_put(args.np);
14395914d285SOlivier Moysan return -ENODEV;
14405914d285SOlivier Moysan }
14415914d285SOlivier Moysan
14425914d285SOlivier Moysan sai->sync = SAI_SYNC_INTERNAL;
14435914d285SOlivier Moysan if (sai->np_sync_provider != sai->pdata->pdev->dev.of_node) {
14445914d285SOlivier Moysan if (!STM_SAI_HAS_EXT_SYNC(sai)) {
14455914d285SOlivier Moysan dev_err(&pdev->dev,
14465914d285SOlivier Moysan "External synchro not supported\n");
14475914d285SOlivier Moysan of_node_put(args.np);
14485914d285SOlivier Moysan return -EINVAL;
14495914d285SOlivier Moysan }
14505914d285SOlivier Moysan sai->sync = SAI_SYNC_EXTERNAL;
14515914d285SOlivier Moysan
14525914d285SOlivier Moysan sai->synci = args.args[0];
14535914d285SOlivier Moysan if (sai->synci < 1 ||
14545914d285SOlivier Moysan (sai->synci > (SAI_GCR_SYNCIN_MAX + 1))) {
14555914d285SOlivier Moysan dev_err(&pdev->dev, "Wrong SAI index\n");
14565914d285SOlivier Moysan of_node_put(args.np);
14575914d285SOlivier Moysan return -EINVAL;
14585914d285SOlivier Moysan }
14595914d285SOlivier Moysan
14605914d285SOlivier Moysan if (of_property_match_string(args.np, "compatible",
14615914d285SOlivier Moysan "st,stm32-sai-sub-a") >= 0)
14625914d285SOlivier Moysan sai->synco = STM_SAI_SYNC_OUT_A;
14635914d285SOlivier Moysan
14645914d285SOlivier Moysan if (of_property_match_string(args.np, "compatible",
14655914d285SOlivier Moysan "st,stm32-sai-sub-b") >= 0)
14665914d285SOlivier Moysan sai->synco = STM_SAI_SYNC_OUT_B;
14675914d285SOlivier Moysan
14685914d285SOlivier Moysan if (!sai->synco) {
14695914d285SOlivier Moysan dev_err(&pdev->dev, "Unknown SAI sub-block\n");
14705914d285SOlivier Moysan of_node_put(args.np);
14715914d285SOlivier Moysan return -EINVAL;
14725914d285SOlivier Moysan }
14735914d285SOlivier Moysan }
14745914d285SOlivier Moysan
14755914d285SOlivier Moysan dev_dbg(&pdev->dev, "%s synchronized with %s\n",
14765914d285SOlivier Moysan pdev->name, args.np->full_name);
14775914d285SOlivier Moysan }
14785914d285SOlivier Moysan
14795914d285SOlivier Moysan of_node_put(args.np);
14803e086edfSolivier moysan sai->sai_ck = devm_clk_get(&pdev->dev, "sai_ck");
1481efc162cbSKuninori Morimoto if (IS_ERR(sai->sai_ck))
1482efc162cbSKuninori Morimoto return dev_err_probe(&pdev->dev, PTR_ERR(sai->sai_ck),
1483efc162cbSKuninori Morimoto "Missing kernel clock sai_ck\n");
14843e086edfSolivier moysan
1485a14bf98cSOlivier Moysan ret = clk_prepare(sai->pdata->pclk);
1486a14bf98cSOlivier Moysan if (ret < 0)
1487a14bf98cSOlivier Moysan return ret;
1488a14bf98cSOlivier Moysan
14898307b2afSOlivier Moysan if (STM_SAI_IS_F4(sai->pdata))
14908307b2afSOlivier Moysan return 0;
14918307b2afSOlivier Moysan
14928307b2afSOlivier Moysan /* Register mclk provider if requested */
14931e108e60SRob Herring if (of_property_present(np, "#clock-cells")) {
14948307b2afSOlivier Moysan ret = stm32_sai_add_mclk_provider(sai);
14958307b2afSOlivier Moysan if (ret < 0)
14968307b2afSOlivier Moysan return ret;
14978307b2afSOlivier Moysan } else {
1498374628fbSChristophe JAILLET sai->sai_mclk = devm_clk_get_optional(&pdev->dev, "MCLK");
1499374628fbSChristophe JAILLET if (IS_ERR(sai->sai_mclk))
15008307b2afSOlivier Moysan return PTR_ERR(sai->sai_mclk);
15018307b2afSOlivier Moysan }
15028307b2afSOlivier Moysan
15033e086edfSolivier moysan return 0;
15043e086edfSolivier moysan }
15053e086edfSolivier moysan
stm32_sai_sub_probe(struct platform_device * pdev)15063e086edfSolivier moysan static int stm32_sai_sub_probe(struct platform_device *pdev)
15073e086edfSolivier moysan {
15083e086edfSolivier moysan struct stm32_sai_sub_data *sai;
15093e086edfSolivier moysan const struct of_device_id *of_id;
15106eb17d70SOlivier Moysan const struct snd_dmaengine_pcm_config *conf = &stm32_sai_pcm_config;
15113e086edfSolivier moysan int ret;
15123e086edfSolivier moysan
15133e086edfSolivier moysan sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL);
15143e086edfSolivier moysan if (!sai)
15153e086edfSolivier moysan return -ENOMEM;
15163e086edfSolivier moysan
15173e086edfSolivier moysan of_id = of_match_device(stm32_sai_sub_ids, &pdev->dev);
15183e086edfSolivier moysan if (!of_id)
15193e086edfSolivier moysan return -EINVAL;
15203e086edfSolivier moysan sai->id = (uintptr_t)of_id->data;
15213e086edfSolivier moysan
15223e086edfSolivier moysan sai->pdev = pdev;
1523187e01d0Solivier moysan mutex_init(&sai->ctrl_lock);
152426f98e82SOlivier Moysan spin_lock_init(&sai->irq_lock);
15253e086edfSolivier moysan platform_set_drvdata(pdev, sai);
15263e086edfSolivier moysan
15273e086edfSolivier moysan sai->pdata = dev_get_drvdata(pdev->dev.parent);
15283e086edfSolivier moysan if (!sai->pdata) {
15293e086edfSolivier moysan dev_err(&pdev->dev, "Parent device data not available\n");
15303e086edfSolivier moysan return -EINVAL;
15313e086edfSolivier moysan }
15323e086edfSolivier moysan
15333e086edfSolivier moysan ret = stm32_sai_sub_parse_of(pdev, sai);
15343e086edfSolivier moysan if (ret)
15353e086edfSolivier moysan return ret;
15363e086edfSolivier moysan
15378f8a5488SArnaud Pouliquen if (STM_SAI_IS_PLAYBACK(sai))
15388f8a5488SArnaud Pouliquen sai->cpu_dai_drv = stm32_sai_playback_dai;
15398f8a5488SArnaud Pouliquen else
15408f8a5488SArnaud Pouliquen sai->cpu_dai_drv = stm32_sai_capture_dai;
15418f8a5488SArnaud Pouliquen sai->cpu_dai_drv.name = dev_name(&pdev->dev);
15423e086edfSolivier moysan
15433e086edfSolivier moysan ret = devm_request_irq(&pdev->dev, sai->pdata->irq, stm32_sai_isr,
15443e086edfSolivier moysan IRQF_SHARED, dev_name(&pdev->dev), sai);
15453e086edfSolivier moysan if (ret) {
1546602fdadcSolivier moysan dev_err(&pdev->dev, "IRQ request returned %d\n", ret);
15473e086edfSolivier moysan return ret;
15483e086edfSolivier moysan }
15493e086edfSolivier moysan
1550e2bcb657SOlivier Moysan if (STM_SAI_PROTOCOL_IS_SPDIF(sai))
1551e2bcb657SOlivier Moysan conf = &stm32_sai_pcm_config_spdif;
1552e2bcb657SOlivier Moysan
15530d6defc7SOlivier Moysan ret = snd_dmaengine_pcm_register(&pdev->dev, conf, 0);
1554efc162cbSKuninori Morimoto if (ret)
1555efc162cbSKuninori Morimoto return dev_err_probe(&pdev->dev, ret, "Could not register pcm dma\n");
15560d6defc7SOlivier Moysan
15570d6defc7SOlivier Moysan ret = snd_soc_register_component(&pdev->dev, &stm32_component,
15588f8a5488SArnaud Pouliquen &sai->cpu_dai_drv, 1);
15594e723e75SOlivier Moysan if (ret) {
15607506baeeSJulia Lawall snd_dmaengine_pcm_unregister(&pdev->dev);
15613e086edfSolivier moysan return ret;
15627506baeeSJulia Lawall }
15633e086edfSolivier moysan
15644e723e75SOlivier Moysan pm_runtime_enable(&pdev->dev);
15654e723e75SOlivier Moysan
15664e723e75SOlivier Moysan return 0;
15674e723e75SOlivier Moysan }
15684e723e75SOlivier Moysan
stm32_sai_sub_remove(struct platform_device * pdev)1569a3bd37e2SUwe Kleine-König static void stm32_sai_sub_remove(struct platform_device *pdev)
1570a14bf98cSOlivier Moysan {
1571a14bf98cSOlivier Moysan struct stm32_sai_sub_data *sai = dev_get_drvdata(&pdev->dev);
1572a14bf98cSOlivier Moysan
1573a14bf98cSOlivier Moysan clk_unprepare(sai->pdata->pclk);
15740d6defc7SOlivier Moysan snd_dmaengine_pcm_unregister(&pdev->dev);
15750d6defc7SOlivier Moysan snd_soc_unregister_component(&pdev->dev);
15764e723e75SOlivier Moysan pm_runtime_disable(&pdev->dev);
1577a14bf98cSOlivier Moysan }
1578a14bf98cSOlivier Moysan
1579cf881773SOlivier Moysan #ifdef CONFIG_PM_SLEEP
stm32_sai_sub_suspend(struct device * dev)1580cf881773SOlivier Moysan static int stm32_sai_sub_suspend(struct device *dev)
1581cf881773SOlivier Moysan {
1582cf881773SOlivier Moysan struct stm32_sai_sub_data *sai = dev_get_drvdata(dev);
1583a14bf98cSOlivier Moysan int ret;
1584a14bf98cSOlivier Moysan
1585a14bf98cSOlivier Moysan ret = clk_enable(sai->pdata->pclk);
1586a14bf98cSOlivier Moysan if (ret < 0)
1587a14bf98cSOlivier Moysan return ret;
1588cf881773SOlivier Moysan
1589cf881773SOlivier Moysan regcache_cache_only(sai->regmap, true);
1590cf881773SOlivier Moysan regcache_mark_dirty(sai->regmap);
1591a14bf98cSOlivier Moysan
1592a14bf98cSOlivier Moysan clk_disable(sai->pdata->pclk);
1593a14bf98cSOlivier Moysan
1594cf881773SOlivier Moysan return 0;
1595cf881773SOlivier Moysan }
1596cf881773SOlivier Moysan
stm32_sai_sub_resume(struct device * dev)1597cf881773SOlivier Moysan static int stm32_sai_sub_resume(struct device *dev)
1598cf881773SOlivier Moysan {
1599cf881773SOlivier Moysan struct stm32_sai_sub_data *sai = dev_get_drvdata(dev);
1600a14bf98cSOlivier Moysan int ret;
1601a14bf98cSOlivier Moysan
1602a14bf98cSOlivier Moysan ret = clk_enable(sai->pdata->pclk);
1603a14bf98cSOlivier Moysan if (ret < 0)
1604a14bf98cSOlivier Moysan return ret;
1605cf881773SOlivier Moysan
1606cf881773SOlivier Moysan regcache_cache_only(sai->regmap, false);
1607a14bf98cSOlivier Moysan ret = regcache_sync(sai->regmap);
1608a14bf98cSOlivier Moysan
1609a14bf98cSOlivier Moysan clk_disable(sai->pdata->pclk);
1610a14bf98cSOlivier Moysan
1611a14bf98cSOlivier Moysan return ret;
1612cf881773SOlivier Moysan }
1613cf881773SOlivier Moysan #endif /* CONFIG_PM_SLEEP */
1614cf881773SOlivier Moysan
1615cf881773SOlivier Moysan static const struct dev_pm_ops stm32_sai_sub_pm_ops = {
1616cf881773SOlivier Moysan SET_SYSTEM_SLEEP_PM_OPS(stm32_sai_sub_suspend, stm32_sai_sub_resume)
1617cf881773SOlivier Moysan };
1618cf881773SOlivier Moysan
16193e086edfSolivier moysan static struct platform_driver stm32_sai_sub_driver = {
16203e086edfSolivier moysan .driver = {
16213e086edfSolivier moysan .name = "st,stm32-sai-sub",
16223e086edfSolivier moysan .of_match_table = stm32_sai_sub_ids,
1623cf881773SOlivier Moysan .pm = &stm32_sai_sub_pm_ops,
16243e086edfSolivier moysan },
16253e086edfSolivier moysan .probe = stm32_sai_sub_probe,
1626a3bd37e2SUwe Kleine-König .remove_new = stm32_sai_sub_remove,
16273e086edfSolivier moysan };
16283e086edfSolivier moysan
16293e086edfSolivier moysan module_platform_driver(stm32_sai_sub_driver);
16303e086edfSolivier moysan
16313e086edfSolivier moysan MODULE_DESCRIPTION("STM32 Soc SAI sub-block Interface");
1632602fdadcSolivier moysan MODULE_AUTHOR("Olivier Moysan <olivier.moysan@st.com>");
16333e086edfSolivier moysan MODULE_ALIAS("platform:st,stm32-sai-sub");
16343e086edfSolivier moysan MODULE_LICENSE("GPL v2");
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