Lines Matching +full:mclk +full:- +full:div
1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Maxime Ripard <maxime.ripard@free-electrons.com>
22 #include <sound/soc-dai.h>
78 #define SUN4I_I2S_CLK_DIV_MCLK(mclk) ((mclk) << 0) argument
85 #define SUN4I_I2S_CHAN_SEL(num_chan) (((num_chan) - 1) << 0)
93 /* Defines required for sun8i-h3 support */
106 #define SUN8I_I2S_FMT0_LRCK_PERIOD(period) ((period - 1) << 8)
119 #define SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(chan) ((chan - 1) << 4)
121 #define SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(chan) (chan - 1)
128 #define SUN8I_I2S_TX_CHAN_EN(num_chan) (((1 << num_chan) - 1) << 4)
133 /* Defines required for sun50i-h6 support */
137 #define SUN50I_H6_I2S_TX_CHAN_SEL(chan) ((chan - 1) << 16)
139 #define SUN50I_H6_I2S_TX_CHAN_EN(num_chan) (((1 << num_chan) - 1))
157 * struct sun4i_i2s_quirks - Differences between SoC variants.
161 * @field_clkdiv_mclk_en: regmap field to enable mclk output.
168 * @mclk_dividers: mclk dividers array
169 * @num_mclk_dividers: number of mclk dividers
232 u8 div; member
237 { .div = 2, .val = 0 },
238 { .div = 4, .val = 1 },
239 { .div = 6, .val = 2 },
240 { .div = 8, .val = 3 },
241 { .div = 12, .val = 4 },
242 { .div = 16, .val = 5 },
243 /* TODO - extend divide ratio supported by newer SoCs */
247 { .div = 1, .val = 0 },
248 { .div = 2, .val = 1 },
249 { .div = 4, .val = 2 },
250 { .div = 6, .val = 3 },
251 { .div = 8, .val = 4 },
252 { .div = 12, .val = 5 },
253 { .div = 16, .val = 6 },
254 { .div = 24, .val = 7 },
255 /* TODO - extend divide ratio supported by newer SoCs */
259 { .div = 1, .val = 1 },
260 { .div = 2, .val = 2 },
261 { .div = 4, .val = 3 },
262 { .div = 6, .val = 4 },
263 { .div = 8, .val = 5 },
264 { .div = 12, .val = 6 },
265 { .div = 16, .val = 7 },
266 { .div = 24, .val = 8 },
267 { .div = 32, .val = 9 },
268 { .div = 48, .val = 10 },
269 { .div = 64, .val = 11 },
270 { .div = 96, .val = 12 },
271 { .div = 128, .val = 13 },
272 { .div = 176, .val = 14 },
273 { .div = 192, .val = 15 },
278 return i2s->mclk_freq; in sun4i_i2s_get_bclk_parent_rate()
283 return clk_get_rate(i2s->mod_clk); in sun8i_i2s_get_bclk_parent_rate()
292 const struct sun4i_i2s_clk_div *dividers = i2s->variant->bclk_dividers; in sun4i_i2s_get_bclk_div()
293 int div = parent_rate / sampling_rate / word_size / channels; in sun4i_i2s_get_bclk_div() local
296 for (i = 0; i < i2s->variant->num_bclk_dividers; i++) { in sun4i_i2s_get_bclk_div()
299 if (bdiv->div == div) in sun4i_i2s_get_bclk_div()
300 return bdiv->val; in sun4i_i2s_get_bclk_div()
303 return -EINVAL; in sun4i_i2s_get_bclk_div()
310 const struct sun4i_i2s_clk_div *dividers = i2s->variant->mclk_dividers; in sun4i_i2s_get_mclk_div()
311 int div = parent_rate / mclk_rate; in sun4i_i2s_get_mclk_div() local
314 for (i = 0; i < i2s->variant->num_mclk_dividers; i++) { in sun4i_i2s_get_mclk_div()
317 if (mdiv->div == div) in sun4i_i2s_get_mclk_div()
318 return mdiv->val; in sun4i_i2s_get_mclk_div()
321 return -EINVAL; in sun4i_i2s_get_mclk_div()
369 dev_err(dai->dev, "Unsupported sample rate: %u\n", rate); in sun4i_i2s_set_clk_rate()
370 return -EINVAL; in sun4i_i2s_set_clk_rate()
373 ret = clk_set_rate(i2s->mod_clk, clk_rate); in sun4i_i2s_set_clk_rate()
377 oversample_rate = i2s->mclk_freq / rate; in sun4i_i2s_set_clk_rate()
379 dev_err(dai->dev, "Unsupported oversample rate: %d\n", in sun4i_i2s_set_clk_rate()
381 return -EINVAL; in sun4i_i2s_set_clk_rate()
384 bclk_parent_rate = i2s->variant->get_bclk_parent_rate(i2s); in sun4i_i2s_set_clk_rate()
388 dev_err(dai->dev, "Unsupported BCLK divider: %d\n", bclk_div); in sun4i_i2s_set_clk_rate()
389 return -EINVAL; in sun4i_i2s_set_clk_rate()
392 mclk_div = sun4i_i2s_get_mclk_div(i2s, clk_rate, i2s->mclk_freq); in sun4i_i2s_set_clk_rate()
394 dev_err(dai->dev, "Unsupported MCLK divider: %d\n", mclk_div); in sun4i_i2s_set_clk_rate()
395 return -EINVAL; in sun4i_i2s_set_clk_rate()
398 regmap_write(i2s->regmap, SUN4I_I2S_CLK_DIV_REG, in sun4i_i2s_set_clk_rate()
402 regmap_field_write(i2s->field_clkdiv_mclk_en, 1); in sun4i_i2s_set_clk_rate()
418 return -EINVAL; in sun4i_i2s_get_sr()
434 return -EINVAL; in sun4i_i2s_get_wss()
456 return -EINVAL; in sun8i_i2s_get_sr_wss()
464 regmap_write(i2s->regmap, SUN4I_I2S_TX_CHAN_MAP_REG, 0x76543210); in sun4i_i2s_set_chan_cfg()
465 regmap_write(i2s->regmap, SUN4I_I2S_RX_CHAN_MAP_REG, 0x00003210); in sun4i_i2s_set_chan_cfg()
468 regmap_update_bits(i2s->regmap, SUN4I_I2S_TX_CHAN_SEL_REG, in sun4i_i2s_set_chan_cfg()
471 regmap_update_bits(i2s->regmap, SUN4I_I2S_RX_CHAN_SEL_REG, in sun4i_i2s_set_chan_cfg()
485 regmap_write(i2s->regmap, SUN8I_I2S_TX_CHAN_MAP_REG, 0x76543210); in sun8i_i2s_set_chan_cfg()
486 regmap_write(i2s->regmap, SUN8I_I2S_RX_CHAN_MAP_REG, 0x76543210); in sun8i_i2s_set_chan_cfg()
489 regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG, in sun8i_i2s_set_chan_cfg()
492 regmap_update_bits(i2s->regmap, SUN8I_I2S_RX_CHAN_SEL_REG, in sun8i_i2s_set_chan_cfg()
496 regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG, in sun8i_i2s_set_chan_cfg()
499 regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG, in sun8i_i2s_set_chan_cfg()
503 switch (i2s->format & SND_SOC_DAIFMT_FORMAT_MASK) { in sun8i_i2s_set_chan_cfg()
516 return -EINVAL; in sun8i_i2s_set_chan_cfg()
519 regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG, in sun8i_i2s_set_chan_cfg()
523 regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG, in sun8i_i2s_set_chan_cfg()
537 regmap_write(i2s->regmap, SUN50I_H6_I2S_TX_CHAN_MAP0_REG(0), 0xFEDCBA98); in sun50i_h6_i2s_set_chan_cfg()
538 regmap_write(i2s->regmap, SUN50I_H6_I2S_TX_CHAN_MAP1_REG(0), 0x76543210); in sun50i_h6_i2s_set_chan_cfg()
539 if (i2s->variant->num_din_pins > 1) { in sun50i_h6_i2s_set_chan_cfg()
540 regmap_write(i2s->regmap, SUN50I_R329_I2S_RX_CHAN_MAP0_REG, 0x0F0E0D0C); in sun50i_h6_i2s_set_chan_cfg()
541 regmap_write(i2s->regmap, SUN50I_R329_I2S_RX_CHAN_MAP1_REG, 0x0B0A0908); in sun50i_h6_i2s_set_chan_cfg()
542 regmap_write(i2s->regmap, SUN50I_R329_I2S_RX_CHAN_MAP2_REG, 0x07060504); in sun50i_h6_i2s_set_chan_cfg()
543 regmap_write(i2s->regmap, SUN50I_R329_I2S_RX_CHAN_MAP3_REG, 0x03020100); in sun50i_h6_i2s_set_chan_cfg()
545 regmap_write(i2s->regmap, SUN50I_H6_I2S_RX_CHAN_MAP0_REG, 0xFEDCBA98); in sun50i_h6_i2s_set_chan_cfg()
546 regmap_write(i2s->regmap, SUN50I_H6_I2S_RX_CHAN_MAP1_REG, 0x76543210); in sun50i_h6_i2s_set_chan_cfg()
550 regmap_update_bits(i2s->regmap, SUN50I_H6_I2S_TX_CHAN_SEL_REG(0), in sun50i_h6_i2s_set_chan_cfg()
553 regmap_update_bits(i2s->regmap, SUN50I_H6_I2S_RX_CHAN_SEL_REG, in sun50i_h6_i2s_set_chan_cfg()
557 regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG, in sun50i_h6_i2s_set_chan_cfg()
560 regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG, in sun50i_h6_i2s_set_chan_cfg()
564 switch (i2s->format & SND_SOC_DAIFMT_FORMAT_MASK) { in sun50i_h6_i2s_set_chan_cfg()
577 return -EINVAL; in sun50i_h6_i2s_set_chan_cfg()
580 regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG, in sun50i_h6_i2s_set_chan_cfg()
584 regmap_update_bits(i2s->regmap, SUN50I_H6_I2S_TX_CHAN_SEL_REG(0), in sun50i_h6_i2s_set_chan_cfg()
605 if (i2s->slots) in sun4i_i2s_hw_params()
606 slots = i2s->slots; in sun4i_i2s_hw_params()
608 if (i2s->slot_width) in sun4i_i2s_hw_params()
609 slot_width = i2s->slot_width; in sun4i_i2s_hw_params()
611 ret = i2s->variant->set_chan_cfg(i2s, channels, slots, slot_width); in sun4i_i2s_hw_params()
613 dev_err(dai->dev, "Invalid channel configuration\n"); in sun4i_i2s_hw_params()
618 regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG, in sun4i_i2s_hw_params()
632 dev_err(dai->dev, "Unsupported physical sample width: %d\n", in sun4i_i2s_hw_params()
634 return -EINVAL; in sun4i_i2s_hw_params()
636 i2s->playback_dma_data.addr_width = width; in sun4i_i2s_hw_params()
638 sr = i2s->variant->get_sr(word_size); in sun4i_i2s_hw_params()
640 return -EINVAL; in sun4i_i2s_hw_params()
642 wss = i2s->variant->get_wss(slot_width); in sun4i_i2s_hw_params()
644 return -EINVAL; in sun4i_i2s_hw_params()
646 regmap_field_write(i2s->field_fmt_wss, wss); in sun4i_i2s_hw_params()
647 regmap_field_write(i2s->field_fmt_sr, sr); in sun4i_i2s_hw_params()
677 return -EINVAL; in sun4i_i2s_set_soc_fmt()
680 regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG, in sun4i_i2s_set_soc_fmt()
700 return -EINVAL; in sun4i_i2s_set_soc_fmt()
703 regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG, in sun4i_i2s_set_soc_fmt()
719 return -EINVAL; in sun4i_i2s_set_soc_fmt()
721 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, in sun4i_i2s_set_soc_fmt()
766 return -EINVAL; in sun8i_i2s_set_soc_fmt()
769 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, in sun8i_i2s_set_soc_fmt()
771 regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG, in sun8i_i2s_set_soc_fmt()
774 regmap_update_bits(i2s->regmap, SUN8I_I2S_RX_CHAN_SEL_REG, in sun8i_i2s_set_soc_fmt()
799 return -EINVAL; in sun8i_i2s_set_soc_fmt()
802 regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG, in sun8i_i2s_set_soc_fmt()
820 return -EINVAL; in sun8i_i2s_set_soc_fmt()
823 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, in sun8i_i2s_set_soc_fmt()
828 regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT1_REG, in sun8i_i2s_set_soc_fmt()
874 return -EINVAL; in sun50i_h6_i2s_set_soc_fmt()
877 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, in sun50i_h6_i2s_set_soc_fmt()
879 regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG, in sun50i_h6_i2s_set_soc_fmt()
882 regmap_update_bits(i2s->regmap, SUN50I_H6_I2S_RX_CHAN_SEL_REG, in sun50i_h6_i2s_set_soc_fmt()
907 return -EINVAL; in sun50i_h6_i2s_set_soc_fmt()
910 regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG, in sun50i_h6_i2s_set_soc_fmt()
929 return -EINVAL; in sun50i_h6_i2s_set_soc_fmt()
932 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, in sun50i_h6_i2s_set_soc_fmt()
937 regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT1_REG, in sun50i_h6_i2s_set_soc_fmt()
949 ret = i2s->variant->set_fmt(i2s, fmt); in sun4i_i2s_set_fmt()
951 dev_err(dai->dev, "Unsupported format configuration\n"); in sun4i_i2s_set_fmt()
955 i2s->format = fmt; in sun4i_i2s_set_fmt()
963 regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG, in sun4i_i2s_start_capture()
968 regmap_write(i2s->regmap, SUN4I_I2S_RX_CNT_REG, 0); in sun4i_i2s_start_capture()
971 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, in sun4i_i2s_start_capture()
976 regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG, in sun4i_i2s_start_capture()
984 regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG, in sun4i_i2s_start_playback()
989 regmap_write(i2s->regmap, SUN4I_I2S_TX_CNT_REG, 0); in sun4i_i2s_start_playback()
992 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, in sun4i_i2s_start_playback()
997 regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG, in sun4i_i2s_start_playback()
1005 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, in sun4i_i2s_stop_capture()
1010 regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG, in sun4i_i2s_stop_capture()
1018 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, in sun4i_i2s_stop_playback()
1023 regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG, in sun4i_i2s_stop_playback()
1037 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) in sun4i_i2s_trigger()
1046 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) in sun4i_i2s_trigger()
1053 return -EINVAL; in sun4i_i2s_trigger()
1065 return -EINVAL; in sun4i_i2s_set_sysclk()
1067 i2s->mclk_freq = freq; in sun4i_i2s_set_sysclk()
1079 return -EINVAL; in sun4i_i2s_set_tdm_slot()
1081 i2s->slots = slots; in sun4i_i2s_set_tdm_slot()
1082 i2s->slot_width = slot_width; in sun4i_i2s_set_tdm_slot()
1092 &i2s->playback_dma_data, in sun4i_i2s_dai_probe()
1093 &i2s->capture_dma_data); in sun4i_i2s_dai_probe()
1131 .name = "sun4i-dai",
1288 ret = clk_prepare_enable(i2s->bus_clk); in sun4i_i2s_runtime_resume()
1294 regcache_cache_only(i2s->regmap, false); in sun4i_i2s_runtime_resume()
1295 regcache_mark_dirty(i2s->regmap); in sun4i_i2s_runtime_resume()
1297 ret = regcache_sync(i2s->regmap); in sun4i_i2s_runtime_resume()
1304 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, in sun4i_i2s_runtime_resume()
1308 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, in sun4i_i2s_runtime_resume()
1312 ret = clk_prepare_enable(i2s->mod_clk); in sun4i_i2s_runtime_resume()
1321 clk_disable_unprepare(i2s->bus_clk); in sun4i_i2s_runtime_resume()
1329 clk_disable_unprepare(i2s->mod_clk); in sun4i_i2s_runtime_suspend()
1332 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, in sun4i_i2s_runtime_suspend()
1336 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, in sun4i_i2s_runtime_suspend()
1339 regcache_cache_only(i2s->regmap, true); in sun4i_i2s_runtime_suspend()
1341 clk_disable_unprepare(i2s->bus_clk); in sun4i_i2s_runtime_suspend()
1482 i2s->field_clkdiv_mclk_en = in sun4i_i2s_init_regmap_fields()
1483 devm_regmap_field_alloc(dev, i2s->regmap, in sun4i_i2s_init_regmap_fields()
1484 i2s->variant->field_clkdiv_mclk_en); in sun4i_i2s_init_regmap_fields()
1485 if (IS_ERR(i2s->field_clkdiv_mclk_en)) in sun4i_i2s_init_regmap_fields()
1486 return PTR_ERR(i2s->field_clkdiv_mclk_en); in sun4i_i2s_init_regmap_fields()
1488 i2s->field_fmt_wss = in sun4i_i2s_init_regmap_fields()
1489 devm_regmap_field_alloc(dev, i2s->regmap, in sun4i_i2s_init_regmap_fields()
1490 i2s->variant->field_fmt_wss); in sun4i_i2s_init_regmap_fields()
1491 if (IS_ERR(i2s->field_fmt_wss)) in sun4i_i2s_init_regmap_fields()
1492 return PTR_ERR(i2s->field_fmt_wss); in sun4i_i2s_init_regmap_fields()
1494 i2s->field_fmt_sr = in sun4i_i2s_init_regmap_fields()
1495 devm_regmap_field_alloc(dev, i2s->regmap, in sun4i_i2s_init_regmap_fields()
1496 i2s->variant->field_fmt_sr); in sun4i_i2s_init_regmap_fields()
1497 if (IS_ERR(i2s->field_fmt_sr)) in sun4i_i2s_init_regmap_fields()
1498 return PTR_ERR(i2s->field_fmt_sr); in sun4i_i2s_init_regmap_fields()
1510 i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL); in sun4i_i2s_probe()
1512 return -ENOMEM; in sun4i_i2s_probe()
1523 i2s->variant = of_device_get_match_data(&pdev->dev); in sun4i_i2s_probe()
1524 if (!i2s->variant) { in sun4i_i2s_probe()
1525 dev_err(&pdev->dev, "Failed to determine the quirks to use\n"); in sun4i_i2s_probe()
1526 return -ENODEV; in sun4i_i2s_probe()
1529 i2s->bus_clk = devm_clk_get(&pdev->dev, "apb"); in sun4i_i2s_probe()
1530 if (IS_ERR(i2s->bus_clk)) { in sun4i_i2s_probe()
1531 dev_err(&pdev->dev, "Can't get our bus clock\n"); in sun4i_i2s_probe()
1532 return PTR_ERR(i2s->bus_clk); in sun4i_i2s_probe()
1535 i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs, in sun4i_i2s_probe()
1536 i2s->variant->sun4i_i2s_regmap); in sun4i_i2s_probe()
1537 if (IS_ERR(i2s->regmap)) { in sun4i_i2s_probe()
1538 dev_err(&pdev->dev, "Regmap initialisation failed\n"); in sun4i_i2s_probe()
1539 return PTR_ERR(i2s->regmap); in sun4i_i2s_probe()
1542 i2s->mod_clk = devm_clk_get(&pdev->dev, "mod"); in sun4i_i2s_probe()
1543 if (IS_ERR(i2s->mod_clk)) { in sun4i_i2s_probe()
1544 dev_err(&pdev->dev, "Can't get our mod clock\n"); in sun4i_i2s_probe()
1545 return PTR_ERR(i2s->mod_clk); in sun4i_i2s_probe()
1548 if (i2s->variant->has_reset) { in sun4i_i2s_probe()
1549 i2s->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL); in sun4i_i2s_probe()
1550 if (IS_ERR(i2s->rst)) { in sun4i_i2s_probe()
1551 dev_err(&pdev->dev, "Failed to get reset control\n"); in sun4i_i2s_probe()
1552 return PTR_ERR(i2s->rst); in sun4i_i2s_probe()
1556 if (!IS_ERR(i2s->rst)) { in sun4i_i2s_probe()
1557 ret = reset_control_deassert(i2s->rst); in sun4i_i2s_probe()
1559 dev_err(&pdev->dev, in sun4i_i2s_probe()
1561 return -EINVAL; in sun4i_i2s_probe()
1565 i2s->playback_dma_data.addr = res->start + in sun4i_i2s_probe()
1566 i2s->variant->reg_offset_txdata; in sun4i_i2s_probe()
1567 i2s->playback_dma_data.maxburst = 8; in sun4i_i2s_probe()
1569 i2s->capture_dma_data.addr = res->start + SUN4I_I2S_FIFO_RX_REG; in sun4i_i2s_probe()
1570 i2s->capture_dma_data.maxburst = 8; in sun4i_i2s_probe()
1572 pm_runtime_enable(&pdev->dev); in sun4i_i2s_probe()
1573 if (!pm_runtime_enabled(&pdev->dev)) { in sun4i_i2s_probe()
1574 ret = sun4i_i2s_runtime_resume(&pdev->dev); in sun4i_i2s_probe()
1579 ret = sun4i_i2s_init_regmap_fields(&pdev->dev, i2s); in sun4i_i2s_probe()
1581 dev_err(&pdev->dev, "Could not initialise regmap fields\n"); in sun4i_i2s_probe()
1585 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); in sun4i_i2s_probe()
1587 dev_err(&pdev->dev, "Could not register PCM\n"); in sun4i_i2s_probe()
1591 ret = devm_snd_soc_register_component(&pdev->dev, in sun4i_i2s_probe()
1595 dev_err(&pdev->dev, "Could not register DAI\n"); in sun4i_i2s_probe()
1602 if (!pm_runtime_status_suspended(&pdev->dev)) in sun4i_i2s_probe()
1603 sun4i_i2s_runtime_suspend(&pdev->dev); in sun4i_i2s_probe()
1605 pm_runtime_disable(&pdev->dev); in sun4i_i2s_probe()
1606 if (!IS_ERR(i2s->rst)) in sun4i_i2s_probe()
1607 reset_control_assert(i2s->rst); in sun4i_i2s_probe()
1614 struct sun4i_i2s *i2s = dev_get_drvdata(&pdev->dev); in sun4i_i2s_remove()
1616 pm_runtime_disable(&pdev->dev); in sun4i_i2s_remove()
1617 if (!pm_runtime_status_suspended(&pdev->dev)) in sun4i_i2s_remove()
1618 sun4i_i2s_runtime_suspend(&pdev->dev); in sun4i_i2s_remove()
1620 if (!IS_ERR(i2s->rst)) in sun4i_i2s_remove()
1621 reset_control_assert(i2s->rst); in sun4i_i2s_remove()
1626 .compatible = "allwinner,sun4i-a10-i2s",
1630 .compatible = "allwinner,sun6i-a31-i2s",
1634 .compatible = "allwinner,sun8i-a83t-i2s",
1638 .compatible = "allwinner,sun8i-h3-i2s",
1642 .compatible = "allwinner,sun50i-a64-codec-i2s",
1646 .compatible = "allwinner,sun50i-h6-i2s",
1650 .compatible = "allwinner,sun50i-r329-i2s",
1666 .name = "sun4i-i2s",
1674 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");