1a92fb944SMarco Felsch# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2a92fb944SMarco Felsch%YAML 1.2 3a92fb944SMarco Felsch--- 4a92fb944SMarco Felsch$id: http://devicetree.org/schemas/media/i2c/toshiba,tc358746.yaml# 5a92fb944SMarco Felsch$schema: http://devicetree.org/meta-schemas/core.yaml# 6a92fb944SMarco Felsch 7a92fb944SMarco Felschtitle: Toshiba TC358746 Parallel to MIPI CSI2 Bridge 8a92fb944SMarco Felsch 9a92fb944SMarco Felschmaintainers: 10a92fb944SMarco Felsch - Marco Felsch <kernel@pengutronix.de> 11a92fb944SMarco Felsch 12a92fb944SMarco Felschdescription: |- 13a92fb944SMarco Felsch The Toshiba TC358746 converts a parallel video stream into a MIPI CSI-2 14a92fb944SMarco Felsch stream. The direction can be either parallel-in -> csi-out or csi-in -> 1547aab533SBjorn Helgaas parallel-out The chip is programmable through I2C and SPI but the SPI 16a92fb944SMarco Felsch interface is only supported in parallel-in -> csi-out mode. 17a92fb944SMarco Felsch 18a92fb944SMarco Felsch Note that the current device tree bindings only support the 19a92fb944SMarco Felsch parallel-in -> csi-out path. 20a92fb944SMarco Felsch 21a92fb944SMarco Felschproperties: 22a92fb944SMarco Felsch compatible: 23a92fb944SMarco Felsch const: toshiba,tc358746 24a92fb944SMarco Felsch 25a92fb944SMarco Felsch reg: 26a92fb944SMarco Felsch maxItems: 1 27a92fb944SMarco Felsch 28a92fb944SMarco Felsch clocks: 29a92fb944SMarco Felsch description: 30a92fb944SMarco Felsch The phandle to the reference clock source. This corresponds to the 31a92fb944SMarco Felsch hardware pin REFCLK. 32a92fb944SMarco Felsch maxItems: 1 33a92fb944SMarco Felsch 34a92fb944SMarco Felsch clock-names: 35a92fb944SMarco Felsch const: refclk 36a92fb944SMarco Felsch 37a92fb944SMarco Felsch "#clock-cells": 38a92fb944SMarco Felsch description: | 39a92fb944SMarco Felsch The bridge can act as clock provider for the sensor. To enable this 40a92fb944SMarco Felsch support #clock-cells must be specified. Attention if this feature is used 41a92fb944SMarco Felsch then the mclk rate must be at least: (2 * link-frequency) / 8 42a92fb944SMarco Felsch `------------------´ ^ 43a92fb944SMarco Felsch internal PLL rate smallest possible 44a92fb944SMarco Felsch mclk-div 45a92fb944SMarco Felsch const: 0 46a92fb944SMarco Felsch 47a92fb944SMarco Felsch clock-output-names: 48a92fb944SMarco Felsch description: 49a92fb944SMarco Felsch The clock name of the MCLK output, the default name is tc358746-mclk. 50a92fb944SMarco Felsch maxItems: 1 51a92fb944SMarco Felsch 52a92fb944SMarco Felsch vddc-supply: 53a92fb944SMarco Felsch description: Digital core voltage supply, 1.2 volts 54a92fb944SMarco Felsch 55a92fb944SMarco Felsch vddio-supply: 56a92fb944SMarco Felsch description: Digital I/O voltage supply, 1.8 volts 57a92fb944SMarco Felsch 58a92fb944SMarco Felsch vddmipi-supply: 59a92fb944SMarco Felsch description: MIPI CSI phy voltage supply, 1.2 volts 60a92fb944SMarco Felsch 61a92fb944SMarco Felsch reset-gpios: 62a92fb944SMarco Felsch description: 63a92fb944SMarco Felsch The phandle and specifier for the GPIO that controls the chip reset. 64a92fb944SMarco Felsch This corresponds to the hardware pin RESX which is physically active low. 65a92fb944SMarco Felsch maxItems: 1 66a92fb944SMarco Felsch 67a92fb944SMarco Felsch ports: 68a92fb944SMarco Felsch $ref: /schemas/graph.yaml#/properties/ports 69a92fb944SMarco Felsch properties: 70a92fb944SMarco Felsch port@0: 71a92fb944SMarco Felsch $ref: /schemas/graph.yaml#/$defs/port-base 72*a47f580cSRob Herring unevaluatedProperties: false 73a92fb944SMarco Felsch description: Input port 74a92fb944SMarco Felsch 75a92fb944SMarco Felsch properties: 76a92fb944SMarco Felsch endpoint: 77a92fb944SMarco Felsch $ref: /schemas/media/video-interfaces.yaml# 78a92fb944SMarco Felsch unevaluatedProperties: false 79a92fb944SMarco Felsch 80a92fb944SMarco Felsch properties: 81a92fb944SMarco Felsch hsync-active: true 82a92fb944SMarco Felsch vsync-active: true 83a92fb944SMarco Felsch bus-type: 84a92fb944SMarco Felsch enum: [ 5, 6 ] 85a92fb944SMarco Felsch 86a92fb944SMarco Felsch required: 87a92fb944SMarco Felsch - hsync-active 88a92fb944SMarco Felsch - vsync-active 89a92fb944SMarco Felsch - bus-type 90a92fb944SMarco Felsch 91a92fb944SMarco Felsch port@1: 92a92fb944SMarco Felsch $ref: /schemas/graph.yaml#/$defs/port-base 93*a47f580cSRob Herring unevaluatedProperties: false 94a92fb944SMarco Felsch description: Output port 95a92fb944SMarco Felsch 96a92fb944SMarco Felsch properties: 97a92fb944SMarco Felsch endpoint: 98a92fb944SMarco Felsch $ref: /schemas/media/video-interfaces.yaml# 99a92fb944SMarco Felsch unevaluatedProperties: false 100a92fb944SMarco Felsch 101a92fb944SMarco Felsch properties: 102a92fb944SMarco Felsch data-lanes: 103a92fb944SMarco Felsch minItems: 1 104a92fb944SMarco Felsch maxItems: 4 105a92fb944SMarco Felsch 106a92fb944SMarco Felsch clock-noncontinuous: true 107a92fb944SMarco Felsch link-frequencies: true 108a92fb944SMarco Felsch 109a92fb944SMarco Felsch required: 110a92fb944SMarco Felsch - data-lanes 111a92fb944SMarco Felsch - link-frequencies 112a92fb944SMarco Felsch 113a92fb944SMarco Felsch required: 114a92fb944SMarco Felsch - port@0 115a92fb944SMarco Felsch - port@1 116a92fb944SMarco Felsch 117a92fb944SMarco Felschrequired: 118a92fb944SMarco Felsch - compatible 119a92fb944SMarco Felsch - reg 120a92fb944SMarco Felsch - clocks 121a92fb944SMarco Felsch - clock-names 122a92fb944SMarco Felsch - vddc-supply 123a92fb944SMarco Felsch - vddio-supply 124a92fb944SMarco Felsch - vddmipi-supply 125a92fb944SMarco Felsch - ports 126a92fb944SMarco Felsch 127a92fb944SMarco FelschadditionalProperties: false 128a92fb944SMarco Felsch 129a92fb944SMarco Felschexamples: 130a92fb944SMarco Felsch - | 131a92fb944SMarco Felsch #include <dt-bindings/gpio/gpio.h> 132a92fb944SMarco Felsch 133a92fb944SMarco Felsch i2c { 134a92fb944SMarco Felsch #address-cells = <1>; 135a92fb944SMarco Felsch #size-cells = <0>; 136a92fb944SMarco Felsch 137a92fb944SMarco Felsch csi-bridge@e { 138a92fb944SMarco Felsch compatible = "toshiba,tc358746"; 139a92fb944SMarco Felsch reg = <0xe>; 140a92fb944SMarco Felsch 141a92fb944SMarco Felsch clocks = <&refclk>; 142a92fb944SMarco Felsch clock-names = "refclk"; 143a92fb944SMarco Felsch 144a92fb944SMarco Felsch reset-gpios = <&gpio 2 GPIO_ACTIVE_LOW>; 145a92fb944SMarco Felsch 146a92fb944SMarco Felsch vddc-supply = <&v1_2d>; 147a92fb944SMarco Felsch vddio-supply = <&v1_8d>; 148a92fb944SMarco Felsch vddmipi-supply = <&v1_2d>; 149a92fb944SMarco Felsch 150a92fb944SMarco Felsch /* sensor mclk provider */ 151a92fb944SMarco Felsch #clock-cells = <0>; 152a92fb944SMarco Felsch 153a92fb944SMarco Felsch ports { 154a92fb944SMarco Felsch #address-cells = <1>; 155a92fb944SMarco Felsch #size-cells = <0>; 156a92fb944SMarco Felsch 157a92fb944SMarco Felsch /* Input */ 158a92fb944SMarco Felsch port@0 { 159a92fb944SMarco Felsch reg = <0>; 160a92fb944SMarco Felsch tc358746_in: endpoint { 161a92fb944SMarco Felsch remote-endpoint = <&sensor_out>; 162a92fb944SMarco Felsch hsync-active = <0>; 163a92fb944SMarco Felsch vsync-active = <0>; 164a92fb944SMarco Felsch bus-type = <5>; 165a92fb944SMarco Felsch }; 166a92fb944SMarco Felsch }; 167a92fb944SMarco Felsch 168a92fb944SMarco Felsch /* Output */ 169a92fb944SMarco Felsch port@1 { 170a92fb944SMarco Felsch reg = <1>; 171a92fb944SMarco Felsch tc358746_out: endpoint { 172a92fb944SMarco Felsch remote-endpoint = <&mipi_csi2_in>; 173a92fb944SMarco Felsch data-lanes = <1 2>; 174a92fb944SMarco Felsch clock-noncontinuous; 175a92fb944SMarco Felsch link-frequencies = /bits/ 64 <216000000>; 176a92fb944SMarco Felsch }; 177a92fb944SMarco Felsch }; 178a92fb944SMarco Felsch }; 179a92fb944SMarco Felsch }; 180a92fb944SMarco Felsch }; 181