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/openbmc/linux/arch/arm/mach-omap1/
H A Dams-delta-fiq.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Amstrad E3 FIQ handling
10 * Parts of this code are taken from linux/arch/arm/mach-omap/irq.c
20 #include <linux/platform_data/ams-delta-fiq.h>
23 #include <asm/fiq.h>
24 #include <linux/soc/ti/omap1-io.h>
27 #include "ams-delta-fiq.h"
28 #include "board-ams-delta.h"
31 .name = "ams-delta-fiq"
35 * This buffer is shared between FIQ and IRQ contexts.
[all …]
H A Dboard-ams-delta.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-omap1/board-ams-delta.c
5 * Modified from board-generic.c
19 #include <linux/mtd/nand-gpio.h>
29 #include <linux/platform_data/gpio-omap.h>
30 #include <linux/soc/ti/omap1-mux.h>
33 #include <asm/mach-types.h>
37 #include <linux/platform_data/keypad-omap.h>
41 #include "ams-delta-fiq.h"
42 #include "board-ams-delta.h"
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/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dapple,aic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/apple,aic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hector Martin <marcan@marcan.st>
19 - Level-triggered hardware IRQs wired to SoC blocks
20 - Single mask bit per IRQ
21 - Per-IRQ affinity setting
22 - Automatic masking on event delivery (auto-ack)
23 - Software triggering (ORed with hw line)
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H A Dapple,aic2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/apple,aic2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hector Martin <marcan@marcan.st>
18 - Level-triggered hardware IRQs wired to SoC blocks
19 - Single mask bit per IRQ
20 - Automatic masking on event delivery (auto-ack)
21 - Software triggering (ORed with hw line)
22 - Automatic prioritization (single event/ack register per CPU, lower IRQs =
[all …]
H A Dst,stih407-irq-syscfg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/st,stih407-irq-syscfg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Patrice Chotard <patrice.chotard@foss.st.com>
15 Configuration registers. This device is used to unmask them prior to use.
19 const: st,stih407-irq-syscfg
22 description: Phandle to Cortex-A9 IRQ system config registers
25 st,irq-device:
27 $ref: /schemas/types.yaml#/definitions/uint32-array
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/openbmc/linux/drivers/irqchip/
H A Dirq-st.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * This is a re-write of Christophe Kerello's PMU driver.
10 #include <dt-bindings/interrupt-controller/irq-st.h>
45 .compatible = "st,stih407-irq-syscfg",
52 int device, int channel, bool irq) in st_irq_xlate() argument
54 struct st_irq_syscfg *ddata = dev_get_drvdata(&pdev->dev); in st_irq_xlate()
56 /* Set the device enable bit. */ in st_irq_xlate()
57 switch (device) { in st_irq_xlate()
59 ddata->config |= ST_A9_IRQ_EN_EXT_0; in st_irq_xlate()
62 ddata->config |= ST_A9_IRQ_EN_EXT_1; in st_irq_xlate()
[all …]
H A Dirq-ixp4xx.c1 // SPDX-License-Identifier: GPL-2.0
6 * Based on arch/arm/mach-ixp4xx/common.c
8 * Copyright 2003-2004 (C) MontaVista, Software, Inc.
28 #define IXP4XX_ICLR 0x08 /* Interrupt IRQ/FIQ Select */
30 #define IXP4XX_ICFP 0x10 /* FIQ Status */
33 #define IXP4XX_ICFH 0x1C /* FIQ Highest Pri Int */
35 /* IXP43x and IXP46x-only */
38 #define IXP4XX_ICLR2 0x28 /* Interrupt IRQ/FIQ Select 2 */
40 #define IXP4XX_ICFP2 0x30 /* FIQ Status */
44 * struct ixp4xx_irq - state container for the Faraday IRQ controller
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H A Dirq-apple-aic.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Based on irq-lpc32xx:
6 * Copyright 2015-2016 Vladimir Zapolskiy <vz@mleia.com>
7 * Based on irq-bcm2836:
14 * - 896 level-triggered hardware IRQs
15 * - Single mask bit per IRQ
16 * - Per-IRQ affinity setting
17 * - Automatic masking on event delivery (auto-ack)
18 * - Software triggering (ORed with hw line)
19 * - 2 per-CPU IPIs (meant as "self" and "other", but they are
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/openbmc/linux/fs/fuse/
H A Ddev.c3 Copyright (C) 2001-2008 Miklos Szeredi <miklos@szeredi.hu>
37 * Lockless access is OK, because file->private data is set in fuse_get_dev()
40 return READ_ONCE(file->private_data); in fuse_get_dev()
45 INIT_LIST_HEAD(&req->list); in fuse_request_init()
46 INIT_LIST_HEAD(&req->intr_entry); in fuse_request_init()
47 init_waitqueue_head(&req->waitq); in fuse_request_init()
48 refcount_set(&req->count, 1); in fuse_request_init()
49 __set_bit(FR_PENDING, &req->flags); in fuse_request_init()
50 req->fm = fm; in fuse_request_init()
69 refcount_inc(&req->count); in __fuse_get_request()
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H A Dvirtio_fs.c1 // SPDX-License-Identifier: GPL-2.0
3 * virtio-fs: Virtio Filesystem
28 /* List of virtio-fs device instances and a lock for the list. Also provides
29 * mutual exclusion in device removal and mounting path
41 /* Per-virtqueue state */
44 struct virtqueue *vq; /* protected by ->lock */
56 /* A virtio-fs device instance */
114 struct fuse_fs_context *ctx = fsc->fs_private; in virtio_fs_parse_param()
123 ctx->dax_mode = FUSE_DAX_ALWAYS; in virtio_fs_parse_param()
126 ctx->dax_mode = result.uint_32; in virtio_fs_parse_param()
[all …]
H A Dfuse_i.h3 Copyright (C) 2001-2008 Miklos Szeredi <miklos@szeredi.hu>
23 #include <linux/backing-dev.h>
41 /** Bias for fi->writectr, meaning new writepages must not be sent */
100 /** The sticky bit in inode->i_mode may have been removed, so
116 /* Files usable in writepage. Protected by fi->lock */
241 /** RB node to be linked on fuse_conn->polled_files */
359 * - FR_ABORTED
360 * - FR_LOCKED (may also be modified under fc->lock, tested under both)
393 /** virtio-fs's physically contiguous buffer for in and out args */
406 * Input queue signalling is device-specific. For example, the /dev/fuse file
[all …]
H A Dinode.c3 Copyright (C) 2001-2008 Miklos Szeredi <miklos@szeredi.hu>
78 sl->forget = fuse_alloc_forget(); in fuse_alloc_submount_lookup()
79 if (!sl->forget) in fuse_alloc_submount_lookup()
97 fi->i_time = 0; in fuse_alloc_inode()
98 fi->inval_mask = ~0; in fuse_alloc_inode()
99 fi->nodeid = 0; in fuse_alloc_inode()
100 fi->nlookup = 0; in fuse_alloc_inode()
101 fi->attr_version = 0; in fuse_alloc_inode()
102 fi->orig_ino = 0; in fuse_alloc_inode()
103 fi->state = 0; in fuse_alloc_inode()
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/openbmc/linux/arch/arm/include/asm/
H A Decard.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 * 11-12-1996 RMK Further minor improvements
11 * 12-09-1997 RMK Added interrupt enable/disable for card level
104 unsigned char fiqmask; /* FIQ mask */
106 unsigned long fiqoff; /* FIQ offset */
130 #define ecard_resource_start(ec,nr) ((ec)->resource[nr].start)
131 #define ecard_resource_end(ec,nr) ((ec)->resource[nr].end)
132 #define ecard_resource_len(ec,nr) ((ec)->resource[nr].end - \
133 (ec)->resource[nr].start + 1)
134 #define ecard_resource_flags(ec,nr) ((ec)->resource[nr].flags)
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/openbmc/qemu/hw/arm/
H A Dbcm2836.c9 * See the COPYING file in the top-level directory.
18 #include "target/arm/cpu-qom.h"
22 DEFINE_PROP_UINT32("enabled-cpus", BCM283XBaseState, enabled_cpus, 0);
30 for (n = 0; n < bc->core_count; n++) { in bcm283x_base_init()
31 object_initialize_child(obj, "cpu[*]", &s->cpu[n].core, in bcm283x_base_init()
32 bc->cpu_type); in bcm283x_base_init()
34 if (bc->core_count > 1) { in bcm283x_base_init()
35 qdev_property_add_static(DEVICE(obj), &bcm2836_enabled_cores_property); in bcm283x_base_init()
36 qdev_prop_set_uint32(DEVICE(obj), "enabled-cpus", bc->core_count); in bcm283x_base_init()
39 if (bc->ctrl_base) { in bcm283x_base_init()
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/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dfsl,ssi.txt3 The SSI is a serial device that communicates with audio codecs. It can
4 be programmed in AC97, I2S, left-justified, or right-justified modes.
7 - compatible: Compatible list, should contain one of the following
9 fsl,mpc8610-ssi
10 fsl,imx51-ssi
11 fsl,imx35-ssi
12 fsl,imx21-ssi
13 - cell-index: The SSI, <0> = SSI1, <1> = SSI2, and so on.
14 - reg: Offset and length of the register set for the device.
15 - interrupts: <a b> where a is the interrupt number and b is a
[all …]
/openbmc/linux/arch/arm/mach-rpc/
H A Ddma.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-rpc/dma.c
12 #include <linux/dma-mapping.h>
17 #include <asm/fiq.h>
48 #define ENDA (IOMD_IO0ENDA - IOMD_IO0CURA)
49 #define CURB (IOMD_IO0CURB - IOMD_IO0CURA)
50 #define ENDB (IOMD_IO0ENDB - IOMD_IO0CURA)
51 #define CR (IOMD_IO0CR - IOMD_IO0CURA)
52 #define ST (IOMD_IO0ST - IOMD_IO0CURA)
58 if (idma->dma.sg) { in iomd_get_next_sg()
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/openbmc/qemu/hw/intc/
H A Domap_intc.c4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
5 * Copyright (C) 2007-2008 Nokia Corporation
23 #include "hw/qdev-properties.h"
26 #include "qemu/error-report.h"
35 uint32_t fiq; member
71 * IRQ_N-1,...,IRQ_0. */ in omap_inth_sir_update()
72 for (j = 0; j < s->nbanks; ++j) { in omap_inth_sir_update()
73 level = s->bank[j].irqs & ~s->bank[j].mask & in omap_inth_sir_update()
74 (is_fiq ? s->bank[j].fiq : ~s->bank[j].fiq); in omap_inth_sir_update()
78 p = s->bank[j].priority[i]; in omap_inth_sir_update()
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H A Dallwinner-a10-pic.c2 * Allwinner A10 interrupt controller device emulation
21 #include "hw/intc/allwinner-a10-pic.h"
29 int irq = 0, fiq = 0, zeroes; in aw_a10_pic_update() local
31 s->vector = 0; in aw_a10_pic_update()
34 irq |= s->irq_pending[i] & ~s->mask[i]; in aw_a10_pic_update()
35 fiq |= s->select[i] & s->irq_pending[i] & ~s->mask[i]; in aw_a10_pic_update()
37 if (!s->vector) { in aw_a10_pic_update()
38 zeroes = ctz32(s->irq_pending[i] & ~s->mask[i]); in aw_a10_pic_update()
40 s->vector = (i * 32 + zeroes) * 4; in aw_a10_pic_update()
45 qemu_set_irq(s->parent_irq, !!irq); in aw_a10_pic_update()
[all …]
H A Dbcm2836_control.c17 * See the COPYING file in the top-level directory.
67 /* deliver a FIQ */ in deliver_local()
68 s->fiqsrc[core] |= (uint32_t)1 << irq; in deliver_local()
71 s->irqsrc[core] |= (uint32_t)1 << irq; in deliver_local()
84 s->irqsrc[i] = s->fiqsrc[i] = 0; in bcm2836_control_update()
88 if (s->gpu_irq) { in bcm2836_control_update()
89 assert(s->route_gpu_irq < BCM2836_NCORES); in bcm2836_control_update()
90 s->irqsrc[s->route_gpu_irq] |= (uint32_t)1 << IRQ_GPU; in bcm2836_control_update()
93 if (s->gpu_fiq) { in bcm2836_control_update()
94 assert(s->route_gpu_fiq < BCM2836_NCORES); in bcm2836_control_update()
[all …]
H A Dbcm2835_ic.c12 * See the COPYING file in the top-level directory.
29 #define FIQ_CONTROL 0x0C /* FIQ register */
42 if (s->fiq_enable) { in bcm2835_ic_update()
43 if (s->fiq_select >= GPU_IRQS) { in bcm2835_ic_update()
45 set = extract32(s->arm_irq_level, s->fiq_select - GPU_IRQS, 1); in bcm2835_ic_update()
47 set = extract64(s->gpu_irq_level, s->fiq_select, 1); in bcm2835_ic_update()
50 qemu_set_irq(s->fiq, set); in bcm2835_ic_update()
52 set = (s->gpu_irq_level & s->gpu_irq_enable) in bcm2835_ic_update()
53 || (s->arm_irq_level & s->arm_irq_enable); in bcm2835_ic_update()
54 qemu_set_irq(s->irq, set); in bcm2835_ic_update()
[all …]
H A Daspeed_vic.c9 * the COPYING file in the top-level directory.
17 * registers for each conceptual register. The device model's implementation
27 * read-modify-write sequence).
47 uint64_t new = (s->raw & s->enable); in aspeed_vic_update()
50 flags = new & s->select; in aspeed_vic_update()
52 qemu_set_irq(s->fiq, !!flags); in aspeed_vic_update()
54 flags = new & ~s->select; in aspeed_vic_update()
56 qemu_set_irq(s->irq, !!flags); in aspeed_vic_update()
74 if (s->sense & irq_mask) { in aspeed_vic_set_irq()
75 /* level-triggered */ in aspeed_vic_set_irq()
[all …]
H A Dpl190.c44 qemu_irq fiq; member
52 return (s->level | s->soft_level) & s->irq_enable & ~s->fiq_select; in pl190_irq_level()
61 set = (level & s->prio_mask[s->priority]) != 0; in pl190_update()
62 qemu_set_irq(s->irq, set); in pl190_update()
63 set = ((s->level | s->soft_level) & s->fiq_select) != 0; in pl190_update()
64 qemu_set_irq(s->fiq, set); in pl190_update()
72 s->level |= 1u << irq; in pl190_set_irq()
74 s->level &= ~(1u << irq); in pl190_set_irq()
87 s->prio_mask[i] = mask; in pl190_update_vectors()
88 if (s->vect_control[i] & 0x20) in pl190_update_vectors()
[all …]
/openbmc/linux/arch/arm64/kernel/
H A Dentry.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Low-level exception handling code
10 #include <linux/arm-smccc.h>
16 #include <asm/asm-offsets.h>
29 #include <asm/asm-uaccess.h>
64 sub x0, sp, x0 // x0' = sp' - x0 = (sp + x0) - x0 = sp
66 sub x0, sp, x0 // x0'' = sp' - x0' = (sp + x0) - sp = x0
67 sub sp, sp, x0 // sp'' = sp' - x0 = (sp + x0) - x0 = sp
89 * after panic() re-enables interrupts.
93 tst x0, #~(OVERFLOW_STACK_SIZE - 1) // within range?
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/openbmc/linux/sound/soc/fsl/
H A Dimx-pcm-fiq.c1 // SPDX-License-Identifier: GPL-2.0+
2 // imx-pcm-fiq.c -- ALSA Soc Audio Layer
11 #include <linux/device.h>
12 #include <linux/dma-mapping.h>
26 #include <asm/fiq.h>
28 #include <linux/platform_data/asoc-imx-ssi.h>
30 #include "imx-ssi.h"
31 #include "imx-pcm.h"
48 struct snd_pcm_substream *substream = iprtd->substream; in snd_hrtimer_callback()
51 if (!atomic_read(&iprtd->playing) && !atomic_read(&iprtd->capturing)) in snd_hrtimer_callback()
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H A Dfsl_ssi.c1 // SPDX-License-Identifier: GPL-2.0
7 // Copyright 2007-2010 Freescale Semiconductor, Inc.
9 // Some notes why imx-pcm-fiq is used instead of DMA on some boards:
16 // we receive in our (PCM-) data stream. The only chance we have is to
17 // manually skip this data in the FIQ handler. With sampling rates different
19 // between pcm data and GPIO status data changes. Our FIQ handler is not
34 #include <linux/device.h>
43 #include <linux/dma/imx-dma.h>
53 #include "imx-pcm.h"
55 /* Define RX and TX to index ssi->regvals array; Can be 0 or 1 only */
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