Lines Matching +full:fiq +full:- +full:device
17 * See the COPYING file in the top-level directory.
67 /* deliver a FIQ */ in deliver_local()
68 s->fiqsrc[core] |= (uint32_t)1 << irq; in deliver_local()
71 s->irqsrc[core] |= (uint32_t)1 << irq; in deliver_local()
84 s->irqsrc[i] = s->fiqsrc[i] = 0; in bcm2836_control_update()
88 if (s->gpu_irq) { in bcm2836_control_update()
89 assert(s->route_gpu_irq < BCM2836_NCORES); in bcm2836_control_update()
90 s->irqsrc[s->route_gpu_irq] |= (uint32_t)1 << IRQ_GPU; in bcm2836_control_update()
93 if (s->gpu_fiq) { in bcm2836_control_update()
94 assert(s->route_gpu_fiq < BCM2836_NCORES); in bcm2836_control_update()
95 s->fiqsrc[s->route_gpu_fiq] |= (uint32_t)1 << IRQ_GPU; in bcm2836_control_update()
100 * cores' IRQ/FIQ; this is distinct from the per-CPU timer in bcm2836_control_update()
103 if ((s->local_timer_control & LOCALTIMER_INTENABLE) && in bcm2836_control_update()
104 (s->local_timer_control & LOCALTIMER_INTFLAG)) { in bcm2836_control_update()
105 if (s->route_localtimer & 4) { in bcm2836_control_update()
106 s->fiqsrc[(s->route_localtimer & 3)] |= (uint32_t)1 << IRQ_TIMER; in bcm2836_control_update()
108 s->irqsrc[(s->route_localtimer & 3)] |= (uint32_t)1 << IRQ_TIMER; in bcm2836_control_update()
114 if (s->timerirqs[i]) { in bcm2836_control_update()
115 assert(s->timerirqs[i] < (1 << (IRQ_CNTVIRQ + 1))); /* sane mask? */ in bcm2836_control_update()
117 if ((s->timerirqs[i] & (1 << j)) != 0) { in bcm2836_control_update()
119 deliver_local(s, i, j, s->timercontrol[i], j); in bcm2836_control_update()
126 if (s->mailboxes[i * BCM2836_MBPERCORE + j] != 0) { in bcm2836_control_update()
128 deliver_local(s, i, j + IRQ_MAILBOX0, s->mailboxcontrol[i], j); in bcm2836_control_update()
135 qemu_set_irq(s->irq[i], s->irqsrc[i] != 0); in bcm2836_control_update()
136 qemu_set_irq(s->fiq[i], s->fiqsrc[i] != 0); in bcm2836_control_update()
148 s->timerirqs[core] = deposit32(s->timerirqs[core], local_irq, 1, !!level); in bcm2836_control_set_local_irq()
182 s->gpu_irq = level; in bcm2836_control_set_gpu_irq()
191 s->gpu_fiq = level; in bcm2836_control_set_gpu_fiq()
201 assert(LOCALTIMER_VALUE(s->local_timer_control) > 0); in bcm2836_control_local_timer_set_next()
204 muldiv64(LOCALTIMER_VALUE(s->local_timer_control), in bcm2836_control_local_timer_set_next()
206 timer_mod(&s->timer, next_event); in bcm2836_control_local_timer_set_next()
215 s->local_timer_control |= LOCALTIMER_INTFLAG; in bcm2836_control_local_timer_tick()
223 s->local_timer_control = val; in bcm2836_control_local_timer_control()
227 timer_del(&s->timer); in bcm2836_control_local_timer_control()
236 s->local_timer_control &= ~LOCALTIMER_INTFLAG; in bcm2836_control_local_timer_ack()
239 (s->local_timer_control & LOCALTIMER_ENABLE)) { in bcm2836_control_local_timer_ack()
249 assert(s->route_gpu_fiq < BCM2836_NCORES in bcm2836_control_read()
250 && s->route_gpu_irq < BCM2836_NCORES); in bcm2836_control_read()
251 return ((uint32_t)s->route_gpu_fiq << 2) | s->route_gpu_irq; in bcm2836_control_read()
253 return s->route_localtimer; in bcm2836_control_read()
255 return s->local_timer_control; in bcm2836_control_read()
259 return s->timercontrol[(offset - REG_TIMERCONTROL) >> 2]; in bcm2836_control_read()
261 return s->mailboxcontrol[(offset - REG_MBOXCONTROL) >> 2]; in bcm2836_control_read()
263 return s->irqsrc[(offset - REG_IRQSRC) >> 2]; in bcm2836_control_read()
265 return s->fiqsrc[(offset - REG_FIQSRC) >> 2]; in bcm2836_control_read()
267 return s->mailboxes[(offset - REG_MBOX0_RDCLR) >> 2]; in bcm2836_control_read()
281 s->route_gpu_irq = val & 0x3; in bcm2836_control_write()
282 s->route_gpu_fiq = (val >> 2) & 0x3; in bcm2836_control_write()
284 s->route_localtimer = val & 7; in bcm2836_control_write()
290 s->timercontrol[(offset - REG_TIMERCONTROL) >> 2] = val & 0xff; in bcm2836_control_write()
292 s->mailboxcontrol[(offset - REG_MBOXCONTROL) >> 2] = val & 0xff; in bcm2836_control_write()
294 s->mailboxes[(offset - REG_MBOX0_WR) >> 2] |= val; in bcm2836_control_write()
296 s->mailboxes[(offset - REG_MBOX0_RDCLR) >> 2] &= ~val; in bcm2836_control_write()
320 s->route_gpu_irq = s->route_gpu_fiq = 0; in bcm2836_control_reset()
322 timer_del(&s->timer); in bcm2836_control_reset()
323 s->route_localtimer = 0; in bcm2836_control_reset()
324 s->local_timer_control = 0; in bcm2836_control_reset()
327 s->timercontrol[i] = 0; in bcm2836_control_reset()
328 s->mailboxcontrol[i] = 0; in bcm2836_control_reset()
332 s->mailboxes[i] = 0; in bcm2836_control_reset()
339 DeviceState *dev = DEVICE(obj); in bcm2836_control_init()
341 memory_region_init_io(&s->iomem, obj, &bcm2836_control_ops, s, in bcm2836_control_init()
343 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); in bcm2836_control_init()
355 /* IRQ and FIQ inputs from upstream bcm2835 controller */ in bcm2836_control_init()
356 qdev_init_gpio_in_named(dev, bcm2836_control_set_gpu_irq, "gpu-irq", 1); in bcm2836_control_init()
357 qdev_init_gpio_in_named(dev, bcm2836_control_set_gpu_fiq, "gpu-fiq", 1); in bcm2836_control_init()
360 qdev_init_gpio_out_named(dev, s->irq, "irq", BCM2836_NCORES); in bcm2836_control_init()
361 qdev_init_gpio_out_named(dev, s->fiq, "fiq", BCM2836_NCORES); in bcm2836_control_init()
364 timer_init_ns(&s->timer, QEMU_CLOCK_VIRTUAL, in bcm2836_control_init()
392 dc->vmsd = &vmstate_bcm2836_control; in bcm2836_control_class_init()