12  * See the COPYING file in the top-level directory.
29 #define FIQ_CONTROL             0x0C /* FIQ register */
42     if (s->fiq_enable) {  in bcm2835_ic_update()
43         if (s->fiq_select >= GPU_IRQS) {  in bcm2835_ic_update()
45             set = extract32(s->arm_irq_level, s->fiq_select - GPU_IRQS, 1);  in bcm2835_ic_update()
47             set = extract64(s->gpu_irq_level, s->fiq_select, 1);  in bcm2835_ic_update()
50     qemu_set_irq(s->fiq, set);  in bcm2835_ic_update()
52     set = (s->gpu_irq_level & s->gpu_irq_enable)  in bcm2835_ic_update()
53         || (s->arm_irq_level & s->arm_irq_enable);  in bcm2835_ic_update()
54     qemu_set_irq(s->irq, set);  in bcm2835_ic_update()
63     s->gpu_irq_level = deposit64(s->gpu_irq_level, irq, 1, level != 0);  in bcm2835_ic_set_gpu_irq()
73     s->arm_irq_level = deposit32(s->arm_irq_level, irq, 1, level != 0);  in bcm2835_ic_set_arm_irq()
83     uint64_t gpu_pending = s->gpu_irq_level & s->gpu_irq_enable;  in bcm2835_ic_read()
88         /* bits 0-7: ARM irqs */  in bcm2835_ic_read()
89         res = s->arm_irq_level & s->arm_irq_enable;  in bcm2835_ic_read()
95         /* bits 10-20: selected GPU IRQs */  in bcm2835_ic_read()
107         res = (s->fiq_enable << 7) | s->fiq_select;  in bcm2835_ic_read()
110         res = s->gpu_irq_enable;  in bcm2835_ic_read()
113         res = s->gpu_irq_enable >> 32;  in bcm2835_ic_read()
116         res = s->arm_irq_enable;  in bcm2835_ic_read()
119         res = ~s->gpu_irq_enable;  in bcm2835_ic_read()
122         res = ~s->gpu_irq_enable >> 32;  in bcm2835_ic_read()
125         res = ~s->arm_irq_enable;  in bcm2835_ic_read()
143         s->fiq_select = extract32(val, 0, 7);  in bcm2835_ic_write()
144         s->fiq_enable = extract32(val, 7, 1);  in bcm2835_ic_write()
147         s->gpu_irq_enable |= val;  in bcm2835_ic_write()
150         s->gpu_irq_enable |= val << 32;  in bcm2835_ic_write()
153         s->arm_irq_enable |= val & 0xff;  in bcm2835_ic_write()
156         s->gpu_irq_enable &= ~val;  in bcm2835_ic_write()
159         s->gpu_irq_enable &= ~(val << 32);  in bcm2835_ic_write()
162         s->arm_irq_enable &= ~val & 0xff;  in bcm2835_ic_write()
184     s->gpu_irq_enable = 0;  in bcm2835_ic_reset()
185     s->arm_irq_enable = 0;  in bcm2835_ic_reset()
186     s->fiq_enable = false;  in bcm2835_ic_reset()
187     s->fiq_select = 0;  in bcm2835_ic_reset()
194     memory_region_init_io(&s->iomem, obj, &bcm2835_ic_ops, s, TYPE_BCM2835_IC,  in bcm2835_ic_init()
196     sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);  in bcm2835_ic_init()
198     qdev_init_gpio_in_named(DEVICE(s), bcm2835_ic_set_gpu_irq,  in bcm2835_ic_init()
200     qdev_init_gpio_in_named(DEVICE(s), bcm2835_ic_set_arm_irq,  in bcm2835_ic_init()
203     sysbus_init_irq(SYS_BUS_DEVICE(s), &s->irq);  in bcm2835_ic_init()
204     sysbus_init_irq(SYS_BUS_DEVICE(s), &s->fiq);  in bcm2835_ic_init()
227     dc->vmsd = &vmstate_bcm2835_ic;  in bcm2835_ic_class_init()