2  * Allwinner A10 interrupt controller device emulation
21 #include "hw/intc/allwinner-a10-pic.h"
29     int irq = 0, fiq = 0, zeroes;  in aw_a10_pic_update()  local
31     s->vector = 0;  in aw_a10_pic_update()
34         irq |= s->irq_pending[i] & ~s->mask[i];  in aw_a10_pic_update()
35         fiq |= s->select[i] & s->irq_pending[i] & ~s->mask[i];  in aw_a10_pic_update()
37         if (!s->vector) {  in aw_a10_pic_update()
38             zeroes = ctz32(s->irq_pending[i] & ~s->mask[i]);  in aw_a10_pic_update()
40                 s->vector = (i * 32 + zeroes) * 4;  in aw_a10_pic_update()
45     qemu_set_irq(s->parent_irq, !!irq);  in aw_a10_pic_update()
46     qemu_set_irq(s->parent_fiq, !!fiq);  in aw_a10_pic_update()
52     uint32_t *pending_reg = &s->irq_pending[irq / 32];  in aw_a10_pic_set_irq()
65         return s->vector;  in aw_a10_pic_read()
67         return s->base_addr;  in aw_a10_pic_read()
69         return s->protect;  in aw_a10_pic_read()
71         return s->nmi;  in aw_a10_pic_read()
73         return s->irq_pending[index];  in aw_a10_pic_read()
75         return s->fiq_pending[index];  in aw_a10_pic_read()
77         return s->select[index];  in aw_a10_pic_read()
79         return s->enable[index];  in aw_a10_pic_read()
81         return s->mask[index];  in aw_a10_pic_read()
99         s->base_addr = value & ~0x3;  in aw_a10_pic_write()
102         s->protect = value;  in aw_a10_pic_write()
105         s->nmi = value;  in aw_a10_pic_write()
109          * The register is read-only; nevertheless, Linux (including  in aw_a10_pic_write()
115         s->fiq_pending[index] &= ~value;  in aw_a10_pic_write()
118         s->select[index] = value;  in aw_a10_pic_write()
121         s->enable[index] = value;  in aw_a10_pic_write()
124         s->mask[index] = value;  in aw_a10_pic_write()
164      qdev_init_gpio_in(DEVICE(dev), aw_a10_pic_set_irq, AW_A10_PIC_INT_NR);  in aw_a10_pic_init()
165      sysbus_init_irq(dev, &s->parent_irq);  in aw_a10_pic_init()
166      sysbus_init_irq(dev, &s->parent_fiq);  in aw_a10_pic_init()
167      memory_region_init_io(&s->iomem, OBJECT(s), &aw_a10_pic_ops, s,  in aw_a10_pic_init()
169      sysbus_init_mmio(dev, &s->iomem);  in aw_a10_pic_init()
177     s->base_addr = 0;  in aw_a10_pic_reset()
178     s->protect = 0;  in aw_a10_pic_reset()
179     s->nmi = 0;  in aw_a10_pic_reset()
180     s->vector = 0;  in aw_a10_pic_reset()
182         s->irq_pending[i] = 0;  in aw_a10_pic_reset()
183         s->fiq_pending[i] = 0;  in aw_a10_pic_reset()
184         s->select[i] = 0;  in aw_a10_pic_reset()
185         s->enable[i] = 0;  in aw_a10_pic_reset()
186         s->mask[i] = 0;  in aw_a10_pic_reset()
195     dc->desc = "allwinner a10 pic";  in aw_a10_pic_class_init()
196     dc->vmsd = &vmstate_aw_a10_pic;  in aw_a10_pic_class_init()