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/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls2088a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
12 /dts-v1/;
14 #include "fsl-ls2088a.dtsi"
15 #include "fsl-ls208xa-rdb.dtsi"
19 compatible = "fsl,ls2088a-rdb", "fsl,ls2088a";
22 stdout-path = "serial1:115200n8";
27 phy-handle = <&mdio1_phy1>;
28 phy-connection-type = "10gbase-r";
32 phy-handle = <&mdio1_phy2>;
33 phy-connection-type = "10gbase-r";
[all …]
H A Dfsl-lx2160a-bluebox3.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 // Copyright 2020-2021 NXP
7 /dts-v1/;
9 #include "fsl-lx2160a.dtsi"
13 compatible = "fsl,lx2160a-bluebox3", "fsl,lx2160a";
23 stdout-path = "serial0:115200n8";
26 sb_3v3: regulator-sb3v3 {
27 compatible = "regulator-fixed";
28 regulator-name = "MC34717-3.3VSB";
29 regulator-min-microvolt = <3300000>;
[all …]
H A Dfsl-ls1028a-qds-13bb.dtso1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2019-2021 NXP
8 * Requires a SCH-30841 card with lane A of connector rewired to PHY lane C.
9 * Set-up is a SCH-30842 card in slot 1 and SCH-30841 in slot 2.
12 /dts-v1/;
16 #address-cells = <1>;
17 #size-cells = <0>;
19 slot1_sgmii: ethernet-phy@2 {
22 compatible = "ethernet-phy-ieee802.3-c45";
27 phy-handle = <&slot1_sgmii>;
[all …]
H A Dfsl-ls1043a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
5 * Copyright 2014-2015 Freescale Semiconductor, Inc.
6 * Copyright 2018-2021 NXP
11 /dts-v1/;
12 #include "fsl-ls1043a.dtsi"
16 compatible = "fsl,ls1043a-qds", "fsl,ls1043a";
27 sgmii-riser-s1-p1 = &sgmii_phy_s1_p1;
28 sgmii-riser-s2-p1 = &sgmii_phy_s2_p1;
29 sgmii-riser-s3-p1 = &sgmii_phy_s3_p1;
[all …]
H A Dfsl-ls1046a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-1046A family SoC.
6 * Copyright 2018-2019 NXP
11 /dts-v1/;
13 #include "fsl-ls1046a.dtsi"
17 compatible = "fsl,ls1046a-qds", "fsl,ls1046a";
20 emi1-slot1 = &ls1046mdio_s1;
21 emi1-slot2 = &ls1046mdio_s2;
22 emi1-slot4 = &ls1046mdio_s4;
27 qsgmii-s2-p1 = &qsgmii_phy_s2_p1;
[all …]
H A Dfsl-ls1028a-qds-7777.dtso1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2019-2021 NXP
8 * Requires a SCH-30841 card without lane A/C rewire and with a FW with muxing
12 /dts-v1/;
16 #address-cells = <1>;
17 #size-cells = <0>;
20 slot1_sxgmii0: ethernet-phy@0 {
22 compatible = "ethernet-phy-ieee802.3-c45";
25 slot1_sxgmii1: ethernet-phy@1 {
27 compatible = "ethernet-phy-ieee802.3-c45";
[all …]
H A Dfsl-ls1043a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
5 * Copyright 2014-2015 Freescale Semiconductor, Inc.
11 /dts-v1/;
12 #include "fsl-ls1043a.dtsi"
16 compatible = "fsl,ls1043a-rdb", "fsl,ls1043a";
26 stdout-path = "serial0:115200n8";
36 shunt-resistor = <1000>;
67 #address-cells = <2>;
68 #size-cells = <1>;
[all …]
/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dt2081qds.dts4 * Copyright 2013 - 2015 Freescale Semiconductor Inc.
35 /include/ "t208xsi-pre.dtsi"
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
57 ethernet@e0000 {
58 phy-handle = <&phy_sgmii_s7_1c>;
59 phy-connection-type = "sgmii";
62 ethernet@e2000 {
63 phy-handle = <&phy_sgmii_s7_1d>;
[all …]
H A Dt4240qds.dts4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
35 /include/ "t4240si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
89 #address-cells = <1>;
90 #size-cells = <1>;
91 compatible = "cfi-flash";
94 bank-width = <2>;
95 device-width = <1>;
[all …]
H A Dt2080qds.dts4 * Copyright 2013 - 2015 Freescale Semiconductor Inc.
35 /include/ "t208xsi-pre.dtsi"
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
65 ethernet@e0000 {
66 phy-handle = <&phy_sgmii_s3_1e>;
67 phy-connection-type = "xgmii";
70 ethernet@e2000 {
71 phy-handle = <&phy_sgmii_s3_1f>;
[all …]
H A Dt4240rdb.dts4 * Copyright 2014 - 2015 Freescale Semiconductor Inc.
35 /include/ "t4240si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
62 #address-cells = <1>;
63 #size-cells = <1>;
64 compatible = "cfi-flash";
67 bank-width = <2>;
68 device-width = <1>;
[all …]
H A Dt2080rdb.dts2 * T2080PCIe-RDB Board Device Tree Source
4 * Copyright 2014 - 2015 Freescale Semiconductor Inc.
35 /include/ "t208xsi-pre.dtsi"
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
59 ethernet@e0000 {
60 phy-handle = <&xg_aq1202_phy3>;
61 phy-connection-type = "xgmii";
64 ethernet@e2000 {
[all …]
H A Dp5040ds.dts4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
35 /include/ "p5040si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
74 reserved-memory {
75 #address-cells = <2>;
76 #size-cells = <2>;
79 bman_fbpr: bman-fbpr {
83 qman_fqd: qman-fqd {
[all …]
H A Dp4080ds.dts4 * Copyright 2009 - 2015 Freescale Semiconductor Inc.
35 /include/ "p4080si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
62 reserved-memory {
63 #address-cells = <2>;
64 #size-cells = <2>;
67 bman_fbpr: bman-fbpr {
71 qman_fqd: qman-fqd {
[all …]
H A Dt1040rdb.dts4 * Copyright 2014 - 2015 Freescale Semiconductor Inc.
35 /include/ "t104xsi-pre.dtsi"
48 ethernet@e0000 {
49 fixed-link = <0 1 1000 0 0>;
50 phy-connection-type = "sgmii";
53 ethernet@e2000 {
54 fixed-link = <1 1 1000 0 0>;
55 phy-connection-type = "sgmii";
58 ethernet@e4000 {
59 phy-handle = <&phy_sgmii_2>;
[all …]
/openbmc/linux/drivers/net/phy/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # PHY Layer Configuration
12 PHYlink models the link between the PHY and MAC, allowing fixed
17 tristate "PHY Device support and infrastructure"
22 Ethernet controllers are usually attached to PHY
24 managing PHY devices.
35 Adds support for a set of LED trigger events per-PHY. Link
38 supported by the PHY and also a one common "link" trigger as a
39 logical-or of all the link speed ones.
41 <mii bus id>:<phy>:<speed>
[all …]
/openbmc/linux/arch/arm64/boot/dts/microchip/
H A Dsparx5_pcb135_board.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
10 gpio-restart {
11 compatible = "gpio-restart";
17 compatible = "gpio-leds";
21 default-state = "off";
26 default-state = "off";
31 default-state = "off";
36 default-state = "off";
41 default-state = "off";
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dethernet-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ethernet PHY Common Properties
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
14 # The dt-schema tools will generate a select statement first by using
21 pattern: "^ethernet-phy(@[a-f0-9]+)?$"
[all …]
H A Dxlnx,axi-ethernet.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/xlnx,axi-ethernet.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: AXI 1G/2.5G Ethernet Subsystem
10 Also called AXI 1G/2.5G Ethernet Subsystem, the xilinx axi ethernet IP core
11 provides connectivity to an external ethernet PHY supporting different
22 - Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
27 - xlnx,axi-ethernet-1.00.a
28 - xlnx,axi-ethernet-1.01.a
[all …]
H A Dhisilicon-hip04-net.txt1 Hisilicon hip04 Ethernet Controller
3 * Ethernet controller node
6 - compatible: should be "hisilicon,hip04-mac".
7 - reg: address and length of the register set for the device.
8 - interrupts: interrupt for the device.
9 - port-handle: <phandle port channel>
14 - phy-mode: see ethernet.txt [1].
17 - phy-handle: see ethernet.txt [1].
19 [1] Documentation/devicetree/bindings/net/ethernet.txt
22 * Ethernet ppe node:
[all …]
H A Dfsl-enetc.txt1 * ENETC ethernet device tree bindings
9 - reg : Specifies PCIe Device Number and Function
12 - compatible : Should be "fsl,enetc".
14 1. The ENETC external port is connected to a MDIO configurable phy
18 In this case, the ENETC node should include a "mdio" sub-node
19 that in turn should contain the "ethernet-phy" node describing the
20 external phy. Below properties are required, their bindings
21 already defined in Documentation/devicetree/bindings/net/ethernet.txt or
22 Documentation/devicetree/bindings/net/phy.txt.
26 - phy-handle : Phandle to a PHY on the MDIO bus.
[all …]
/openbmc/u-boot/drivers/net/phy/
H A DKconfig3 bool "Bit-banged ethernet MII management channel support"
9 bool "Ethernet PHY (physical media interface) support"
12 Enable Ethernet PHY (physical media interface) support.
17 bool "Limit phy address"
20 Select this if you want to control which phy address is used
24 int "PHY address"
28 The address of PHY on MII bus. Usually in range of 0 to 31.
32 bool "Broadcom BCM53xx (RoboSwitch) Ethernet switch PHY support."
34 Enable support for Broadcom BCM53xx (RoboSwitch) Ethernet switches.
44 hex "Bitmask of PHY ports"
[all …]
/openbmc/linux/arch/arm/boot/dts/marvell/
H A Dorion5x-netgear-wnr854t.dts1 // SPDX-License-Identifier: GPL-2.0-only
4 /dts-v1/;
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
8 #include "orion5x-mv88f5181.dtsi"
11 model = "Netgear WNR854-t";
12 compatible = "netgear,wnr854t", "marvell,orion5x-88f5181",
24 stdout-path = "serial0:115200n8";
33 gpio-keys {
34 compatible = "gpio-keys";
[all …]
/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-j721e-evm-quad-port-eth-exp.dtso1 // SPDX-License-Identifier: GPL-2.0
3 * DT Overlay for CPSW9G in QSGMII mode using J7 Quad Port ETH EXP Add-On Ethernet Card with
6 * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
9 /dts-v1/;
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/phy/phy-cadence.h>
16 #include "k3-pinctrl.h"
17 #include "k3-serdes.h"
21 ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1";
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/dsa/
H A Dmicrochip,lan937x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LAN937x Ethernet Switch Series
10 - UNGLinuxDriver@microchip.com
13 - $ref: dsa.yaml#/$defs/ethernet-ports
18 - microchip,lan9370
19 - microchip,lan9371
20 - microchip,lan9372
21 - microchip,lan9373
[all …]

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