dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso

1 // SPDX-License-Identifier: GPL-2.0
3  * DT Overlay for CPSW9G in QSGMII mode using J7 Quad Port ETH EXP Add-On Ethernet Card with
6  * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
9 /dts-v1/;
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/phy/phy-cadence.h>
16 #include "k3-pinctrl.h"
17 #include "k3-serdes.h"
21 		ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1";
22 		ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2";
23 		ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@3";
24 		ethernet4 = "/bus@100000/ethernet@c000000/ethernet-ports/port@4";
34 	phy-handle = <&cpsw9g_phy0>;
35 	phy-mode = "qsgmii";
36 	mac-address = [00 00 00 00 00 00];
42 	phy-handle = <&cpsw9g_phy1>;
43 	phy-mode = "qsgmii";
44 	mac-address = [00 00 00 00 00 00];
50 	phy-handle = <&cpsw9g_phy2>;
51 	phy-mode = "qsgmii";
52 	mac-address = [00 00 00 00 00 00];
58 	phy-handle = <&cpsw9g_phy3>;
59 	phy-mode = "qsgmii";
60 	mac-address = [00 00 00 00 00 00];
66 	pinctrl-names = "default";
67 	pinctrl-0 = <&mdio0_pins_default>;
68 	reset-gpios = <&exp2 17 GPIO_ACTIVE_LOW>;
69 	reset-post-delay-us = <120000>;
70 	#address-cells = <1>;
71 	#size-cells = <0>;
73 	cpsw9g_phy0: ethernet-phy@17 {
76 	cpsw9g_phy1: ethernet-phy@16 {
79 	cpsw9g_phy2: ethernet-phy@18 {
82 	cpsw9g_phy3: ethernet-phy@19 {
88 	qsgmii-line-hog {
89 		gpio-hog;
91 		output-low;
92 		line-name = "qsgmii-pwrdn-line";
97 	mdio0_pins_default: mdio0-default-pins {
98 		pinctrl-single,pins = <
106 	idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_QSGMII_LANE2>,
121 	assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>, <&serdes0 CDNS_SIERRA_PLL_CMNLC1>;
122 	assigned-clock-parents = <&wiz0_pll1_refclk>, <&wiz0_pll1_refclk>;
123 	#address-cells = <1>;
124 	#size-cells = <0>;
126 	serdes0_qsgmii_link: phy@1 {
128 		cdns,num-lanes = <1>;
129 		#phy-cells = <0>;
130 		cdns,phy-type = <PHY_TYPE_QSGMII>;