17a2aeb91SLi Yang// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2ac0ca416SShaohui Xie/* 3ac0ca416SShaohui Xie * Device Tree Include file for Freescale Layerscape-1043A family SoC. 4ac0ca416SShaohui Xie * 58637f58bSLi Yang * Copyright 2014-2015 Freescale Semiconductor, Inc. 603444ad8SPrabhakar Kushwaha * Copyright 2018 NXP 7ac0ca416SShaohui Xie * 8ac0ca416SShaohui Xie * Mingkai Hu <Mingkai.hu@freescale.com> 9ac0ca416SShaohui Xie */ 10ac0ca416SShaohui Xie 11ac0ca416SShaohui Xie/dts-v1/; 1218486552SHongtao Jia#include "fsl-ls1043a.dtsi" 13ac0ca416SShaohui Xie 14ac0ca416SShaohui Xie/ { 15ac0ca416SShaohui Xie model = "LS1043A RDB Board"; 16fa578d4eSYangbo Lu compatible = "fsl,ls1043a-rdb", "fsl,ls1043a"; 1763dac35bSHoria Geantă 1863dac35bSHoria Geantă aliases { 1944605b65SStuart Yoder serial0 = &duart0; 2044605b65SStuart Yoder serial1 = &duart1; 2144605b65SStuart Yoder serial2 = &duart2; 2244605b65SStuart Yoder serial3 = &duart3; 2363dac35bSHoria Geantă }; 24d5c8b122SStuart Yoder 25d5c8b122SStuart Yoder chosen { 26d5c8b122SStuart Yoder stdout-path = "serial0:115200n8"; 27d5c8b122SStuart Yoder }; 28ac0ca416SShaohui Xie}; 29ac0ca416SShaohui Xie 30ac0ca416SShaohui Xie&i2c0 { 31ac0ca416SShaohui Xie status = "okay"; 32*a81e12d2SLi Yang 33ac0ca416SShaohui Xie ina220@40 { 34ac0ca416SShaohui Xie compatible = "ti,ina220"; 35ac0ca416SShaohui Xie reg = <0x40>; 36ac0ca416SShaohui Xie shunt-resistor = <1000>; 37ac0ca416SShaohui Xie }; 38*a81e12d2SLi Yang 39ac0ca416SShaohui Xie adt7461a@4c { 40ac0ca416SShaohui Xie compatible = "adi,adt7461"; 41ac0ca416SShaohui Xie reg = <0x4c>; 42ac0ca416SShaohui Xie }; 43*a81e12d2SLi Yang 44*a81e12d2SLi Yang rtc@51 { 45*a81e12d2SLi Yang compatible = "nxp,pcf85263"; 46*a81e12d2SLi Yang reg = <0x51>; 47*a81e12d2SLi Yang }; 48*a81e12d2SLi Yang 49ac0ca416SShaohui Xie eeprom@52 { 50f218868bSJavier Martinez Canillas compatible = "atmel,24c512"; 51ac0ca416SShaohui Xie reg = <0x52>; 52ac0ca416SShaohui Xie }; 53*a81e12d2SLi Yang 54ac0ca416SShaohui Xie eeprom@53 { 55f218868bSJavier Martinez Canillas compatible = "atmel,24c512"; 56ac0ca416SShaohui Xie reg = <0x53>; 57ac0ca416SShaohui Xie }; 58*a81e12d2SLi Yang 59ac0ca416SShaohui Xie rtc@68 { 60ac0ca416SShaohui Xie compatible = "pericom,pt7c4338"; 61ac0ca416SShaohui Xie reg = <0x68>; 62ac0ca416SShaohui Xie }; 63ac0ca416SShaohui Xie}; 64ac0ca416SShaohui Xie 65ac0ca416SShaohui Xie&ifc { 66ac0ca416SShaohui Xie status = "okay"; 67ac0ca416SShaohui Xie #address-cells = <2>; 68ac0ca416SShaohui Xie #size-cells = <1>; 69ac0ca416SShaohui Xie /* NOR, NAND Flashes and FPGA on board */ 70ac0ca416SShaohui Xie ranges = <0x0 0x0 0x0 0x60000000 0x08000000 71ac0ca416SShaohui Xie 0x1 0x0 0x0 0x7e800000 0x00010000 72ac0ca416SShaohui Xie 0x2 0x0 0x0 0x7fb00000 0x00000100>; 73ac0ca416SShaohui Xie 74ac0ca416SShaohui Xie nor@0,0 { 75ac0ca416SShaohui Xie compatible = "cfi-flash"; 76ac0ca416SShaohui Xie #address-cells = <1>; 77ac0ca416SShaohui Xie #size-cells = <1>; 78ac0ca416SShaohui Xie reg = <0x0 0x0 0x8000000>; 7903444ad8SPrabhakar Kushwaha big-endian; 80ac0ca416SShaohui Xie bank-width = <2>; 81ac0ca416SShaohui Xie device-width = <1>; 82ac0ca416SShaohui Xie }; 83ac0ca416SShaohui Xie 84ac0ca416SShaohui Xie nand@1,0 { 85ac0ca416SShaohui Xie compatible = "fsl,ifc-nand"; 86ac0ca416SShaohui Xie #address-cells = <1>; 87ac0ca416SShaohui Xie #size-cells = <1>; 88ac0ca416SShaohui Xie reg = <0x1 0x0 0x10000>; 89ac0ca416SShaohui Xie }; 90ac0ca416SShaohui Xie 91ac0ca416SShaohui Xie cpld: board-control@2,0 { 92ac0ca416SShaohui Xie compatible = "fsl,ls1043ardb-cpld"; 93ac0ca416SShaohui Xie reg = <0x2 0x0 0x0000100>; 94ac0ca416SShaohui Xie }; 95ac0ca416SShaohui Xie}; 96ac0ca416SShaohui Xie 97730628f0SYunhui Cui&dspi0 { 98730628f0SYunhui Cui bus-num = <0>; 99730628f0SYunhui Cui status = "okay"; 100730628f0SYunhui Cui 101730628f0SYunhui Cui flash@0 { 102730628f0SYunhui Cui #address-cells = <1>; 103730628f0SYunhui Cui #size-cells = <1>; 104730628f0SYunhui Cui compatible = "n25q128a13", "jedec,spi-nor"; /* 16MB */ 105730628f0SYunhui Cui reg = <0>; 106730628f0SYunhui Cui spi-max-frequency = <1000000>; /* input clock */ 107745fa3e4SMeng Li fsl,spi-cs-sck-delay = <100>; 108745fa3e4SMeng Li fsl,spi-sck-cs-delay = <100>; 109730628f0SYunhui Cui }; 11048ffd4ebSZhao Qiang 11148ffd4ebSZhao Qiang slic@2 { 11248ffd4ebSZhao Qiang compatible = "maxim,ds26522"; 11348ffd4ebSZhao Qiang reg = <2>; 11448ffd4ebSZhao Qiang spi-max-frequency = <2000000>; 11548ffd4ebSZhao Qiang fsl,spi-cs-sck-delay = <100>; 11648ffd4ebSZhao Qiang fsl,spi-sck-cs-delay = <50>; 11748ffd4ebSZhao Qiang }; 11848ffd4ebSZhao Qiang 11948ffd4ebSZhao Qiang slic@3 { 12048ffd4ebSZhao Qiang compatible = "maxim,ds26522"; 12148ffd4ebSZhao Qiang reg = <3>; 12248ffd4ebSZhao Qiang spi-max-frequency = <2000000>; 12348ffd4ebSZhao Qiang fsl,spi-cs-sck-delay = <100>; 12448ffd4ebSZhao Qiang fsl,spi-sck-cs-delay = <50>; 12548ffd4ebSZhao Qiang }; 126730628f0SYunhui Cui}; 127730628f0SYunhui Cui 128ac0ca416SShaohui Xie&duart0 { 129ac0ca416SShaohui Xie status = "okay"; 130ac0ca416SShaohui Xie}; 131ac0ca416SShaohui Xie 132ac0ca416SShaohui Xie&duart1 { 133ac0ca416SShaohui Xie status = "okay"; 134ac0ca416SShaohui Xie}; 135bf02f2ffSMadalin Bucur 136bf02f2ffSMadalin Bucur#include "fsl-ls1043-post.dtsi" 137bf02f2ffSMadalin Bucur 138bf02f2ffSMadalin Bucur&fman0 { 139bf02f2ffSMadalin Bucur ethernet@e0000 { 140bf02f2ffSMadalin Bucur phy-handle = <&qsgmii_phy1>; 141bf02f2ffSMadalin Bucur phy-connection-type = "qsgmii"; 142bf02f2ffSMadalin Bucur }; 143bf02f2ffSMadalin Bucur 144bf02f2ffSMadalin Bucur ethernet@e2000 { 145bf02f2ffSMadalin Bucur phy-handle = <&qsgmii_phy2>; 146bf02f2ffSMadalin Bucur phy-connection-type = "qsgmii"; 147bf02f2ffSMadalin Bucur }; 148bf02f2ffSMadalin Bucur 149bf02f2ffSMadalin Bucur ethernet@e4000 { 150bf02f2ffSMadalin Bucur phy-handle = <&rgmii_phy1>; 1514022d808SMadalin Bucur phy-connection-type = "rgmii-id"; 152bf02f2ffSMadalin Bucur }; 153bf02f2ffSMadalin Bucur 154bf02f2ffSMadalin Bucur ethernet@e6000 { 155bf02f2ffSMadalin Bucur phy-handle = <&rgmii_phy2>; 1564022d808SMadalin Bucur phy-connection-type = "rgmii-id"; 157bf02f2ffSMadalin Bucur }; 158bf02f2ffSMadalin Bucur 159bf02f2ffSMadalin Bucur ethernet@e8000 { 160bf02f2ffSMadalin Bucur phy-handle = <&qsgmii_phy3>; 161bf02f2ffSMadalin Bucur phy-connection-type = "qsgmii"; 162bf02f2ffSMadalin Bucur }; 163bf02f2ffSMadalin Bucur 164bf02f2ffSMadalin Bucur ethernet@ea000 { 165bf02f2ffSMadalin Bucur phy-handle = <&qsgmii_phy4>; 166bf02f2ffSMadalin Bucur phy-connection-type = "qsgmii"; 167bf02f2ffSMadalin Bucur }; 168bf02f2ffSMadalin Bucur 169bf02f2ffSMadalin Bucur ethernet@f0000 { /* 10GEC1 */ 170bf02f2ffSMadalin Bucur phy-handle = <&aqr105_phy>; 171bf02f2ffSMadalin Bucur phy-connection-type = "xgmii"; 172bf02f2ffSMadalin Bucur }; 173bf02f2ffSMadalin Bucur 174bf02f2ffSMadalin Bucur mdio@fc000 { 175bf02f2ffSMadalin Bucur rgmii_phy1: ethernet-phy@1 { 176bf02f2ffSMadalin Bucur reg = <0x1>; 177bf02f2ffSMadalin Bucur }; 178bf02f2ffSMadalin Bucur 179bf02f2ffSMadalin Bucur rgmii_phy2: ethernet-phy@2 { 180bf02f2ffSMadalin Bucur reg = <0x2>; 181bf02f2ffSMadalin Bucur }; 182bf02f2ffSMadalin Bucur 183bf02f2ffSMadalin Bucur qsgmii_phy1: ethernet-phy@4 { 184bf02f2ffSMadalin Bucur reg = <0x4>; 185bf02f2ffSMadalin Bucur }; 186bf02f2ffSMadalin Bucur 187bf02f2ffSMadalin Bucur qsgmii_phy2: ethernet-phy@5 { 188bf02f2ffSMadalin Bucur reg = <0x5>; 189bf02f2ffSMadalin Bucur }; 190bf02f2ffSMadalin Bucur 191bf02f2ffSMadalin Bucur qsgmii_phy3: ethernet-phy@6 { 192bf02f2ffSMadalin Bucur reg = <0x6>; 193bf02f2ffSMadalin Bucur }; 194bf02f2ffSMadalin Bucur 195bf02f2ffSMadalin Bucur qsgmii_phy4: ethernet-phy@7 { 196bf02f2ffSMadalin Bucur reg = <0x7>; 197bf02f2ffSMadalin Bucur }; 198bf02f2ffSMadalin Bucur }; 199bf02f2ffSMadalin Bucur 200bf02f2ffSMadalin Bucur mdio@fd000 { 201bf02f2ffSMadalin Bucur aqr105_phy: ethernet-phy@1 { 202bf02f2ffSMadalin Bucur compatible = "ethernet-phy-ieee802.3-c45"; 203bf02f2ffSMadalin Bucur interrupts = <0 132 4>; 204bf02f2ffSMadalin Bucur reg = <0x1>; 205bf02f2ffSMadalin Bucur }; 206bf02f2ffSMadalin Bucur }; 207bf02f2ffSMadalin Bucur}; 20876afd7dbSZhao Qiang 20976afd7dbSZhao Qiang&uqe { 21076afd7dbSZhao Qiang ucc_hdlc: ucc@2000 { 21176afd7dbSZhao Qiang compatible = "fsl,ucc-hdlc"; 21276afd7dbSZhao Qiang rx-clock-name = "clk8"; 21376afd7dbSZhao Qiang tx-clock-name = "clk9"; 21476afd7dbSZhao Qiang fsl,rx-sync-clock = "rsync_pin"; 21576afd7dbSZhao Qiang fsl,tx-sync-clock = "tsync_pin"; 21676afd7dbSZhao Qiang fsl,tx-timeslot-mask = <0xfffffffe>; 21776afd7dbSZhao Qiang fsl,rx-timeslot-mask = <0xfffffffe>; 21876afd7dbSZhao Qiang fsl,tdm-framer-type = "e1"; 21976afd7dbSZhao Qiang fsl,tdm-id = <0>; 22076afd7dbSZhao Qiang fsl,siram-entry-id = <0>; 22176afd7dbSZhao Qiang fsl,tdm-interface; 22276afd7dbSZhao Qiang }; 22376afd7dbSZhao Qiang}; 2241069a0bbSRan Wang 2251069a0bbSRan Wang&usb0 { 2261069a0bbSRan Wang status = "okay"; 2271069a0bbSRan Wang}; 2281069a0bbSRan Wang 2291069a0bbSRan Wang&usb1 { 2301069a0bbSRan Wang status = "okay"; 2311069a0bbSRan Wang}; 232