1*4c33cb31SAndrew Davis// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4c33cb31SAndrew Davis/* 3*4c33cb31SAndrew Davis * Device Tree fragment for LS1028A QDS board, serdes 13bb 4*4c33cb31SAndrew Davis * 5*4c33cb31SAndrew Davis * Copyright 2019-2021 NXP 6*4c33cb31SAndrew Davis * 7*4c33cb31SAndrew Davis * Requires a LS1028A QDS board with lane B rework. 8*4c33cb31SAndrew Davis * Requires a SCH-30841 card with lane A of connector rewired to PHY lane C. 9*4c33cb31SAndrew Davis * Set-up is a SCH-30842 card in slot 1 and SCH-30841 in slot 2. 10*4c33cb31SAndrew Davis */ 11*4c33cb31SAndrew Davis 12*4c33cb31SAndrew Davis/dts-v1/; 13*4c33cb31SAndrew Davis/plugin/; 14*4c33cb31SAndrew Davis 15*4c33cb31SAndrew Davis&mdio_slot1 { 16*4c33cb31SAndrew Davis #address-cells = <1>; 17*4c33cb31SAndrew Davis #size-cells = <0>; 18*4c33cb31SAndrew Davis 19*4c33cb31SAndrew Davis slot1_sgmii: ethernet-phy@2 { 20*4c33cb31SAndrew Davis /* AQR112 */ 21*4c33cb31SAndrew Davis reg = <0x2>; 22*4c33cb31SAndrew Davis compatible = "ethernet-phy-ieee802.3-c45"; 23*4c33cb31SAndrew Davis }; 24*4c33cb31SAndrew Davis}; 25*4c33cb31SAndrew Davis 26*4c33cb31SAndrew Davis&enetc_port0 { 27*4c33cb31SAndrew Davis phy-handle = <&slot1_sgmii>; 28*4c33cb31SAndrew Davis phy-mode = "usxgmii"; 29*4c33cb31SAndrew Davis managed = "in-band-status"; 30*4c33cb31SAndrew Davis status = "okay"; 31*4c33cb31SAndrew Davis}; 32*4c33cb31SAndrew Davis 33*4c33cb31SAndrew Davis&mdio_slot2 { 34*4c33cb31SAndrew Davis #address-cells = <1>; 35*4c33cb31SAndrew Davis #size-cells = <0>; 36*4c33cb31SAndrew Davis 37*4c33cb31SAndrew Davis /* 4 ports on AQR412 */ 38*4c33cb31SAndrew Davis slot2_qxgmii0: ethernet-phy@0 { 39*4c33cb31SAndrew Davis reg = <0x0>; 40*4c33cb31SAndrew Davis compatible = "ethernet-phy-ieee802.3-c45"; 41*4c33cb31SAndrew Davis }; 42*4c33cb31SAndrew Davis 43*4c33cb31SAndrew Davis slot2_qxgmii1: ethernet-phy@1 { 44*4c33cb31SAndrew Davis reg = <0x1>; 45*4c33cb31SAndrew Davis compatible = "ethernet-phy-ieee802.3-c45"; 46*4c33cb31SAndrew Davis }; 47*4c33cb31SAndrew Davis 48*4c33cb31SAndrew Davis slot2_qxgmii2: ethernet-phy@2 { 49*4c33cb31SAndrew Davis reg = <0x2>; 50*4c33cb31SAndrew Davis compatible = "ethernet-phy-ieee802.3-c45"; 51*4c33cb31SAndrew Davis }; 52*4c33cb31SAndrew Davis 53*4c33cb31SAndrew Davis slot2_qxgmii3: ethernet-phy@3 { 54*4c33cb31SAndrew Davis reg = <0x3>; 55*4c33cb31SAndrew Davis compatible = "ethernet-phy-ieee802.3-c45"; 56*4c33cb31SAndrew Davis }; 57*4c33cb31SAndrew Davis}; 58*4c33cb31SAndrew Davis 59*4c33cb31SAndrew Davis&mscc_felix_ports { 60*4c33cb31SAndrew Davis port@0 { 61*4c33cb31SAndrew Davis status = "okay"; 62*4c33cb31SAndrew Davis phy-handle = <&slot2_qxgmii0>; 63*4c33cb31SAndrew Davis phy-mode = "usxgmii"; 64*4c33cb31SAndrew Davis managed = "in-band-status"; 65*4c33cb31SAndrew Davis }; 66*4c33cb31SAndrew Davis 67*4c33cb31SAndrew Davis port@1 { 68*4c33cb31SAndrew Davis status = "okay"; 69*4c33cb31SAndrew Davis phy-handle = <&slot2_qxgmii1>; 70*4c33cb31SAndrew Davis phy-mode = "usxgmii"; 71*4c33cb31SAndrew Davis managed = "in-band-status"; 72*4c33cb31SAndrew Davis }; 73*4c33cb31SAndrew Davis 74*4c33cb31SAndrew Davis port@2 { 75*4c33cb31SAndrew Davis status = "okay"; 76*4c33cb31SAndrew Davis phy-handle = <&slot2_qxgmii2>; 77*4c33cb31SAndrew Davis phy-mode = "usxgmii"; 78*4c33cb31SAndrew Davis managed = "in-band-status"; 79*4c33cb31SAndrew Davis }; 80*4c33cb31SAndrew Davis 81*4c33cb31SAndrew Davis port@3 { 82*4c33cb31SAndrew Davis status = "okay"; 83*4c33cb31SAndrew Davis phy-handle = <&slot2_qxgmii3>; 84*4c33cb31SAndrew Davis phy-mode = "usxgmii"; 85*4c33cb31SAndrew Davis managed = "in-band-status"; 86*4c33cb31SAndrew Davis }; 87*4c33cb31SAndrew Davis}; 88*4c33cb31SAndrew Davis 89*4c33cb31SAndrew Davis&mscc_felix { 90*4c33cb31SAndrew Davis status = "okay"; 91*4c33cb31SAndrew Davis}; 92