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/openbmc/linux/sound/soc/atmel/
H A Datmel-pcm.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * at91-pcm.h - ALSA PCM interface for the Atmel AT91 SoC.
10 * Based on at91-pcm. by:
14 * Based on pxa2xx-pcm.c by:
24 #include <linux/atmel-ssc.h>
40 u32 ssc_enable; /* SSC recv/trans enable */
41 u32 ssc_disable; /* SSC recv/trans disable */
42 u32 ssc_error; /* SSC error conditions */
43 u32 ssc_endx; /* SSC ENDTX or ENDRX */
44 u32 ssc_endbuf; /* SSC TXBUFE or RXBUFF */
[all …]
H A Datmel_ssc_dai.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * atmel_ssc_dai.c -- ALSA SoC ATMEL SSC Audio Layer Platform driver
11 * Based on at91-ssc.c by
25 #include <linux/atmel-ssc.h>
32 #include "atmel-pcm.h"
39 * SSC PDC registers required by the PCM DMA engine.
56 * SSC & PDC status bits for transmit and receive.
136 * SSC interrupt handler. Passes PDC interrupts to the DMA
147 ssc_sr = (unsigned long)ssc_readl(ssc_p->ssc->regs, SR) in atmel_ssc_interrupt()
148 & (unsigned long)ssc_readl(ssc_p->ssc->regs, IMR); in atmel_ssc_interrupt()
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/openbmc/linux/drivers/mmc/host/
H A Dsdhci-pci-gli.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Version: v0.9.0 (2019-08-08)
18 #include "sdhci-cqhci.h"
19 #include "sdhci-pci.h"
335 /* enable tuning parameters control */ in gli_set_9750()
392 if (!host->tuning_done) { in __sdhci_execute_tuning_9750()
405 if (!host->tuning_done) { in __sdhci_execute_tuning_9750()
407 mmc_hostname(host->mmc)); in __sdhci_execute_tuning_9750()
408 return -ETIMEDOUT; in __sdhci_execute_tuning_9750()
412 mmc_hostname(host->mmc)); in __sdhci_execute_tuning_9750()
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/openbmc/linux/include/linux/
H A Datmel-ssc.h1 /* SPDX-License-Identifier: GPL-2.0 */
28 void ssc_free(struct ssc_device *ssc);
30 /* SSC register offsets */
32 /* SSC Control Register */
45 /* SSC Clock Mode Register */
50 /* SSC Receive Clock Mode Register */
69 /* SSC Receive Frame Mode Register */
92 /* SSC Transmit Clock Mode Register */
109 /* SSC Transmit Frame Mode Register */
134 /* SSC Receive Hold Register */
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/openbmc/linux/include/linux/clk/
H A Dti.h1 /* SPDX-License-Identifier: GPL-2.0-only */
10 #include <linux/clk-provider.h>
14 * struct clk_omap_reg - OMAP register declaration
26 * struct dpll_data - DPLL registers and integration data
40 * @max_multiplier: maximum valid non-bypass multiplier value (actual)
42 * @min_divider: minimum valid non-bypass divider value (actual)
43 * @max_divider: maximum valid non-bypass divider value (actual)
53 * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg
55 * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
58 * @ssc_deltam_reg: register containing the DPLL SSC frequency spreading
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/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_pch_refclk.c1 // SPDX-License-Identifier: MIT
19 drm_err(&dev_priv->drm, "FDI mPHY reset assert timeout\n"); in lpt_fdi_reset_mphy()
25 drm_err(&dev_priv->drm, "FDI mPHY reset de-assert timeout\n"); in lpt_fdi_reset_mphy()
111 mutex_lock(&dev_priv->sb_lock); in lpt_disable_iclkip()
117 mutex_unlock(&dev_priv->sb_lock); in lpt_disable_iclkip()
130 p->iclk_virtual_root_freq = 172800 * 1000; in iclkip_params_init()
131 p->iclk_pi_range = 64; in iclkip_params_init()
136 return DIV_ROUND_CLOSEST(p->iclk_virtual_root_freq, in lpt_iclkip_freq()
137 p->desired_divisor << p->auxdiv); in lpt_iclkip_freq()
145 * but the adjusted_mode->crtc_clock in KHz. To get the in lpt_compute_iclkip()
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/openbmc/linux/Documentation/devicetree/bindings/clock/ti/
H A Ddpll.txt3 Binding status: Unstable - ABI compatibility may be broken in the future
6 register-mapped DPLL with usually two selectable input clocks
11 sub-types, which effectively result in slightly different setup
14 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
17 - compatible : shall be one of:
18 "ti,omap3-dpll-clock",
19 "ti,omap3-dpll-core-clock",
20 "ti,omap3-dpll-per-clock",
21 "ti,omap3-dpll-per-j-type-clock",
22 "ti,omap4-dpll-clock",
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/openbmc/linux/drivers/scsi/mvsas/
H A Dmv_94xx.h1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
45 MVS_STP_REG_SET_0 = 0x118, /* STP/SATA Register Set Enable */
61 MVS_INT_MASK = 0x154, /* Central int enable */
66 MVS_NON_NCQ_ERR_0 = 0x168, /* SRS Non-specific NCQ Error */
72 /* ports 1-3 follow after this */
75 /* ports 5-7 follow after this */
77 MVS_P4_INT_MASK = 0x1A4, /* Port4 interrupt enable mask */
79 /* ports 1-3 follow after this */
81 /* ports 5-7 follow after this */
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/openbmc/linux/drivers/scsi/isci/
H A Dprobe_roms.h7 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
20 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
26 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
80 * This field specifies the NOTIFY (ENABLE SPIN UP) primitive
103 * - A value of 1 indicates generation 1 (i.e. 1.5 Gb/s).
104 * - A value of 2 indicates generation 2 (i.e. 3.0 Gb/s).
105 * - A value of 3 indicates generation 3 (i.e. 6.0 Gb/s).
228 * Spread Spectrum Clocking (SSC) settings for SATA and SAS.
229 * NOTE: Default SSC Modulation Frequency is 31.5KHz.
234 * NOTE: Max spread for SATA is +0 / -5000 PPM.
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/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Drenesas,usb3-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/renesas,usb3-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car generation 3 USB 3.0 PHY
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
15 - enum:
16 - renesas,r8a774a1-usb3-phy # RZ/G2M
17 - renesas,r8a774b1-usb3-phy # RZ/G2N
18 - renesas,r8a774e1-usb3-phy # RZ/G2H
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H A Dphy-rockchip-naneng-combphy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-rockchip-naneng-combphy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
15 - rockchip,rk3568-naneng-combphy
16 - rockchip,rk3588-naneng-combphy
23 - description: reference clock
24 - description: apb clock
25 - description: pipe clock
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H A Dbrcm,sata-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/brcm,sata-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Florian Fainelli <f.fainelli@gmail.com>
14 pattern: "^sata[-|_]phy(@.*)?$"
18 - items:
19 - enum:
20 - brcm,bcm7216-sata-phy
21 - brcm,bcm7425-sata-phy
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H A Dphy-cadence-torrent.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
16 - Swapnil Jakhade <sjakhade@cadence.com>
17 - Yuti Amonkar <yamonkar@cadence.com>
22 - cdns,torrent-phy
23 - ti,j721e-serdes-10g
25 '#address-cells':
28 '#size-cells':
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/openbmc/linux/sound/spi/
H A Dat73c213.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Driver for AT73C213 16-bit stereo DAC connected to Atmel SSC
5 * Copyright (C) 2006-2007 Atmel Norway
14 #include <linux/dma-mapping.h>
27 #include <linux/atmel-ssc.h>
41 0x00, /* 00 - CTRL */
42 0x05, /* 01 - LLIG */
43 0x05, /* 02 - RLIG */
44 0x08, /* 03 - LPMG */
45 0x08, /* 04 - RPMG */
[all …]
/openbmc/linux/drivers/spi/
H A Dspi-st-ssc4.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2008-2014 STMicroelectronics Limited
25 /* SSC registers */
33 /* SSC Control */
48 /* SSC Interrupt Enable */
54 /* SSC SPI Controller */
59 /* SSC SPI current transaction */
74 if (spi_st->words_remaining > FIFO_SIZE) in ssc_write_tx_fifo()
77 count = spi_st->words_remaining; in ssc_write_tx_fifo()
80 if (spi_st->tx_ptr) { in ssc_write_tx_fifo()
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/openbmc/qemu/target/arm/
H A Dhyp_gdbstub.c4 * Copyright Mian-M. Hamayun 2013, Virtual Open Systems
8 * See the COPYING file in the top-level directory.
26 * simple un-linked breakpoints (i.e. we don't chain breakpoints
34 * +------+------+-------+-----+----+------+-----+------+-----+---+
35 * | RES0 | BT | LBN | SSC | HMC| RES0 | BAS | RES0 | PMC | E |
36 * +------+------+-------+-----+----+------+-----+------+-----+---+
40 * SSC/HMC/PMC: Security, Higher and Priv access control (Table D-12)
42 * E: Enable bit
47 * +------+-----------+----------+-----+
49 * +------+-----------+----------+-----+
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/openbmc/linux/include/linux/phy/
H A Dphy-dp.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 * struct phy_configure_opts_dp - DisplayPort PHY configuration set
51 * Pre-emphasis levels, as specified by DisplayPort specification, to be
59 * @ssc:
61 * Flag indicating, whether or not to enable spread-spectrum clocking.
64 u8 ssc : 1; member
69 * Flag indicating, whether or not reconfigure link rate and SSC to
88 * and pre-emphasis to requested values. Only lanes specified
/openbmc/linux/drivers/bus/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
29 Say y here to enable support for the ARM Logic Module bus
37 Driver for the Broadcom Set Top Box System-on-a-chip internal bus
42 bool "Baikal-T1 APB-bus driver"
46 Baikal-T1 AXI-APB bridge is used to access the SoC subsystem CSRs.
53 errors counter. The counter and the APB-bus operations timeout can be
57 bool "Baikal-T1 AXI-bus driver"
61 AXI3-bus is the main communication bus connecting all high-speed
62 peripheral IP-cores with RAM controller and with MIPS P5600 cores on
63 Baikal-T1 SoC. Traffic arbitration is done by means of DW AMBA 3 AXI
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/openbmc/linux/drivers/phy/cadence/
H A Dphy-cadence-torrent.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/phy/phy-cadence.h>
12 #include <linux/clk-provider.h>
239 [CDNS_TORRENT_REFCLK_DRIVER] = "refclk-driver",
240 [CDNS_TORRENT_DERIVED_REFCLK] = "refclk-der",
241 [CDNS_TORRENT_RECEIVED_REFCLK] = "refclk-rec",
329 #define CDNS_TORRENT_KEY(refclk0, refclk1, link0, link1, ssc) \ argument
334 (((ssc) << SSC_SHIFT) & SSC_MASK))
459 enum cdns_torrent_ssc_mode ssc) in cdns_torrent_get_tbl_vals() argument
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/openbmc/linux/drivers/phy/xilinx/
H A Dphy-zynqmp.c1 // SPDX-License-Identifier: GPL-2.0
3 * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT.
5 * Copyright (C) 2018-2020 Xilinx Inc.
26 #include <dt-bindings/phy/phy.h>
32 /* TX De-emphasis parameters */
61 /* PLL SSC step size offsets */
70 /* SSC step size parameters */
190 * struct xpsgtr_ssc - structure to hold SSC settings for a lane
193 * @steps: number of steps of SSC (Spread Spectrum Clock)
204 * struct xpsgtr_phy - representation of a lane
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/openbmc/linux/drivers/i2c/busses/
H A Di2c-st.c1 // SPDX-License-Identifier: GPL-2.0-only
23 /* SSC registers */
47 /* SSC Control */
62 /* SSC Interrupt Enable */
76 /* SSC Status */
93 /* SSC I2C Control */
103 /* SSC Tx FIFO Status */
106 /* SSC Rx FIFO Status */
109 /* SSC Clear bit operation */
116 /* SSC Clock Prescaler */
[all …]
/openbmc/linux/drivers/phy/st/
H A Dphy-miphy28lp.c1 // SPDX-License-Identifier: GPL-2.0-only
25 #include <dt-bindings/phy/phy.h>
171 * 0: 30MHz crystal clk - 1: 100MHz ext clk routed through MiPHY1
173 * 1: 30MHz crystal clk - 0: 100MHz ext clk routed through MiPHY1
211 bool ssc; member
238 static char *PHY_TYPE_name[] = { "sata-up", "pcie-up", "", "usb3-up" };
367 void __iomem *base = miphy_phy->base; in miphy28lp_set_reset()
378 /* Bringing the MIPHY-CPU registers out of reset */ in miphy28lp_set_reset()
379 if (miphy_phy->type == PHY_TYPE_PCIE) { in miphy28lp_set_reset()
391 void __iomem *base = miphy_phy->base; in miphy28lp_pll_calibration()
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/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dbrcm,stb-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/brcm,stb-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
15 - enum:
16 - brcm,bcm2711-pcie # The Raspberry Pi 4
17 - brcm,bcm4908-pcie
18 - brcm,bcm7211-pcie # Broadcom STB version of RPi4
19 - brcm,bcm7278-pcie # Broadcom 7278 Arm
[all …]
/openbmc/linux/drivers/phy/ralink/
H A Dphy-mt7621-pci.c1 // SPDX-License-Identifier: GPL-2.0+
7 #include <dt-bindings/phy/phy.h>
66 * struct mt7621_pci_phy - Mt7621 Pcie PHY core
98 regmap_read(phy->regmap, reg, &val); in mt7621_phy_rmw()
101 regmap_write(phy->regmap, reg, val); in mt7621_phy_rmw()
109 if (phy->has_dual_port) { in mt7621_bypass_pipe_rst()
119 struct device *dev = phy->dev; in mt7621_set_phy_for_ssc()
122 clk_rate = clk_get_rate(phy->sys_clk); in mt7621_set_phy_for_ssc()
124 return -EINVAL; in mt7621_set_phy_for_ssc()
126 /* Set PCIe Port PHY to disable SSC */ in mt7621_set_phy_for_ssc()
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/openbmc/linux/drivers/phy/broadcom/
H A Dphy-bcm-ns-usb3.c1 // SPDX-License-Identifier: GPL-2.0-only
58 .compatible = "brcm,ns-ax-usb3-phy",
62 .compatible = "brcm,ns-bx-usb3-phy",
94 writel(0, usb3->dmp + BCMA_RESET_CTL); in bcm_ns_usb3_phy_init_ns_bx()
96 /* PLL frequency monitor enable */ in bcm_ns_usb3_phy_init_ns_bx()
113 /* Enabling SSC */ in bcm_ns_usb3_phy_init_ns_bx()
135 /* Enable SSC */ in bcm_ns_usb3_phy_init_ns_ax()
144 writel(0, usb3->dmp + BCMA_RESET_CTL); in bcm_ns_usb3_phy_init_ns_ax()
155 writel(BCMA_RESET_CTL_RESET, usb3->dmp + BCMA_RESET_CTL); in bcm_ns_usb3_phy_init()
157 switch (usb3->family) { in bcm_ns_usb3_phy_init()
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