1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 2eb1f2930SHans-Christian Egtvedt #ifndef __INCLUDE_ATMEL_SSC_H 3eb1f2930SHans-Christian Egtvedt #define __INCLUDE_ATMEL_SSC_H 4eb1f2930SHans-Christian Egtvedt 5eb1f2930SHans-Christian Egtvedt #include <linux/platform_device.h> 6eb1f2930SHans-Christian Egtvedt #include <linux/list.h> 7b969afc8SJoachim Eastwood #include <linux/io.h> 8eb1f2930SHans-Christian Egtvedt 9636036d2SBo Shen struct atmel_ssc_platform_data { 10636036d2SBo Shen int use_dma; 11c4027fafSBo Shen int has_fslen_ext; 12636036d2SBo Shen }; 13636036d2SBo Shen 14eb1f2930SHans-Christian Egtvedt struct ssc_device { 15eb1f2930SHans-Christian Egtvedt struct list_head list; 1610175b3bSBo Shen dma_addr_t phybase; 17eb1f2930SHans-Christian Egtvedt void __iomem *regs; 18eb1f2930SHans-Christian Egtvedt struct platform_device *pdev; 19636036d2SBo Shen struct atmel_ssc_platform_data *pdata; 20eb1f2930SHans-Christian Egtvedt struct clk *clk; 21eb1f2930SHans-Christian Egtvedt int user; 22eb1f2930SHans-Christian Egtvedt int irq; 23048d4ff8SBo Shen bool clk_from_rk_pin; 24e8314d7dSPeter Rosin bool sound_dai; 25eb1f2930SHans-Christian Egtvedt }; 26eb1f2930SHans-Christian Egtvedt 27eb1f2930SHans-Christian Egtvedt struct ssc_device * __must_check ssc_request(unsigned int ssc_num); 28eb1f2930SHans-Christian Egtvedt void ssc_free(struct ssc_device *ssc); 29eb1f2930SHans-Christian Egtvedt 30eb1f2930SHans-Christian Egtvedt /* SSC register offsets */ 31eb1f2930SHans-Christian Egtvedt 32eb1f2930SHans-Christian Egtvedt /* SSC Control Register */ 33eb1f2930SHans-Christian Egtvedt #define SSC_CR 0x00000000 34eb1f2930SHans-Christian Egtvedt #define SSC_CR_RXDIS_SIZE 1 35eb1f2930SHans-Christian Egtvedt #define SSC_CR_RXDIS_OFFSET 1 36eb1f2930SHans-Christian Egtvedt #define SSC_CR_RXEN_SIZE 1 37eb1f2930SHans-Christian Egtvedt #define SSC_CR_RXEN_OFFSET 0 38eb1f2930SHans-Christian Egtvedt #define SSC_CR_SWRST_SIZE 1 39eb1f2930SHans-Christian Egtvedt #define SSC_CR_SWRST_OFFSET 15 40eb1f2930SHans-Christian Egtvedt #define SSC_CR_TXDIS_SIZE 1 41eb1f2930SHans-Christian Egtvedt #define SSC_CR_TXDIS_OFFSET 9 42eb1f2930SHans-Christian Egtvedt #define SSC_CR_TXEN_SIZE 1 43eb1f2930SHans-Christian Egtvedt #define SSC_CR_TXEN_OFFSET 8 44eb1f2930SHans-Christian Egtvedt 45eb1f2930SHans-Christian Egtvedt /* SSC Clock Mode Register */ 46eb1f2930SHans-Christian Egtvedt #define SSC_CMR 0x00000004 47eb1f2930SHans-Christian Egtvedt #define SSC_CMR_DIV_SIZE 12 48eb1f2930SHans-Christian Egtvedt #define SSC_CMR_DIV_OFFSET 0 49eb1f2930SHans-Christian Egtvedt 50eb1f2930SHans-Christian Egtvedt /* SSC Receive Clock Mode Register */ 51eb1f2930SHans-Christian Egtvedt #define SSC_RCMR 0x00000010 52eb1f2930SHans-Christian Egtvedt #define SSC_RCMR_CKG_SIZE 2 53eb1f2930SHans-Christian Egtvedt #define SSC_RCMR_CKG_OFFSET 6 54eb1f2930SHans-Christian Egtvedt #define SSC_RCMR_CKI_SIZE 1 55eb1f2930SHans-Christian Egtvedt #define SSC_RCMR_CKI_OFFSET 5 56eb1f2930SHans-Christian Egtvedt #define SSC_RCMR_CKO_SIZE 3 57eb1f2930SHans-Christian Egtvedt #define SSC_RCMR_CKO_OFFSET 2 58eb1f2930SHans-Christian Egtvedt #define SSC_RCMR_CKS_SIZE 2 59eb1f2930SHans-Christian Egtvedt #define SSC_RCMR_CKS_OFFSET 0 60eb1f2930SHans-Christian Egtvedt #define SSC_RCMR_PERIOD_SIZE 8 61eb1f2930SHans-Christian Egtvedt #define SSC_RCMR_PERIOD_OFFSET 24 62eb1f2930SHans-Christian Egtvedt #define SSC_RCMR_START_SIZE 4 63eb1f2930SHans-Christian Egtvedt #define SSC_RCMR_START_OFFSET 8 64eb1f2930SHans-Christian Egtvedt #define SSC_RCMR_STOP_SIZE 1 65eb1f2930SHans-Christian Egtvedt #define SSC_RCMR_STOP_OFFSET 12 66eb1f2930SHans-Christian Egtvedt #define SSC_RCMR_STTDLY_SIZE 8 67eb1f2930SHans-Christian Egtvedt #define SSC_RCMR_STTDLY_OFFSET 16 68eb1f2930SHans-Christian Egtvedt 69eb1f2930SHans-Christian Egtvedt /* SSC Receive Frame Mode Register */ 70eb1f2930SHans-Christian Egtvedt #define SSC_RFMR 0x00000014 71eb1f2930SHans-Christian Egtvedt #define SSC_RFMR_DATLEN_SIZE 5 72eb1f2930SHans-Christian Egtvedt #define SSC_RFMR_DATLEN_OFFSET 0 73eb1f2930SHans-Christian Egtvedt #define SSC_RFMR_DATNB_SIZE 4 74eb1f2930SHans-Christian Egtvedt #define SSC_RFMR_DATNB_OFFSET 8 75eb1f2930SHans-Christian Egtvedt #define SSC_RFMR_FSEDGE_SIZE 1 76eb1f2930SHans-Christian Egtvedt #define SSC_RFMR_FSEDGE_OFFSET 24 77dfaf5356SBo Shen /* 78dfaf5356SBo Shen * The FSLEN_EXT exist on at91sam9rl, at91sam9g10, 79dfaf5356SBo Shen * at91sam9g20, and at91sam9g45 and newer SoCs 80dfaf5356SBo Shen */ 81dfaf5356SBo Shen #define SSC_RFMR_FSLEN_EXT_SIZE 4 82dfaf5356SBo Shen #define SSC_RFMR_FSLEN_EXT_OFFSET 28 83eb1f2930SHans-Christian Egtvedt #define SSC_RFMR_FSLEN_SIZE 4 84eb1f2930SHans-Christian Egtvedt #define SSC_RFMR_FSLEN_OFFSET 16 85eb1f2930SHans-Christian Egtvedt #define SSC_RFMR_FSOS_SIZE 4 86eb1f2930SHans-Christian Egtvedt #define SSC_RFMR_FSOS_OFFSET 20 87eb1f2930SHans-Christian Egtvedt #define SSC_RFMR_LOOP_SIZE 1 88eb1f2930SHans-Christian Egtvedt #define SSC_RFMR_LOOP_OFFSET 5 89eb1f2930SHans-Christian Egtvedt #define SSC_RFMR_MSBF_SIZE 1 90eb1f2930SHans-Christian Egtvedt #define SSC_RFMR_MSBF_OFFSET 7 91eb1f2930SHans-Christian Egtvedt 92eb1f2930SHans-Christian Egtvedt /* SSC Transmit Clock Mode Register */ 93eb1f2930SHans-Christian Egtvedt #define SSC_TCMR 0x00000018 94eb1f2930SHans-Christian Egtvedt #define SSC_TCMR_CKG_SIZE 2 95eb1f2930SHans-Christian Egtvedt #define SSC_TCMR_CKG_OFFSET 6 96eb1f2930SHans-Christian Egtvedt #define SSC_TCMR_CKI_SIZE 1 97eb1f2930SHans-Christian Egtvedt #define SSC_TCMR_CKI_OFFSET 5 98eb1f2930SHans-Christian Egtvedt #define SSC_TCMR_CKO_SIZE 3 99eb1f2930SHans-Christian Egtvedt #define SSC_TCMR_CKO_OFFSET 2 100eb1f2930SHans-Christian Egtvedt #define SSC_TCMR_CKS_SIZE 2 101eb1f2930SHans-Christian Egtvedt #define SSC_TCMR_CKS_OFFSET 0 102eb1f2930SHans-Christian Egtvedt #define SSC_TCMR_PERIOD_SIZE 8 103eb1f2930SHans-Christian Egtvedt #define SSC_TCMR_PERIOD_OFFSET 24 104eb1f2930SHans-Christian Egtvedt #define SSC_TCMR_START_SIZE 4 105eb1f2930SHans-Christian Egtvedt #define SSC_TCMR_START_OFFSET 8 106eb1f2930SHans-Christian Egtvedt #define SSC_TCMR_STTDLY_SIZE 8 107eb1f2930SHans-Christian Egtvedt #define SSC_TCMR_STTDLY_OFFSET 16 108eb1f2930SHans-Christian Egtvedt 109eb1f2930SHans-Christian Egtvedt /* SSC Transmit Frame Mode Register */ 110eb1f2930SHans-Christian Egtvedt #define SSC_TFMR 0x0000001c 111eb1f2930SHans-Christian Egtvedt #define SSC_TFMR_DATDEF_SIZE 1 112eb1f2930SHans-Christian Egtvedt #define SSC_TFMR_DATDEF_OFFSET 5 113eb1f2930SHans-Christian Egtvedt #define SSC_TFMR_DATLEN_SIZE 5 114eb1f2930SHans-Christian Egtvedt #define SSC_TFMR_DATLEN_OFFSET 0 115eb1f2930SHans-Christian Egtvedt #define SSC_TFMR_DATNB_SIZE 4 116eb1f2930SHans-Christian Egtvedt #define SSC_TFMR_DATNB_OFFSET 8 117eb1f2930SHans-Christian Egtvedt #define SSC_TFMR_FSDEN_SIZE 1 118eb1f2930SHans-Christian Egtvedt #define SSC_TFMR_FSDEN_OFFSET 23 119eb1f2930SHans-Christian Egtvedt #define SSC_TFMR_FSEDGE_SIZE 1 120eb1f2930SHans-Christian Egtvedt #define SSC_TFMR_FSEDGE_OFFSET 24 121dfaf5356SBo Shen /* 122dfaf5356SBo Shen * The FSLEN_EXT exist on at91sam9rl, at91sam9g10, 123dfaf5356SBo Shen * at91sam9g20, and at91sam9g45 and newer SoCs 124dfaf5356SBo Shen */ 125dfaf5356SBo Shen #define SSC_TFMR_FSLEN_EXT_SIZE 4 126dfaf5356SBo Shen #define SSC_TFMR_FSLEN_EXT_OFFSET 28 127eb1f2930SHans-Christian Egtvedt #define SSC_TFMR_FSLEN_SIZE 4 128eb1f2930SHans-Christian Egtvedt #define SSC_TFMR_FSLEN_OFFSET 16 129eb1f2930SHans-Christian Egtvedt #define SSC_TFMR_FSOS_SIZE 3 130eb1f2930SHans-Christian Egtvedt #define SSC_TFMR_FSOS_OFFSET 20 131eb1f2930SHans-Christian Egtvedt #define SSC_TFMR_MSBF_SIZE 1 132eb1f2930SHans-Christian Egtvedt #define SSC_TFMR_MSBF_OFFSET 7 133eb1f2930SHans-Christian Egtvedt 134eb1f2930SHans-Christian Egtvedt /* SSC Receive Hold Register */ 135eb1f2930SHans-Christian Egtvedt #define SSC_RHR 0x00000020 136eb1f2930SHans-Christian Egtvedt #define SSC_RHR_RDAT_SIZE 32 137eb1f2930SHans-Christian Egtvedt #define SSC_RHR_RDAT_OFFSET 0 138eb1f2930SHans-Christian Egtvedt 139eb1f2930SHans-Christian Egtvedt /* SSC Transmit Hold Register */ 140eb1f2930SHans-Christian Egtvedt #define SSC_THR 0x00000024 141eb1f2930SHans-Christian Egtvedt #define SSC_THR_TDAT_SIZE 32 142eb1f2930SHans-Christian Egtvedt #define SSC_THR_TDAT_OFFSET 0 143eb1f2930SHans-Christian Egtvedt 144eb1f2930SHans-Christian Egtvedt /* SSC Receive Sync. Holding Register */ 145eb1f2930SHans-Christian Egtvedt #define SSC_RSHR 0x00000030 146eb1f2930SHans-Christian Egtvedt #define SSC_RSHR_RSDAT_SIZE 16 147eb1f2930SHans-Christian Egtvedt #define SSC_RSHR_RSDAT_OFFSET 0 148eb1f2930SHans-Christian Egtvedt 149eb1f2930SHans-Christian Egtvedt /* SSC Transmit Sync. Holding Register */ 150eb1f2930SHans-Christian Egtvedt #define SSC_TSHR 0x00000034 151eb1f2930SHans-Christian Egtvedt #define SSC_TSHR_TSDAT_SIZE 16 152eb1f2930SHans-Christian Egtvedt #define SSC_TSHR_RSDAT_OFFSET 0 153eb1f2930SHans-Christian Egtvedt 154eb1f2930SHans-Christian Egtvedt /* SSC Receive Compare 0 Register */ 155eb1f2930SHans-Christian Egtvedt #define SSC_RC0R 0x00000038 156eb1f2930SHans-Christian Egtvedt #define SSC_RC0R_CP0_SIZE 16 157eb1f2930SHans-Christian Egtvedt #define SSC_RC0R_CP0_OFFSET 0 158eb1f2930SHans-Christian Egtvedt 159eb1f2930SHans-Christian Egtvedt /* SSC Receive Compare 1 Register */ 160eb1f2930SHans-Christian Egtvedt #define SSC_RC1R 0x0000003c 161eb1f2930SHans-Christian Egtvedt #define SSC_RC1R_CP1_SIZE 16 162eb1f2930SHans-Christian Egtvedt #define SSC_RC1R_CP1_OFFSET 0 163eb1f2930SHans-Christian Egtvedt 164eb1f2930SHans-Christian Egtvedt /* SSC Status Register */ 165eb1f2930SHans-Christian Egtvedt #define SSC_SR 0x00000040 166eb1f2930SHans-Christian Egtvedt #define SSC_SR_CP0_SIZE 1 167eb1f2930SHans-Christian Egtvedt #define SSC_SR_CP0_OFFSET 8 168eb1f2930SHans-Christian Egtvedt #define SSC_SR_CP1_SIZE 1 169eb1f2930SHans-Christian Egtvedt #define SSC_SR_CP1_OFFSET 9 170eb1f2930SHans-Christian Egtvedt #define SSC_SR_ENDRX_SIZE 1 171eb1f2930SHans-Christian Egtvedt #define SSC_SR_ENDRX_OFFSET 6 172eb1f2930SHans-Christian Egtvedt #define SSC_SR_ENDTX_SIZE 1 173eb1f2930SHans-Christian Egtvedt #define SSC_SR_ENDTX_OFFSET 2 174eb1f2930SHans-Christian Egtvedt #define SSC_SR_OVRUN_SIZE 1 175eb1f2930SHans-Christian Egtvedt #define SSC_SR_OVRUN_OFFSET 5 176eb1f2930SHans-Christian Egtvedt #define SSC_SR_RXBUFF_SIZE 1 177eb1f2930SHans-Christian Egtvedt #define SSC_SR_RXBUFF_OFFSET 7 178eb1f2930SHans-Christian Egtvedt #define SSC_SR_RXEN_SIZE 1 179eb1f2930SHans-Christian Egtvedt #define SSC_SR_RXEN_OFFSET 17 180eb1f2930SHans-Christian Egtvedt #define SSC_SR_RXRDY_SIZE 1 181eb1f2930SHans-Christian Egtvedt #define SSC_SR_RXRDY_OFFSET 4 182eb1f2930SHans-Christian Egtvedt #define SSC_SR_RXSYN_SIZE 1 183eb1f2930SHans-Christian Egtvedt #define SSC_SR_RXSYN_OFFSET 11 184eb1f2930SHans-Christian Egtvedt #define SSC_SR_TXBUFE_SIZE 1 185eb1f2930SHans-Christian Egtvedt #define SSC_SR_TXBUFE_OFFSET 3 186eb1f2930SHans-Christian Egtvedt #define SSC_SR_TXEMPTY_SIZE 1 187eb1f2930SHans-Christian Egtvedt #define SSC_SR_TXEMPTY_OFFSET 1 188eb1f2930SHans-Christian Egtvedt #define SSC_SR_TXEN_SIZE 1 189eb1f2930SHans-Christian Egtvedt #define SSC_SR_TXEN_OFFSET 16 190eb1f2930SHans-Christian Egtvedt #define SSC_SR_TXRDY_SIZE 1 191eb1f2930SHans-Christian Egtvedt #define SSC_SR_TXRDY_OFFSET 0 192eb1f2930SHans-Christian Egtvedt #define SSC_SR_TXSYN_SIZE 1 193eb1f2930SHans-Christian Egtvedt #define SSC_SR_TXSYN_OFFSET 10 194eb1f2930SHans-Christian Egtvedt 195eb1f2930SHans-Christian Egtvedt /* SSC Interrupt Enable Register */ 196eb1f2930SHans-Christian Egtvedt #define SSC_IER 0x00000044 197eb1f2930SHans-Christian Egtvedt #define SSC_IER_CP0_SIZE 1 198eb1f2930SHans-Christian Egtvedt #define SSC_IER_CP0_OFFSET 8 199eb1f2930SHans-Christian Egtvedt #define SSC_IER_CP1_SIZE 1 200eb1f2930SHans-Christian Egtvedt #define SSC_IER_CP1_OFFSET 9 201eb1f2930SHans-Christian Egtvedt #define SSC_IER_ENDRX_SIZE 1 202eb1f2930SHans-Christian Egtvedt #define SSC_IER_ENDRX_OFFSET 6 203eb1f2930SHans-Christian Egtvedt #define SSC_IER_ENDTX_SIZE 1 204eb1f2930SHans-Christian Egtvedt #define SSC_IER_ENDTX_OFFSET 2 205eb1f2930SHans-Christian Egtvedt #define SSC_IER_OVRUN_SIZE 1 206eb1f2930SHans-Christian Egtvedt #define SSC_IER_OVRUN_OFFSET 5 207eb1f2930SHans-Christian Egtvedt #define SSC_IER_RXBUFF_SIZE 1 208eb1f2930SHans-Christian Egtvedt #define SSC_IER_RXBUFF_OFFSET 7 209eb1f2930SHans-Christian Egtvedt #define SSC_IER_RXRDY_SIZE 1 210eb1f2930SHans-Christian Egtvedt #define SSC_IER_RXRDY_OFFSET 4 211eb1f2930SHans-Christian Egtvedt #define SSC_IER_RXSYN_SIZE 1 212eb1f2930SHans-Christian Egtvedt #define SSC_IER_RXSYN_OFFSET 11 213eb1f2930SHans-Christian Egtvedt #define SSC_IER_TXBUFE_SIZE 1 214eb1f2930SHans-Christian Egtvedt #define SSC_IER_TXBUFE_OFFSET 3 215eb1f2930SHans-Christian Egtvedt #define SSC_IER_TXEMPTY_SIZE 1 216eb1f2930SHans-Christian Egtvedt #define SSC_IER_TXEMPTY_OFFSET 1 217eb1f2930SHans-Christian Egtvedt #define SSC_IER_TXRDY_SIZE 1 218eb1f2930SHans-Christian Egtvedt #define SSC_IER_TXRDY_OFFSET 0 219eb1f2930SHans-Christian Egtvedt #define SSC_IER_TXSYN_SIZE 1 220eb1f2930SHans-Christian Egtvedt #define SSC_IER_TXSYN_OFFSET 10 221eb1f2930SHans-Christian Egtvedt 222eb1f2930SHans-Christian Egtvedt /* SSC Interrupt Disable Register */ 223eb1f2930SHans-Christian Egtvedt #define SSC_IDR 0x00000048 224eb1f2930SHans-Christian Egtvedt #define SSC_IDR_CP0_SIZE 1 225eb1f2930SHans-Christian Egtvedt #define SSC_IDR_CP0_OFFSET 8 226eb1f2930SHans-Christian Egtvedt #define SSC_IDR_CP1_SIZE 1 227eb1f2930SHans-Christian Egtvedt #define SSC_IDR_CP1_OFFSET 9 228eb1f2930SHans-Christian Egtvedt #define SSC_IDR_ENDRX_SIZE 1 229eb1f2930SHans-Christian Egtvedt #define SSC_IDR_ENDRX_OFFSET 6 230eb1f2930SHans-Christian Egtvedt #define SSC_IDR_ENDTX_SIZE 1 231eb1f2930SHans-Christian Egtvedt #define SSC_IDR_ENDTX_OFFSET 2 232eb1f2930SHans-Christian Egtvedt #define SSC_IDR_OVRUN_SIZE 1 233eb1f2930SHans-Christian Egtvedt #define SSC_IDR_OVRUN_OFFSET 5 234eb1f2930SHans-Christian Egtvedt #define SSC_IDR_RXBUFF_SIZE 1 235eb1f2930SHans-Christian Egtvedt #define SSC_IDR_RXBUFF_OFFSET 7 236eb1f2930SHans-Christian Egtvedt #define SSC_IDR_RXRDY_SIZE 1 237eb1f2930SHans-Christian Egtvedt #define SSC_IDR_RXRDY_OFFSET 4 238eb1f2930SHans-Christian Egtvedt #define SSC_IDR_RXSYN_SIZE 1 239eb1f2930SHans-Christian Egtvedt #define SSC_IDR_RXSYN_OFFSET 11 240eb1f2930SHans-Christian Egtvedt #define SSC_IDR_TXBUFE_SIZE 1 241eb1f2930SHans-Christian Egtvedt #define SSC_IDR_TXBUFE_OFFSET 3 242eb1f2930SHans-Christian Egtvedt #define SSC_IDR_TXEMPTY_SIZE 1 243eb1f2930SHans-Christian Egtvedt #define SSC_IDR_TXEMPTY_OFFSET 1 244eb1f2930SHans-Christian Egtvedt #define SSC_IDR_TXRDY_SIZE 1 245eb1f2930SHans-Christian Egtvedt #define SSC_IDR_TXRDY_OFFSET 0 246eb1f2930SHans-Christian Egtvedt #define SSC_IDR_TXSYN_SIZE 1 247eb1f2930SHans-Christian Egtvedt #define SSC_IDR_TXSYN_OFFSET 10 248eb1f2930SHans-Christian Egtvedt 249eb1f2930SHans-Christian Egtvedt /* SSC Interrupt Mask Register */ 250eb1f2930SHans-Christian Egtvedt #define SSC_IMR 0x0000004c 251eb1f2930SHans-Christian Egtvedt #define SSC_IMR_CP0_SIZE 1 252eb1f2930SHans-Christian Egtvedt #define SSC_IMR_CP0_OFFSET 8 253eb1f2930SHans-Christian Egtvedt #define SSC_IMR_CP1_SIZE 1 254eb1f2930SHans-Christian Egtvedt #define SSC_IMR_CP1_OFFSET 9 255eb1f2930SHans-Christian Egtvedt #define SSC_IMR_ENDRX_SIZE 1 256eb1f2930SHans-Christian Egtvedt #define SSC_IMR_ENDRX_OFFSET 6 257eb1f2930SHans-Christian Egtvedt #define SSC_IMR_ENDTX_SIZE 1 258eb1f2930SHans-Christian Egtvedt #define SSC_IMR_ENDTX_OFFSET 2 259eb1f2930SHans-Christian Egtvedt #define SSC_IMR_OVRUN_SIZE 1 260eb1f2930SHans-Christian Egtvedt #define SSC_IMR_OVRUN_OFFSET 5 261eb1f2930SHans-Christian Egtvedt #define SSC_IMR_RXBUFF_SIZE 1 262eb1f2930SHans-Christian Egtvedt #define SSC_IMR_RXBUFF_OFFSET 7 263eb1f2930SHans-Christian Egtvedt #define SSC_IMR_RXRDY_SIZE 1 264eb1f2930SHans-Christian Egtvedt #define SSC_IMR_RXRDY_OFFSET 4 265eb1f2930SHans-Christian Egtvedt #define SSC_IMR_RXSYN_SIZE 1 266eb1f2930SHans-Christian Egtvedt #define SSC_IMR_RXSYN_OFFSET 11 267eb1f2930SHans-Christian Egtvedt #define SSC_IMR_TXBUFE_SIZE 1 268eb1f2930SHans-Christian Egtvedt #define SSC_IMR_TXBUFE_OFFSET 3 269eb1f2930SHans-Christian Egtvedt #define SSC_IMR_TXEMPTY_SIZE 1 270eb1f2930SHans-Christian Egtvedt #define SSC_IMR_TXEMPTY_OFFSET 1 271eb1f2930SHans-Christian Egtvedt #define SSC_IMR_TXRDY_SIZE 1 272eb1f2930SHans-Christian Egtvedt #define SSC_IMR_TXRDY_OFFSET 0 273eb1f2930SHans-Christian Egtvedt #define SSC_IMR_TXSYN_SIZE 1 274eb1f2930SHans-Christian Egtvedt #define SSC_IMR_TXSYN_OFFSET 10 275eb1f2930SHans-Christian Egtvedt 276eb1f2930SHans-Christian Egtvedt /* SSC PDC Receive Pointer Register */ 277eb1f2930SHans-Christian Egtvedt #define SSC_PDC_RPR 0x00000100 278eb1f2930SHans-Christian Egtvedt 279eb1f2930SHans-Christian Egtvedt /* SSC PDC Receive Counter Register */ 280eb1f2930SHans-Christian Egtvedt #define SSC_PDC_RCR 0x00000104 281eb1f2930SHans-Christian Egtvedt 282eb1f2930SHans-Christian Egtvedt /* SSC PDC Transmit Pointer Register */ 283eb1f2930SHans-Christian Egtvedt #define SSC_PDC_TPR 0x00000108 284eb1f2930SHans-Christian Egtvedt 285eb1f2930SHans-Christian Egtvedt /* SSC PDC Receive Next Pointer Register */ 286eb1f2930SHans-Christian Egtvedt #define SSC_PDC_RNPR 0x00000110 287eb1f2930SHans-Christian Egtvedt 288eb1f2930SHans-Christian Egtvedt /* SSC PDC Receive Next Counter Register */ 289eb1f2930SHans-Christian Egtvedt #define SSC_PDC_RNCR 0x00000114 290eb1f2930SHans-Christian Egtvedt 291eb1f2930SHans-Christian Egtvedt /* SSC PDC Transmit Counter Register */ 292eb1f2930SHans-Christian Egtvedt #define SSC_PDC_TCR 0x0000010c 293eb1f2930SHans-Christian Egtvedt 294eb1f2930SHans-Christian Egtvedt /* SSC PDC Transmit Next Pointer Register */ 295eb1f2930SHans-Christian Egtvedt #define SSC_PDC_TNPR 0x00000118 296eb1f2930SHans-Christian Egtvedt 297eb1f2930SHans-Christian Egtvedt /* SSC PDC Transmit Next Counter Register */ 298eb1f2930SHans-Christian Egtvedt #define SSC_PDC_TNCR 0x0000011c 299eb1f2930SHans-Christian Egtvedt 300eb1f2930SHans-Christian Egtvedt /* SSC PDC Transfer Control Register */ 301eb1f2930SHans-Christian Egtvedt #define SSC_PDC_PTCR 0x00000120 302eb1f2930SHans-Christian Egtvedt #define SSC_PDC_PTCR_RXTDIS_SIZE 1 303eb1f2930SHans-Christian Egtvedt #define SSC_PDC_PTCR_RXTDIS_OFFSET 1 304eb1f2930SHans-Christian Egtvedt #define SSC_PDC_PTCR_RXTEN_SIZE 1 305eb1f2930SHans-Christian Egtvedt #define SSC_PDC_PTCR_RXTEN_OFFSET 0 306eb1f2930SHans-Christian Egtvedt #define SSC_PDC_PTCR_TXTDIS_SIZE 1 307eb1f2930SHans-Christian Egtvedt #define SSC_PDC_PTCR_TXTDIS_OFFSET 9 308eb1f2930SHans-Christian Egtvedt #define SSC_PDC_PTCR_TXTEN_SIZE 1 309eb1f2930SHans-Christian Egtvedt #define SSC_PDC_PTCR_TXTEN_OFFSET 8 310eb1f2930SHans-Christian Egtvedt 311eb1f2930SHans-Christian Egtvedt /* SSC PDC Transfer Status Register */ 312eb1f2930SHans-Christian Egtvedt #define SSC_PDC_PTSR 0x00000124 313eb1f2930SHans-Christian Egtvedt #define SSC_PDC_PTSR_RXTEN_SIZE 1 314eb1f2930SHans-Christian Egtvedt #define SSC_PDC_PTSR_RXTEN_OFFSET 0 315eb1f2930SHans-Christian Egtvedt #define SSC_PDC_PTSR_TXTEN_SIZE 1 316eb1f2930SHans-Christian Egtvedt #define SSC_PDC_PTSR_TXTEN_OFFSET 8 317eb1f2930SHans-Christian Egtvedt 318eb1f2930SHans-Christian Egtvedt /* Bit manipulation macros */ 319eb1f2930SHans-Christian Egtvedt #define SSC_BIT(name) \ 320eb1f2930SHans-Christian Egtvedt (1 << SSC_##name##_OFFSET) 321eb1f2930SHans-Christian Egtvedt #define SSC_BF(name, value) \ 322eb1f2930SHans-Christian Egtvedt (((value) & ((1 << SSC_##name##_SIZE) - 1)) \ 323eb1f2930SHans-Christian Egtvedt << SSC_##name##_OFFSET) 324eb1f2930SHans-Christian Egtvedt #define SSC_BFEXT(name, value) \ 325eb1f2930SHans-Christian Egtvedt (((value) >> SSC_##name##_OFFSET) \ 326eb1f2930SHans-Christian Egtvedt & ((1 << SSC_##name##_SIZE) - 1)) 327eb1f2930SHans-Christian Egtvedt #define SSC_BFINS(name, value, old) \ 328eb1f2930SHans-Christian Egtvedt (((old) & ~(((1 << SSC_##name##_SIZE) - 1) \ 329eb1f2930SHans-Christian Egtvedt << SSC_##name##_OFFSET)) | SSC_BF(name, value)) 330eb1f2930SHans-Christian Egtvedt 331eb1f2930SHans-Christian Egtvedt /* Register access macros */ 332eb1f2930SHans-Christian Egtvedt #define ssc_readl(base, reg) __raw_readl(base + SSC_##reg) 333eb1f2930SHans-Christian Egtvedt #define ssc_writel(base, reg, value) __raw_writel((value), base + SSC_##reg) 334eb1f2930SHans-Christian Egtvedt 335eb1f2930SHans-Christian Egtvedt #endif /* __INCLUDE_ATMEL_SSC_H */ 336