Revision tags: v6.6.25, v6.6.24, v6.6.23 |
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#
c69d3928 |
| 16-Feb-2024 |
Peter Robinson <pbrobinson@gmail.com> |
bus: tegra-aconnect: Update dependency to ARCH_TEGRA
[ Upstream commit 4acd21a45c1446277e2abaece97d7fa7c2e692a9 ]
Update the architecture dependency to be the generic Tegra because the driver works
bus: tegra-aconnect: Update dependency to ARCH_TEGRA
[ Upstream commit 4acd21a45c1446277e2abaece97d7fa7c2e692a9 ]
Update the architecture dependency to be the generic Tegra because the driver works on the four latest Tegra generations not just Tegra210, if you build a kernel with a specific ARCH_TEGRA_xxx_SOC option that excludes Tegra210 you don't get this driver.
Fixes: 46a88534afb59 ("bus: Add support for Tegra ACONNECT") Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Cc: Jon Hunter <jonathanh@nvidia.com> Cc: Thierry Reding <treding@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
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Revision tags: v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5, v6.6.4, v6.6.3, v6.6.2, v6.5.11, v6.6.1, v6.5.10, v6.6, v6.5.9, v6.5.8, v6.5.7, v6.5.6, v6.5.5, v6.5.4, v6.5.3, v6.5.2, v6.1.51, v6.5.1, v6.1.50, v6.5, v6.1.49, v6.1.48, v6.1.46, v6.1.45, v6.1.44 |
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063dc062 |
| 04-Aug-2023 |
Tony Lindgren <tony@atomide.com> |
bus: ti-sysc: Build driver for TI K3 SoCs
Allow building ti-sysc also for K3 SoCs. This allows configuring the wkup domain devices for SYSCONFIG register wake-up events in a generic way.
As this is
bus: ti-sysc: Build driver for TI K3 SoCs
Allow building ti-sysc also for K3 SoCs. This allows configuring the wkup domain devices for SYSCONFIG register wake-up events in a generic way.
As this is an interconnect level driver, default to built-in on K3 SoCs to probe the devices connected to the wkup domain like gpio, uart and timers.
Reviewed-by: Dhruva Gole <d-gole@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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Revision tags: v6.1.43, v6.1.42, v6.1.41, v6.1.40, v6.1.39, v6.1.38, v6.1.37, v6.1.36, v6.4, v6.1.35, v6.1.34, v6.1.33, v6.1.32, v6.1.31, v6.1.30, v6.1.29, v6.1.28, v6.1.27, v6.1.26, v6.3, v6.1.25, v6.1.24, v6.1.23, v6.1.22 |
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fcbfe812 |
| 23-Mar-2023 |
Niklas Schnelle <schnelle@linux.ibm.com> |
Kconfig: introduce HAS_IOPORT option and select it as necessary
We introduce a new HAS_IOPORT Kconfig option to indicate support for I/O Port access. In a future patch HAS_IOPORT=n will disable comp
Kconfig: introduce HAS_IOPORT option and select it as necessary
We introduce a new HAS_IOPORT Kconfig option to indicate support for I/O Port access. In a future patch HAS_IOPORT=n will disable compilation of the I/O accessor functions inb()/outb() and friends on architectures which can not meaningfully support legacy I/O spaces such as s390.
The following architectures do not select HAS_IOPORT:
* ARC * C-SKY * Hexagon * Nios II * OpenRISC * s390 * User-Mode Linux * Xtensa
All other architectures select HAS_IOPORT at least conditionally.
The "depends on" relations on HAS_IOPORT in drivers as well as ifdefs for HAS_IOPORT specific sections will be added in subsequent patches on a per subsystem basis.
Co-developed-by: Arnd Bergmann <arnd@kernel.org> Signed-off-by: Arnd Bergmann <arnd@kernel.org> Acked-by: Johannes Berg <johannes@sipsolutions.net> # for ARCH=um Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Niklas Schnelle <schnelle@linux.ibm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Revision tags: v6.1.21, v6.1.20, v6.1.19, v6.1.18, v6.1.17, v6.1.16, v6.1.15, v6.1.14, v6.1.13, v6.2, v6.1.12, v6.1.11, v6.1.10, v6.1.9, v6.1.8, v6.1.7, v6.1.6, v6.1.5, v6.0.19, v6.0.18, v6.1.4, v6.1.3, v6.0.17, v6.1.2, v6.0.16, v6.1.1, v6.0.15, v6.0.14, v6.0.13, v6.1, v6.0.12, v6.0.11, v6.0.10, v5.15.80, v6.0.9, v5.15.79, v6.0.8, v5.15.78, v6.0.7, v5.15.77, v5.15.76, v6.0.6, v6.0.5, v5.15.75, v6.0.4, v6.0.3, v6.0.2, v5.15.74, v5.15.73, v6.0.1, v5.15.72, v6.0, v5.15.71, v5.15.70, v5.15.69, v5.15.68, v5.15.67, v5.15.66, v5.15.65, v5.15.64, v5.15.63, v5.15.62, v5.15.61, v5.15.60, v5.15.59, v5.19, v5.15.58, v5.15.57, v5.15.56, v5.15.55, v5.15.54, v5.15.53, v5.15.52, v5.15.51, v5.15.50, v5.15.49, v5.15.48, v5.15.47, v5.15.46, v5.15.45, v5.15.44, v5.15.43, v5.15.42, v5.18, v5.15.41, v5.15.40, v5.15.39, v5.15.38, v5.15.37, v5.15.36, v5.15.35, v5.15.34 |
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#
97d485ed |
| 11-Apr-2022 |
Michael Srba <Michael.Srba@seznam.cz> |
bus: add driver for initializing the SSC bus on (some) qcom SoCs
Add bindings for the AHB bus which exposes the SSC (Snapdragon Sensor Core) block in the global address space. This bus (and the SSC
bus: add driver for initializing the SSC bus on (some) qcom SoCs
Add bindings for the AHB bus which exposes the SSC (Snapdragon Sensor Core) block in the global address space. This bus (and the SSC block itself) is present on certain qcom SoCs.
In typical configuration, this bus (as some of the clocks and registers that we need to manipulate) is not accessible to Linux, and the resources on this bus are indirectly accessed by communicating with a hexagon CPU core residing in the SSC block. In this configuration, the hypervisor is the one performing the bus initialization for the purposes of bringing the hexagon CPU core out of reset.
However, it is possible to change the configuration, in which case this driver will initialize the bus.
In combination with drivers for resources on the SSC bus, this driver can aid in debugging, and for example with a TLMM driver can be used to directly access SSC-dedicated GPIO pins, removing the need to commit to a particular usecase during hw design.
Finally, until open firmware for the hexagon core is available, this approach allows for using sensors hooked up to SSC-dedicated GPIO pins on mainline Linux simply by utilizing the existing in-tree drivers for these sensors.
Signed-off-by: Michael Srba <Michael.Srba@seznam.cz> Reviewed-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220411072156.24451-5-michael.srba@seznam.cz
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Revision tags: v5.15.33, v5.15.32, v5.15.31, v5.17, v5.15.30, v5.15.29, v5.15.28, v5.15.27, v5.15.26, v5.15.25, v5.15.24, v5.15.23, v5.15.22, v5.15.21, v5.15.20, v5.15.19, v5.15.18, v5.15.17, v5.4.173, v5.15.16, v5.15.15, v5.16, v5.15.10, v5.15.9, v5.15.8, v5.15.7, v5.15.6, v5.15.5, v5.15.4, v5.15.3, v5.15.2, v5.15.1, v5.15, v5.14.14, v5.14.13, v5.14.12, v5.14.11, v5.14.10, v5.14.9, v5.14.8 |
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707a4cdf |
| 24-Sep-2021 |
Florian Fainelli <f.fainelli@gmail.com> |
bus: brcmstb_gisb: Allow building as module
Allow building the Broadcom STB GISB arbiter driver as a module, however similar to interrupt controller drivers, don't allow its unbind/removal since it
bus: brcmstb_gisb: Allow building as module
Allow building the Broadcom STB GISB arbiter driver as a module, however similar to interrupt controller drivers, don't allow its unbind/removal since it is not quite prepared for that and we want it to catch bus errors all the time.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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81967efb |
| 28-Sep-2021 |
Saravana Kannan <saravanak@google.com> |
drivers: bus: Delete CONFIG_SIMPLE_PM_BUS
The simple-pm-bus driver is mandatory for CONFIG_OF based platforms to work with fw_devlink. So, always compile it in for CONFIG_OF and delete the config si
drivers: bus: Delete CONFIG_SIMPLE_PM_BUS
The simple-pm-bus driver is mandatory for CONFIG_OF based platforms to work with fw_devlink. So, always compile it in for CONFIG_OF and delete the config since it's no longer necessary.
Tested-by: Ulf Hansson <ulf.hansson@linaro.org> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Damien Le Moal <damien.lemoal@wdc.com> Cc: Rob Herring <robh+dt@kernel.org> Signed-off-by: Saravana Kannan <saravanak@google.com> Link: https://lore.kernel.org/r/20210929000735.585237-3-saravanak@google.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Revision tags: v5.14.7, v5.14.6, v5.10.67, v5.10.66, v5.14.5, v5.14.4, v5.10.65, v5.14.3, v5.10.64, v5.14.2, v5.10.63, v5.14.1, v5.10.62, v5.14, v5.10.61, v5.10.60, v5.10.53, v5.10.52, v5.10.51 |
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1c953bda |
| 15-Jul-2021 |
Linus Walleij <linus.walleij@linaro.org> |
bus: ixp4xx: Add a driver for IXP4xx expansion bus
The Intel IXP4xx SoCs have an expansion bus that is usually just used for flash memory and configured by the boot loaders and can be accessed using
bus: ixp4xx: Add a driver for IXP4xx expansion bus
The Intel IXP4xx SoCs have an expansion bus that is usually just used for flash memory and configured by the boot loaders and can be accessed using the "simple-bus".
However some devices need more elaborate configuration and then we need to provide a proper 3-unit address space indicating chip select for each device and provide timing and similar information.
Cc: Marc Zyngier <maz@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Revision tags: v5.10.50, v5.10.49, v5.13, v5.10.46, v5.10.43, v5.10.42, v5.10.41, v5.10.40, v5.10.39, v5.4.119, v5.10.36, v5.10.35, v5.10.34, v5.4.116, v5.10.33, v5.12, v5.10.32, v5.10.31, v5.10.30, v5.10.27, v5.10.26, v5.10.25, v5.10.24, v5.10.23, v5.10.22, v5.10.21, v5.10.20, v5.10.19, v5.4.101, v5.10.18, v5.10.17, v5.11, v5.10.16, v5.10.15, v5.10.14 |
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a579fcfa |
| 18-Jan-2021 |
Arnd Bergmann <arnd@arndb.de> |
c6x: remove architecture
The c6x architecture was added to the kernel in 2011 at a time when running Linux on DSPs was widely seen as the logical evolution. It appears the trend has gone back to run
c6x: remove architecture
The c6x architecture was added to the kernel in 2011 at a time when running Linux on DSPs was widely seen as the logical evolution. It appears the trend has gone back to running Linux on Arm based SoCs with DSP, using a better supported software ecosystem, and having better real-time behavior for the DSP code. An example of this is TI's own Keystone2 platform.
The upstream kernel port appears to no longer have any users. Mark Salter remained avaialable to review patches, but mentioned that he no longer has access to working hardware himself. Without any users, it's best to just remove the code completely to reduce the work for cross-architecture code changes.
Many thanks to Mark for maintaining the code for the past ten years.
Link: https://lore.kernel.org/lkml/41dc7795afda9f776d8cd0d3075f776cf586e97c.camel@redhat.com/ Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Revision tags: v5.10, v5.8.17, v5.8.16, v5.8.15, v5.9, v5.8.14, v5.8.13, v5.8.12, v5.8.11, v5.8.10, v5.8.9, v5.8.8, v5.8.7, v5.8.6, v5.4.62, v5.8.5, v5.8.4, v5.4.61, v5.8.3, v5.4.60, v5.8.2, v5.4.59, v5.8.1, v5.4.58, v5.4.57, v5.4.56, v5.8, v5.7.12, v5.4.55, v5.7.11, v5.4.54, v5.7.10, v5.4.53, v5.4.52, v5.7.9 |
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16274e58 |
| 14-Jul-2020 |
Serge Semin <Sergey.Semin@baikalelectronics.ru> |
bus: cdmm: Add MIPS R5 arch support
CDMM may be available not only on MIPS R2 architectures, but also on newer MIPS R5 chips. For instance our P5600 chip has one. Let's mark the CDMM bus being suppo
bus: cdmm: Add MIPS R5 arch support
CDMM may be available not only on MIPS R2 architectures, but also on newer MIPS R5 chips. For instance our P5600 chip has one. Let's mark the CDMM bus being supported for that MIPS arch too.
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Reviewed-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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Revision tags: v5.7.8, v5.4.51, v5.4.50, v5.7.7, v5.4.49, v5.7.6, v5.7.5, v5.4.48, v5.7.4, v5.7.3, v5.4.47, v5.4.46, v5.7.2, v5.4.45, v5.7.1, v5.4.44, v5.7 |
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22e795b4 |
| 28-May-2020 |
Serge Semin <Sergey.Semin@baikalelectronics.ru> |
bus: bt1-axi: Build the driver into the kernel
Alas the method trigger_all_cpu_backtrace() isn't exported by the kernel, but we need to have it called in case of the bus errors detected to get a bet
bus: bt1-axi: Build the driver into the kernel
Alas the method trigger_all_cpu_backtrace() isn't exported by the kernel, but we need to have it called in case of the bus errors detected to get a better description of a possible cause of the error. Let's disable the ability to build the driver as a loadable kernel module then. Note In future the driver will support the AXI-bus interconnect capability, so we'd have to make it built into the kernel anyway.
Link: https://lore.kernel.org/r/20200528193113.17372-2-Sergey.Semin@baikalelectronics.ru Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru> Cc: Olof Johansson <olof@lixom.net> Cc: soc@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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dc20e93b |
| 28-May-2020 |
Serge Semin <Sergey.Semin@baikalelectronics.ru> |
bus: bt1-apb: Build the driver into the kernel
Seeing trigger_all_cpu_backtrace() isn't exported from the kernel and since calling it is a very important part of driver, which may provide a better d
bus: bt1-apb: Build the driver into the kernel
Seeing trigger_all_cpu_backtrace() isn't exported from the kernel and since calling it is a very important part of driver, which may provide a better description of a possible cause of the error, let's disable the ability to build the driver as a loadable kernel module.
Link: https://lore.kernel.org/r/20200528193113.17372-1-Sergey.Semin@baikalelectronics.ru Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru> Cc: Olof Johansson <olof@lixom.net> Cc: soc@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Revision tags: v5.4.43 |
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8f93662d |
| 26-May-2020 |
Serge Semin <Sergey.Semin@baikalelectronics.ru> |
bus: Add Baikal-T1 APB-bus driver
Baikal-T1 AXI-APB bridge is used to access the SoC subsystem CSRs. IO requests are routed to this bus by means of the DW AMBA 3 AXI Interconnect. In case if an atte
bus: Add Baikal-T1 APB-bus driver
Baikal-T1 AXI-APB bridge is used to access the SoC subsystem CSRs. IO requests are routed to this bus by means of the DW AMBA 3 AXI Interconnect. In case if an attempted APB transaction stays with no response for a pre-defined time an interrupt occurs and the bus gets freed for a next operation. This driver provides the interrupt handler to detect the erroneous address, prints an error message about the address fault, updates an errors counter. The counter and the APB-bus operations timeout can be accessed via corresponding sysfs nodes. A dedicated sysfs-node can be also used to artificially cause the bus errors described above.
[arnd: fix build warnings for missing includes and wrong return types]
Link: https://lore.kernel.org/r/20200526125928.17096-6-Sergey.Semin@baikalelectronics.ru Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru> Cc: Paul Burton <paulburton@kernel.org> Cc: Olof Johansson <olof@lixom.net> Cc: Rob Herring <robh+dt@kernel.org> Cc: linux-mips@vger.kernel.org Cc: soc@kernel.org Cc: devicetree@vger.kernel.org Reported-by: kbuild test robot <lkp@intel.com> Reported-by: kbuild test robot <lkp@intel.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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#
63cb7713 |
| 26-May-2020 |
Serge Semin <Sergey.Semin@baikalelectronics.ru> |
bus: Add Baikal-T1 AXI-bus driver
AXI3-bus is the main communication bus connecting all high-speed peripheral IP-cores with RAM controller and MIPS P5600 cores on Baikal-T1 SoC. Bus traffic arbitrat
bus: Add Baikal-T1 AXI-bus driver
AXI3-bus is the main communication bus connecting all high-speed peripheral IP-cores with RAM controller and MIPS P5600 cores on Baikal-T1 SoC. Bus traffic arbitration is done by means of DW AMBA 3 AXI Interconnect (so called AXI Main Interconnect) routing IO requests from one SoC block to another. This driver provides a way to detect any bus protocol errors and device not responding situations by means of an embedded on top of the interconnect errors handler block (EHB). AXI Interconnect QoS arbitration tuning is currently unsupported. The bus doesn't provide a way to detect the interconnected devices, so they are supposed to be statically defined like by means of the simple-bus sub-nodes.
[arnd: fix build warnings for missing includes and wrong return types]
Link: https://lore.kernel.org/r/20200526125928.17096-5-Sergey.Semin@baikalelectronics.ru Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru> Cc: Paul Burton <paulburton@kernel.org> Cc: Olof Johansson <olof@lixom.net> Cc: Rob Herring <robh+dt@kernel.org> Cc: linux-mips@vger.kernel.org Cc: soc@kernel.org Cc: devicetree@vger.kernel.org Reported-by: kbuild test robot <lkp@intel.com> Reported-by: kbuild test robot <lkp@intel.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Revision tags: v5.4.42, v5.4.41, v5.4.40, v5.4.39, v5.4.38, v5.4.37 |
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70e4758a |
| 29-Apr-2020 |
Rob Herring <robh@kernel.org> |
bus: vexpress-config: Support building as module
Enable building vexpress-config driver as a module.
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Linus Walleij <linus.walleij@linaro.org> C
bus: vexpress-config: Support building as module
Enable building vexpress-config driver as a module.
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Reviewed-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Liviu Dudau <liviu.dudau@arm.com> Signed-off-by: Rob Herring <robh@kernel.org>
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Revision tags: v5.4.36, v5.4.35, v5.4.34, v5.4.33, v5.4.32, v5.4.31, v5.4.30, v5.4.29, v5.6, v5.4.28, v5.4.27, v5.4.26, v5.4.25, v5.4.24, v5.4.23, v5.4.22, v5.4.21, v5.4.20 |
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ccea5e8a |
| 13-Feb-2020 |
Linus Walleij <linus.walleij@linaro.org> |
bus: Add driver for Integrator/AP logic modules
The logic modules on the Integrator/AP (Application Platform) are logic tiles with (typically) one or a few peripheral devices. They are most commonly
bus: Add driver for Integrator/AP logic modules
The logic modules on the Integrator/AP (Application Platform) are logic tiles with (typically) one or a few peripheral devices. They are most commonly used for FPGA prototyping.
Using the device tree node for logic tiles, we probe them in order and check if the special system controller register confirm their presence before populating the node for a tile.
This supercedes the code in arch/arm/mach-integrator/lm.[c|h] and makes it possible to populate the tiles using the device tree instead of boardfile-based descriptions.
Tested with all peripherals including graphics and MMC card working fine with the IM-PD1 example tile from Arm.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
0cbf2608 |
| 20-Feb-2020 |
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> |
bus: mhi: core: Add support for registering MHI controllers
This commit adds support for registering MHI controller drivers with the MHI stack. MHI controller drivers manages the interaction with th
bus: mhi: core: Add support for registering MHI controllers
This commit adds support for registering MHI controller drivers with the MHI stack. MHI controller drivers manages the interaction with the MHI client devices such as the external modems and WiFi chipsets. They are also the MHI bus master in charge of managing the physical link between the host and client device.
This is based on the patch submitted by Sujeev Dias: https://lkml.org/lkml/2018/7/9/987
Signed-off-by: Sujeev Dias <sdias@codeaurora.org> Signed-off-by: Siddartha Mohanadoss <smohanad@codeaurora.org> [jhugo: added static config for controllers and fixed several bugs] Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org> [mani: removed DT dependency, splitted and cleaned up for upstream] Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20200220095854.4804-3-manivannan.sadhasivam@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Revision tags: v5.4.19, v5.4.18, v5.4.17, v5.4.16, v5.5, v5.4.15, v5.4.14, v5.4.13, v5.4.12, v5.4.11, v5.4.10, v5.4.9, v5.4.8, v5.4.7, v5.4.6, v5.4.5, v5.4.4, v5.4.3, v5.3.15, v5.4.2, v5.4.1, v5.3.14, v5.4, v5.3.13, v5.3.12, v5.3.11, v5.3.10, v5.3.9, v5.3.8, v5.3.7, v5.3.6, v5.3.5, v5.3.4, v5.3.3, v5.3.2, v5.3.1, v5.3, v5.2.14, v5.3-rc8, v5.2.13, v5.2.12, v5.2.11, v5.2.10, v5.2.9, v5.2.8, v5.2.7, v5.2.6, v5.2.5, v5.2.4, v5.2.3, v5.2.2, v5.2.1, v5.2, v5.1.16, v5.1.15, v5.1.14, v5.1.13 |
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2f56acf8 |
| 20-Jun-2019 |
Sameer Pujar <spujar@nvidia.com> |
bus: tegra-aconnect: Remove PM_CLK dependency
The ACONNECT bus driver does not use pm-clk interface anymore and hence the dependency can be removed from its Kconfig option.
Fixes: 0d7dab926130 ("bu
bus: tegra-aconnect: Remove PM_CLK dependency
The ACONNECT bus driver does not use pm-clk interface anymore and hence the dependency can be removed from its Kconfig option.
Fixes: 0d7dab926130 ("bus: tegra-aconnect: use devm_clk_*() helpers") Signed-off-by: Sameer Pujar <spujar@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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3e5cd20d |
| 04-Nov-2019 |
John Garry <john.garry@huawei.com> |
bus: hisi_lpc: Expand build test coverage
Currently the driver will only ever be built for ARM64 because it selects CONFIG_INDIRECT_PIO, which itself depends on ARM64.
Expand build test coverage fo
bus: hisi_lpc: Expand build test coverage
Currently the driver will only ever be built for ARM64 because it selects CONFIG_INDIRECT_PIO, which itself depends on ARM64.
Expand build test coverage for the driver to other architectures by only selecting CONFIG_INDIRECT_PIO for ARM64, when we really want it.
We don't include ALPHA, C6X, HEXAGON, and PARISC architectures as they don't define {read, write}sb.
Signed-off-by: John Garry <john.garry@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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f213729f |
| 01-Sep-2019 |
David Lechner <david@lechnology.com> |
counter: new TI eQEP driver
This adds a new counter driver for the Texas Instruments Enhanced Quadrature Encoder Pulse (eQEP) module.
Only very basic functionality is currently implemented - only e
counter: new TI eQEP driver
This adds a new counter driver for the Texas Instruments Enhanced Quadrature Encoder Pulse (eQEP) module.
Only very basic functionality is currently implemented - only enough to be able to read the position. The actual device has many more features which can be added to the driver on an as-needed basis.
It is not possible to read the QEPA/B signal values in hardware, so that feature is omitted.
The TI_PWMSS kernel option is selected in Kconfig to enable the parent bus, which is needed for power management.
Signed-off-by: David Lechner <david@lechnology.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
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7cabf925 |
| 01-Sep-2019 |
David Lechner <david@lechnology.com> |
bus/ti-pwmss: move TI PWMSS driver from PWM to bus subsystem
The TI PWMSS driver is a simple bus driver for providing power power management for the PWM peripherals on TI AM33xx SoCs, namely eCAP, e
bus/ti-pwmss: move TI PWMSS driver from PWM to bus subsystem
The TI PWMSS driver is a simple bus driver for providing power power management for the PWM peripherals on TI AM33xx SoCs, namely eCAP, eHRPWM and eQEP. The eQEP is a counter rather than a PWM, so it does not make sense to have the bus driver in the PWM subsystem since the PWMSS is not exclusive to PWM devices.
Signed-off-by: David Lechner <david@lechnology.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
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5bc7f990 |
| 12-Aug-2019 |
Marek Behún <marek.behun@nic.cz> |
bus: Add support for Moxtet bus
On the Turris Mox router different modules can be connected to the main CPU board: currently a module with a SFP cage, a module with MiniPCIe connector, a PCIe pass-t
bus: Add support for Moxtet bus
On the Turris Mox router different modules can be connected to the main CPU board: currently a module with a SFP cage, a module with MiniPCIe connector, a PCIe pass-through MiniPCIe connector module, a 4-port switch module, an 8-port switch module, and a 4-port USB3 module.
For example: [CPU]-[PCIe-pass-through]-[PCIe]-[8-port switch]-[8-port switch]-[SFP]
Each of this modules has an input and output shift register, and these are connected via SPI to the CPU board.
Via SPI we are able to discover which modules are connected, in which order, and we can also read some information about the modules (eg. their interrupt status), and configure them. From each module 8 bits can be read (of which low 4 bits identify the module) and 8 bits can be written.
For example from the module with a SFP cage we can read the LOS, TX-FAULT and MOD-DEF0 signals, while we can write TX-DISABLE and RATE-SELECT signals.
This driver creates a new bus type, called "moxtet". For each Mox module it finds via SPI, it creates a new device on the moxtet bus so that drivers can be written for them.
It also implements a virtual interrupt controller for the modules which send their interrupt status over the SPI shift register. These modules do this in addition to sending their interrupt status via the shared interrupt line. When the shared interrupt is triggered, we read from the shift register and handle IRQs for all devices which are in interrupt.
The topology of how Mox modules are connected can then be read by listing /sys/bus/moxtet/devices.
Link: https://lore.kernel.org/r/20190812161118.21476-2-marek.behun@nic.cz Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Revision tags: v5.1.12, v5.1.11, v5.1.10, v5.1.9, v5.1.8, v5.1.7, v5.1.6, v5.1.5, v5.1.4, v5.1.3, v5.1.2, v5.1.1, v5.0.14, v5.1, v5.0.13, v5.0.12, v5.0.11, v5.0.10, v5.0.9, v5.0.8, v5.0.7, v5.0.6, v5.0.5, v5.0.4, v5.0.3, v4.19.29, v5.0.2, v4.19.28, v5.0.1, v4.19.27, v5.0, v4.19.26, v4.19.25, v4.19.24, v4.19.23, v4.19.22, v4.19.21, v4.19.20, v4.19.19, v4.19.18, v4.19.17, v4.19.16, v4.19.15, v4.19.14, v4.19.13, v4.19.12, v4.19.11, v4.19.10, v4.19.9, v4.19.8, v4.19.7, v4.19.6, v4.19.5, v4.19.4, v4.18.20, v4.19.3, v4.18.19, v4.19.2, v4.18.18, v4.18.17, v4.19.1, v4.19, v4.18.16, v4.18.15, v4.18.14, v4.18.13, v4.18.12, v4.18.11, v4.18.10, v4.18.9, v4.18.7, v4.18.6, v4.18.5, v4.17.18, v4.18.4, v4.18.3, v4.17.17, v4.18.2, v4.17.16, v4.17.15, v4.18.1, v4.18, v4.17.14, v4.17.13, v4.17.12, v4.17.11, v4.17.10, v4.17.9, v4.17.8, v4.17.7, v4.17.6, v4.17.5, v4.17.4, v4.17.3 |
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8818e865 |
| 22-Jun-2018 |
Icenowy Zheng <icenowy@aosc.io> |
bus: add bus driver for accessing Allwinner A64 DE2
The "Display Engine 2.0" (usually called DE2) on the Allwinner A64 SoC is different from the ones on other Allwinner SoCs. It requires a SRAM regi
bus: add bus driver for accessing Allwinner A64 DE2
The "Display Engine 2.0" (usually called DE2) on the Allwinner A64 SoC is different from the ones on other Allwinner SoCs. It requires a SRAM region to be claimed, otherwise all DE2 subblocks won't be accessible.
Add a bus driver for the Allwinner A64 DE2 part which claims the SRAM region when probing.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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Revision tags: v4.17.2, v4.17.1, v4.17 |
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332f632e |
| 08-May-2018 |
John Garry <john.garry@huawei.com> |
HISI LPC: Stop using MFD APIs
The MFD APIs should only be used by drivers in drivers/mfd. It is not worth splitting the driver to have separate parts in drivers/bus and drivers/mfd, so just drop MFD
HISI LPC: Stop using MFD APIs
The MFD APIs should only be used by drivers in drivers/mfd. It is not worth splitting the driver to have separate parts in drivers/bus and drivers/mfd, so just drop MFD API usage.
As a solution, we will use the platform device APIs directly to achieve the same as we had when using MFD APIs.
Signed-off-by: John Garry <john.garry@huawei.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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4b313ca7 |
| 19-Apr-2018 |
John Garry <john.garry@huawei.com> |
HISI LPC: Add Kconfig MFD_CORE dependency
For ACPI support of the HiSilicon LPC driver we depend on MFD_CORE config.
Currently the HiSi LPC Kconfig entry does not define this dependency, so add it.
HISI LPC: Add Kconfig MFD_CORE dependency
For ACPI support of the HiSilicon LPC driver we depend on MFD_CORE config.
Currently the HiSi LPC Kconfig entry does not define this dependency, so add it.
The reason for depending on MFD_CORE in the driver is that we model the LPC host as an MFD, in that a platform device will be created for each device on the bus.
We do this as we need to modify the resources of these derived platform devices, something which we should not do to the original devices created in the ACPI scan. Details in e0aa1563f894 ("HISI LPC: Add ACPI support").
Fixes: e0aa1563f894 ("HISI LPC: Add ACPI support") Reported-and-tested-by: Tan Xiaojun <tanxiaojun@huawei.com> Signed-off-by: John Garry <john.garry@huawei.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Revision tags: v4.16 |
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adf38bb0 |
| 21-Mar-2018 |
Zhichang Yuan <yuanzhichang@hisilicon.com> |
HISI LPC: Support the LPC host on Hip06/Hip07 with DT bindings
The low-pin-count (LPC) interface of Hip06/Hip07 accesses I/O port space of peripherals.
Implement the LPC host controller driver whic
HISI LPC: Support the LPC host on Hip06/Hip07 with DT bindings
The low-pin-count (LPC) interface of Hip06/Hip07 accesses I/O port space of peripherals.
Implement the LPC host controller driver which performs the I/O operations on the underlying hardware. We don't want to touch existing drivers such as ipmi-bt, so this driver applies the indirect-IO introduced in the previous patch after registering an indirect-IO node to the indirect-IO devices list which will be searched by the I/O accessors to retrieve the host-local I/O port.
The driver config is set as a bool instead of a tristate. The reason here is that, by the very nature of the driver providing a logical PIO range, it does not make sense to have this driver as a loadable module. Another more specific reason is that the Huawei D03 board which includes Hip06 SoC requires the LPC bus for UART console, so should be built in.
Tested-by: dann frazier <dann.frazier@canonical.com> Signed-off-by: Zou Rongrong <zourongrong@huawei.com> Signed-off-by: Zhichang Yuan <yuanzhichang@hisilicon.com> Signed-off-by: John Garry <john.garry@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Acked-by: Rob Herring <robh@kernel.org> # dts part
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